* [U-Boot] [PATCH v8 02/10] nds32: add NDS32 support into common header file
2011-04-11 2:46 [U-Boot] [PATCH v8 01/10] nds32: add header files support for nds32 Macpaul Lin
@ 2011-04-11 2:46 ` Macpaul Lin
2011-04-11 2:46 ` [U-Boot] [PATCH v8 03/10] nds32/core N1213: NDS32 N12 core family N1213 Macpaul Lin
` (7 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Macpaul Lin @ 2011-04-11 2:46 UTC (permalink / raw)
To: u-boot
Add NDS32 support into common header file.
Signed-off-by: Macpaul Lin <macpaul@andestech.com>
---
include/common.h | 4 ++++
1 files changed, 4 insertions(+), 0 deletions(-)
diff --git a/include/common.h b/include/common.h
index 54503ed..423bbd8 100644
--- a/include/common.h
+++ b/include/common.h
@@ -273,6 +273,10 @@ int setenv (char *, char *);
#ifdef CONFIG_I386 /* x86 version to be fixed! */
# include <asm/u-boot-i386.h>
#endif /* CONFIG_I386 */
+#ifdef CONFIG_NDS32
+# include <asm/mach-types.h>
+# include <asm/u-boot-nds32.h> /* NDS32 version to be fixed! */
+#endif /* CONFIG_NDS32 */
#ifdef CONFIG_AUTO_COMPLETE
int env_complete(char *var, int maxv, char *cmdv[], int maxsz, char *buf);
--
1.7.3.5
^ permalink raw reply related [flat|nested] 10+ messages in thread* [U-Boot] [PATCH v8 03/10] nds32/core N1213: NDS32 N12 core family N1213
2011-04-11 2:46 [U-Boot] [PATCH v8 01/10] nds32: add header files support for nds32 Macpaul Lin
2011-04-11 2:46 ` [U-Boot] [PATCH v8 02/10] nds32: add NDS32 support into common header file Macpaul Lin
@ 2011-04-11 2:46 ` Macpaul Lin
2011-04-11 2:46 ` [U-Boot] [PATCH v8 04/10] nds32/ag101: dev offset header of SoC ag101 Macpaul Lin
` (6 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Macpaul Lin @ 2011-04-11 2:46 UTC (permalink / raw)
To: u-boot
Add N1213 cpu core (N12 Core family) support for NDS32 arch.
This patch includes start.S for the initialize procedure of N1213.
NDS32 Core N1213 has the following hardware features.
Core:
- 16-/32-bit mixable instruction format
- 32 general-purpose 32-bit registers
- 8-stage pipeline
- Dynamic branch prediction
- 32/64/128/256 BTB
- Return address stack (RAS)
- Vector interrupts for internal/external
- 3 HW-level nested interruptions
- User and super-user mode support
- Memory-mapped I/O
- Address space up to 4GB
Memory Management Unit:
- TLB
- Optional hardware page table walker
- Two groups of page size support
Memory Subsystem:
- I & D cache
- I & D local memory (LM)
Bus Interface:
- Synchronous/Asynchronous AHB bus: 0, 1 or 2 ports
Start procedure:
start.S will start up the N1213 CPU core at first,
then jump to SoC dependent "lowlevel_init.S" and
"watchdog.S" to configure peripheral devices.
Signed-off-by: Macpaul Lin <macpaul@andestech.com>
---
arch/nds32/cpu/n1213/Makefile | 50 +++++
arch/nds32/cpu/n1213/start.S | 447 +++++++++++++++++++++++++++++++++++++++
arch/nds32/cpu/n1213/u-boot.lds | 68 ++++++
3 files changed, 565 insertions(+), 0 deletions(-)
create mode 100644 arch/nds32/cpu/n1213/Makefile
create mode 100644 arch/nds32/cpu/n1213/start.S
create mode 100644 arch/nds32/cpu/n1213/u-boot.lds
diff --git a/arch/nds32/cpu/n1213/Makefile b/arch/nds32/cpu/n1213/Makefile
new file mode 100644
index 0000000..111d14f
--- /dev/null
+++ b/arch/nds32/cpu/n1213/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# Copyright (C) 2011 Andes Technology Corporation
+# Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+# Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(CPU).o
+
+START = start.o
+
+SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
+START := $(addprefix $(obj),$(START))
+
+all: $(obj).depend $(START) $(LIB)
+
+$(LIB): $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/arch/nds32/cpu/n1213/start.S b/arch/nds32/cpu/n1213/start.S
new file mode 100644
index 0000000..b04f3a5
--- /dev/null
+++ b/arch/nds32/cpu/n1213/start.S
@@ -0,0 +1,447 @@
+/*
+ * Andesboot - Startup Code for Whitiger core
+ *
+ * Copyright (C) 2006 Andes Technology Corporation
+ * Copyright (C) 2006 Shawn Lin <nobuhiro@andestech.com>
+ * Copyright (C) 2011 Macpaul <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <common.h>
+#include <version.h>
+
+/*
+ * Jump vector table for EVIC mode
+ */
+#define ENA_DCAC 2UL
+#define DIS_DCAC ~ENA_DCAC
+#define ICAC_MEM_KBF_ISET (0x07) ! I Cache sets per way
+#define ICAC_MEM_KBF_IWAY (0x07<<3) ! I cache ways
+#define ICAC_MEM_KBF_ISZ (0x07<<6) ! I cache line size
+#define DCAC_MEM_KBF_DSET (0x07) ! D Cache sets per way
+#define DCAC_MEM_KBF_DWAY (0x07<<3) ! D cache ways
+#define DCAC_MEM_KBF_DSZ (0x07<<6) ! D cache line size
+
+#define PSW $ir0
+#define EIT_INTR_PSW $ir1 ! interruption $PSW
+#define EIT_PREV_IPSW $ir2 ! previous $IPSW
+#define EIT_IVB $ir3 ! intr vector base address
+#define EIT_EVA $ir4 ! MMU related Exception Virtual Address register */
+#define EIT_PREV_EVA $ir5 ! previous $eva
+#define EIT_ITYPE $ir6 ! interruption type
+#define EIT_PREV_ITYPE $ir7 ! prev intr type
+#define EIT_MACH_ERR $ir8 ! machine error log
+#define EIT_INTR_PC $ir9 ! Interruption PC
+#define EIT_PREV_IPC $ir10 ! previous $IPC
+#define EIT_OVL_INTR_PC $ir11 ! overflow interruption PC
+#define EIT_PREV_P0 $ir12 ! prev $P0
+#define EIT_PREV_P1 $ir13 ! prev $p1
+#define CR_ICAC_MEM $cr1 ! I-cache/memory config reg
+#define CR_DCAC_MEM $cr2 ! D-cache/memory config reg
+#define MR_CAC_CTL $mr8
+
+.globl _start
+
+_start: b reset
+ b tlb_fill
+ b tlb_not_present
+ b tlb_misc
+ b tlb_vlpt_miss
+ b cache_parity_error
+ b debug
+ b general_exception
+ b internal_interrupt ! H0I
+ b internal_interrupt ! H1I
+ b internal_interrupt ! H2I
+ b internal_interrupt ! H3I
+ b internal_interrupt ! H4I
+ b internal_interrupt ! H5I
+
+ .balign 16
+
+!========================================================================
+! Andesboot Startup Code (reset vector)
+!
+! 1. bootstrap
+! 1.1 reset - start of Andesboot
+! 1.2 to superuser mode - as is when reset
+! 1.4 Do lowlevel_init
+! - (this will jump out to lowlevel_init.S in SoC)
+! - (lowlevel_init)
+! 1.3 Turn off watchdog timer
+! - (this will jump out to watchdog.S in SoC)
+! - (turnoff_watchdog)
+! 2. Do critical init when reboot (not from mem)
+! 3. Relocate andesboot to ram
+! 4. Setup stack
+! 5. Jump to second stage (start_andesboot)
+!========================================================================
+
+! Note: TEXT_BASE is defined by the (board-dependent) linker script
+_TEXT_BASE:
+ .word CONFIG_SYS_TEXT_BASE
+
+.globl _andesboot_start
+_andesboot_start:
+ .word _start
+
+! Note: andesboot_end is defined by the (board-dependent) linker script
+.globl _andesboot_end
+_andesboot_end:
+ .word andesboot_end
+
+! _andesboot_real_end is the first usable RAM address behind Andesboot
+! and the various stacks
+.globl _andesboot_real_end
+_andesboot_real_end:
+ .word 0x0badc0de
+
+!=============================================
+! The bootstrap code of Andesboot
+!=============================================
+
+reset:
+
+load_lli:
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+ jal load_lowlevel_init
+ jral $p0
+#endif
+
+! Set the Whitiger core to superuser mode
+! According to spec, it is already when reset
+
+turnoff_wtdog:
+#ifndef CONFIG_SKIP_TRUNOFF_WATCHDOG
+ jal load_turnoff_watchdog
+ jral $p0
+#endif
+
+! Do CPU critical regs init only at reboot, not when booting from ram
+#ifdef CONFIG_INIT_CRITICAL
+ bal cpu_init_crit ! Do CPU critical regs init
+#endif
+
+ .align 2
+relocate:
+ ! relocate andesboot to RAM
+ jal 2f
+ !la $r0, _start ! $r0 = source start addr
+ !l.w $r2, _andesboot_start ! Andesboot start address
+ !l.w $r3, _andesboot_end ! Andesboot end address
+ !sub $r2, $r3, $r2 ! $r2 = size of Andesboot
+ !l.w $r1, _TEXT_BASE ! $r1 = destination start addr
+ move $r0, $lp
+ la $p0, _start
+ la $p1, relocate+4
+ sub $p0, $p1, $p0
+ sub $r0, $r0, $p0
+
+ la $p0, _andesboot_end
+ sub $p0, $p0, $p1
+ move $r3, $lp
+ lw $r3, [$r3+$p0] ! _andesboot_end
+ addi $p0, $p0, -4
+ move $r2, $lp
+ lw $r2, [$r2+$p0] ! _andesboot_start
+ sub $r2, $r3, $r2
+ addi $p0, $p0, -4
+ move $r1, $lp
+ lw $r1, [$r1+$p0] ! _TEXT_BASE
+
+ ! $r0 = source address
+ ! $r1 = destination address
+ ! $r2 = size to copy
+copy_loop:
+ lmw.bim $r3, [$r0], $r10
+ smw.bim $r3, [$r1], $r10
+ addi $r2, $r2, -32
+ bgez $r2, copy_loop
+
+ ! Set up the stack
+ l.w $p0, _andesboot_end ! Defined by board linker script
+ li $p1, CONFIG_STACKSIZE ! (128*1024) defined in config.h
+ add $sp, $p0, $p1
+
+ bal flib_init_bss_memory
+
+ ! Jump to start_andesboot (2nd phase)
+ l.w $p0, __start_andesboot
+ br $p0
+
+__start_andesboot: .word start_andesboot
+
+!=========================================================================
+! Initialize CPU critical registers
+!
+! 1. Setup control registers
+! 1.1 Mask all IRQs
+! 1.2 Flush cache and TLB
+! 1.3 Disable MMU and cache
+! 2. Setup memory timing
+!=========================================================================
+
+cpu_init_crit:
+ !push ra
+ move $r0, $lp
+ ! Disable Interrupts by clear GIE in $PSW reg
+ setgie.d
+
+ ! Flush caches and TLB
+
+ ! Invalidate caches
+ bal invalidate_icac
+ bal invalidate_dcac
+
+ ! Flush TLB
+ mfsr $p0, $MMU_CFG
+ andi $p0, $p0, 0x3 ! MMPS
+ li $p1, 0x2 ! TLB MMU
+ bne $p0, $p1, 1f
+ tlbop FlushAll ! Flush TLB
+
+1:
+ ! Disable MMU, Dcache
+ ! Whitiger is MMU disabled when reset
+ ! Disable the D$
+ mfsr $p0, MR_CAC_CTL ! Get the $CACHE_CTL reg
+ li $p1, DIS_DCAC
+ and $p0, $p0, $p1 ! Set DC_EN bit
+ mtsr $p0, MR_CAC_CTL ! write back the $CACHE_CTL reg
+ isb
+
+ ! RAM is initialized in the dram_init()(board/nds32/cpe.c)
+ ! Remove the memsetup.S in the board directory.
+ !pop ra
+
+ move $lp, $r0
+2:
+ ret
+
+flib_init_bss_memory:
+ smw.adm $r4, [$sp], $r6, #0x1
+
+ la $r4, __bss_start
+ la $r5, __bss_end
+ move $r6, #0
+1:
+ swi.p $r6, [$r4], #4
+ blt $r4, $r5, 1b ! Check if done..
+
+ lmw.bim $r4, [$sp], $r6, #0x1
+ ret
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+load_lowlevel_init:
+ la $r6, lowlevel_init
+ la $r7, load_lli + 4
+ sub $p0, $r6, $r7
+ add $p0, $p0, $lp
+ret
+#endif
+
+#ifndef CONFIG_SKIP_TRUNOFF_WATCHDOG
+load_turnoff_watchdog:
+ la $r6, turnoff_watchdog
+ la $r7, turnoff_wtdog + 4
+ sub $p0, $r6, $r7
+ add $p0, $p0, $lp
+ret
+#endif
+
+
+!=======================================================
+! Invalidate I$
+!=======================================================
+invalidate_icac:
+ mfsr $t0, CR_ICAC_MEM ! read $cr1(I CAC/MEM cfg. reg.) configuration
+ andi $p0, $t0, ICAC_MEM_KBF_ISZ ! Get the ISZ field
+ beqz $p0, end_flush_icache ! if $p0=0, then no I CAC existed
+ srli $p0, $p0, 6 ! get $p0 the index of I$ block
+ addi $t1, $p0, 2 ! $t1= bit width of I cache line size(ISZ)
+ li $t4, 1
+ sll $t5, $t4, $t1 ! get $t5 cache line size
+ andi $p1, $t0, ICAC_MEM_KBF_ISET ! get the ISET field
+ addi $t2, $p1, 6 ! $t2= bit width of ISET
+ andi $p1, $t0, ICAC_MEM_KBF_IWAY ! get bitfield of Iway
+ srli $p1, $p1, 3
+ addi $p1, $p1, 1 ! then $p1 is I way number
+ add $t3, $t2, $t1 ! SHIFT
+ sll $p1, $p1, $t3 ! GET the total cache size
+ICAC_LOOP:
+ sub $p1, $p1, $t5
+ cctl $p1, L1I_IX_INVAL
+ bnez $p1, ICAC_LOOP
+end_flush_icache:
+ ret
+
+!=======================================================
+! Invalidate D$
+!=======================================================
+invalidate_dcac:
+ mfsr $t0, CR_DCAC_MEM ! read $cr2(D CAC/MEM cfg. reg.) configuration
+ andi $p0, $t0, DCAC_MEM_KBF_DSZ ! Get the DSZ field
+ beqz $p0, end_flush_dcache ! if $p0=0, then no D CAC existed
+ srli $p0, $p0, 6 ! get $p0 the index of D$ block
+ addi $t1, $p0, 2 ! $t1= bit width of D cache line size(DSZ)
+ li $t4, 1
+ sll $t5, $t4, $t1 ! get $t5 cache line size
+ andi $p1, $t0, DCAC_MEM_KBF_DSET ! get the DSET field
+ addi $t2, $p1, 6 ! $t2= bit width of DSET
+ andi $p1, $t0, DCAC_MEM_KBF_DWAY ! get bitfield of D way
+ srli $p1, $p1, 3
+ addi $p1, $p1, 1 ! then $p1 is D way number
+ add $t3, $t2, $t1 ! SHIFT
+ sll $p1, $p1, $t3 ! GET the total cache size
+DCAC_LOOP:
+ sub $p1, $p1, $t5
+ cctl $p1, L1D_IX_INVAL
+ bnez $p1, DCAC_LOOP
+end_flush_dcache:
+ ret
+
+!========================================================================
+! Interrupt handling
+!========================================================================
+
+/*
+ * exception handlers
+ */
+ .align 5
+
+ .macro SAVE_ALL
+ ! FIXME: Other way to get PC?
+ ! FIXME: Update according to the newest spec!!
+1: la $r28, 1
+ push $r28
+ mfsr $r28, PSW ! $PSW
+ push $r28
+ mfsr $r28, EIT_EVA ! $ir1 $EVA
+ push $r28
+ mfsr $r28, EIT_ITYPE ! $ir2 $ITYPE
+ push $r28
+ mfsr $r28, EIT_MACH_ERR ! $ir3 Mach Error
+ push $r28
+ mfsr $r28, EIT_INTR_PSW ! $ir5 $IPSW
+ push $r28
+ mfsr $r28, EIT_PREV_IPSW ! $ir6 prev $IPSW
+ push $r28
+ mfsr $r28, EIT_PREV_EVA ! $ir7 prev $EVA
+ push $r28
+ mfsr $r28, EIT_PREV_ITYPE ! $ir8 prev $ITYPE
+ push $r28
+ mfsr $r28, EIT_INTR_PC ! $ir9 Interruption PC
+ push $r28
+ mfsr $r28, EIT_PREV_IPC ! $ir10 prev INTR_PC
+ push $r28
+ mfsr $r28, EIT_OVL_INTR_PC ! $ir11 Overflowed INTR_PC
+ push $r28
+ mfusr $r28, $d1.lo
+ push $r28
+ mfusr $r28, $d1.hi
+ push $r28
+ mfusr $r28, $d0.lo
+ push $r28
+ mfusr $r28, $d0.hi
+ push $r28
+ pushm $r0,$r30 /* we will also store $sp-$r31, ra-$r30, $gp-$r29, $r28-$fp */
+ addi $sp, $sp, -4 ! make room for implicit pt_regs parameters
+ .endm
+
+ .align 5
+tlb_fill:
+ SAVE_ALL
+ move $r0, $sp ! To get the kernel stack
+ li $r1, 1 ! Determine interruption type
+ bal do_interruption
+
+ .align 5
+tlb_not_present:
+ SAVE_ALL
+ move $r0, $sp ! To get the kernel stack
+ li $r1, 2 ! Determine interruption type
+ bal do_interruption
+
+ .align 5
+tlb_misc:
+ SAVE_ALL
+ move $r0, $sp ! To get the kernel stack
+ li $r1, 3 ! Determine interruption type
+ bal do_interruption
+
+ .align 5
+tlb_vlpt_miss:
+ SAVE_ALL
+ move $r0, $sp ! To get the kernel stack
+ li $r1, 4 ! Determine interruption type
+ bal do_interruption
+
+ .align 5
+cache_parity_error:
+ SAVE_ALL
+ move $r0, $sp ! To get the kernel stack
+ li $r1, 5 ! Determine interruption type
+ bal do_interruption
+
+ .align 5
+debug:
+ SAVE_ALL
+ move $r0, $sp ! To get the kernel stack
+ li $r1, 6 ! Determine interruption type
+ bal do_interruption
+
+ .align 5
+general_exception:
+ SAVE_ALL
+ move $r0, $sp ! To get the kernel stack
+ li $r1, 7 ! Determine interruption type
+ bal do_interruption
+
+ .align 5
+internal_interrupt:
+ SAVE_ALL
+ move $r0, $sp ! To get the kernel stack
+ li $r1, 8 ! Determine interruption type
+ bal do_interruption
+
+ .align 5
+
+!===========================================
+!void reset_cpu(ulong addr);
+! $r0: input address to jump to
+!===========================================
+.globl reset_cpu
+reset_cpu:
+! No need to disable MMU because we never enable it!
+
+ bal invalidate_icac
+ bal invalidate_dcac
+ mfsr $p0, $MMU_CFG
+ andi $p0, $p0, 0x3 ! MMPS
+ li $p1, 0x2 ! TLB MMU
+ bne $p0, $p1, 1f
+ tlbop FlushAll ! Flush TLB
+1:
+ mfsr $p0, MR_CAC_CTL ! Get the $CACHE_CTL reg
+ li $p1, DIS_DCAC
+ and $p0, $p0, $p1 ! Clear the DC_EN bit
+ mtsr $p0, MR_CAC_CTL ! Write back the $CACHE_CTL reg
+ br $r0 ! Jump to the input address
diff --git a/arch/nds32/cpu/n1213/u-boot.lds b/arch/nds32/cpu/n1213/u-boot.lds
new file mode 100644
index 0000000..824d05d
--- /dev/null
+++ b/arch/nds32/cpu/n1213/u-boot.lds
@@ -0,0 +1,68 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-nds32", "elf32-nds32", "elf32-nds32")
+OUTPUT_ARCH(nds32)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0x00000000;
+
+ . = ALIGN(4);
+ .text :
+ {
+ arch/nds32/cpu/n1213/start.o (.text)
+ *(.text)
+ }
+
+ . = ALIGN(4);
+ .rodata : { *(.rodata) }
+
+ . = ALIGN(4);
+ .data : { *(.data) }
+
+ . = ALIGN(4);
+ .got : { *(.got) }
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ __bss_start = .;
+ .bss : { *(.bss) }
+ __bss_end = .;
+
+ . = ALIGN(4);
+ .rela.text : { *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) }
+
+ andesboot_end = .;
+
+ . = 0x02000000;
+ .u_boot_ohci_data_st : { *(.u_boot_ohci_data_st) }
+}
--
1.7.3.5
^ permalink raw reply related [flat|nested] 10+ messages in thread* [U-Boot] [PATCH v8 04/10] nds32/ag101: dev offset header of SoC ag101
2011-04-11 2:46 [U-Boot] [PATCH v8 01/10] nds32: add header files support for nds32 Macpaul Lin
2011-04-11 2:46 ` [U-Boot] [PATCH v8 02/10] nds32: add NDS32 support into common header file Macpaul Lin
2011-04-11 2:46 ` [U-Boot] [PATCH v8 03/10] nds32/core N1213: NDS32 N12 core family N1213 Macpaul Lin
@ 2011-04-11 2:46 ` Macpaul Lin
2011-04-11 2:47 ` [U-Boot] [PATCH v8 05/10] nds32/ag101: lowlevel_init.S of ag101 Macpaul Lin
` (5 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Macpaul Lin @ 2011-04-11 2:46 UTC (permalink / raw)
To: u-boot
Add header file of device offset support for SoC ag101.
SoC ag101 is the first chip using NDS32 N1213 cpu core.
Note:
Ag101 is actually use ftsdmc021 instead of ftsdmc020
as dram controller, which is probably wrong in the datasheet.
Signed-off-by: Macpaul Lin <macpaul@andestech.com>
---
arch/nds32/include/asm/arch-ag101/ag101.h | 68 +++++++++++++++++++++++++++++
1 files changed, 68 insertions(+), 0 deletions(-)
create mode 100644 arch/nds32/include/asm/arch-ag101/ag101.h
diff --git a/arch/nds32/include/asm/arch-ag101/ag101.h b/arch/nds32/include/asm/arch-ag101/ag101.h
new file mode 100644
index 0000000..011989a
--- /dev/null
+++ b/arch/nds32/include/asm/arch-ag101/ag101.h
@@ -0,0 +1,68 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Nobuhiro Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __AG101_H
+#define __AG101_H
+
+/* Hardware register bases */
+#define CONFIG_FTAHBC020S_BASE 0x90100000 /* AHB Controller */
+#define CONFIG_FTSMC020_BASE 0x90200000 /* Static Memory Controller (SRAM) */
+#define CONFIG_FTSDMC021_BASE 0x90300000 /* FTSDMC020/021 SDRAM Controller */
+#define CONFIG_FTDMAC020_BASE 0x90400000 /* DMA Controller */
+#define CONFIG_FTAPBBRG020S_01_BASE 0x90500000 /* AHB-to-APB Bridge */
+#define CONFIG_FTLCDC100_BASE 0x90600000 /* LCD Controller */
+#define CONFIG_RESERVED_01_BASE 0x90700000 /* Reserved */
+#define CONFIG_RESERVED_02_BASE 0x90800000 /* Reserved */
+#define CONFIG_FTMAC100_BASE 0x90900000 /* Ethernet */
+#define CONFIG_EXT_USB_HOST_BASE 0x90A00000 /* External USB host */
+#define CONFIG_USB_DEV_BASE 0x90B00000 /* USB Device */
+#define CONFIG_EXT_AHBPCIBRG_BASE 0x90C00000 /* External AHB-to-PCI Bridge (FTPCI100 not exist in ag101) */
+#define CONFIG_RESERVED_03_BASE 0x90D00000 /* Reserved */
+#define CONFIG_EXT_AHBAPBBRG_BASE 0x90E00000 /* External AHB-to-APB Bridger (FTAPBBRG020S_02) */
+#define CONFIG_EXT_AHBSLAVE01_BASE 0x90F00000 /* External AHB slave1 (LCD) */
+
+#define CONFIG_EXT_AHBSLAVE02_BASE 0x92000000 /* External AHB slave2 (FUSBH200) */
+
+/* DEBUG LED */
+#define CONFIG_DEBUG_LED 0x902FFFFC /* Debug LED */
+
+/* APB Device definitions */
+#define CONFIG_FTPMU010_BASE 0x98100000 /* Power Management Unit */
+#define CONFIG_FTUART010_01_BASE 0x98300000 /* BT UART 2/IrDA (UART 01 in Linux) */
+#define CONFIG_FTTMR010_BASE 0x98400000 /* Counter/Timers */
+#define CONFIG_FTWDT010_BASE 0x98500000 /* Watchdog Timer */
+#define CONFIG_FTRTC010_BASE 0x98600000 /* Real Time Clock */
+#define CONFIG_FTGPIO010_BASE 0x98700000 /* GPIO */
+#define CONFIG_FTINTC010_BASE 0x98800000 /* Interrupt Controller */
+#define CONFIG_FTIIC010_BASE 0x98A00000 /* I2C */
+#define CONFIG_RESERVED_04_BASE 0x98C00000 /* Reserved */
+#define CONFIG_FTCFC010_BASE 0x98D00000 /* Compat Flash Controller */
+#define CONFIG_FTSDC010_BASE 0x98E00000 /* SD Controller */
+
+#define CONFIG_FTSSP010_02_BASE 0x99400000 /* Synchronous Serial Port Controller (SSP) I2S/AC97 */
+#define CONFIG_FTUART010_02_BASE 0x99600000 /* ST UART ? SSP 02 (UART 02 in Linux) */
+
+/* The following address was not defined in Linux */
+#define CONFIG_FTUART010_03_BASE 0x98200000 /* FF UART 3 */
+#define CONFIG_FTSSP010_01_BASE 0x98B00000 /* Synchronous Serial Port Controller (SSP) 01 */
+#define CONFIG_IRDA_BASE 0x98900000 /* IrDA */
+#define CONFIG_PMW_BASE 0x99100000 /* PWM - Pulse Width Modulator Controller */
+
+#endif /* __AG101_H */
--
1.7.3.5
^ permalink raw reply related [flat|nested] 10+ messages in thread* [U-Boot] [PATCH v8 05/10] nds32/ag101: lowlevel_init.S of ag101
2011-04-11 2:46 [U-Boot] [PATCH v8 01/10] nds32: add header files support for nds32 Macpaul Lin
` (2 preceding siblings ...)
2011-04-11 2:46 ` [U-Boot] [PATCH v8 04/10] nds32/ag101: dev offset header of SoC ag101 Macpaul Lin
@ 2011-04-11 2:47 ` Macpaul Lin
2011-04-11 2:47 ` [U-Boot] [PATCH v8 06/10] nds32/ag101: cpu and init funcs of SoC ag101 Macpaul Lin
` (4 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Macpaul Lin @ 2011-04-11 2:47 UTC (permalink / raw)
To: u-boot
lowlevel_init.S is a peripheral initial procedure of ag101.
It configures onboard dram, clock, and power settings.
It also prepars the dram environment before moving u-boot
from rom and flash into dram.
This version of lowlevel_init.S also replace hardcode value
by MARCO defines from the GPL version andesboot for better
code quality.
Signed-off-by: Macpaul Lin <macpaul@andestech.com>
---
ChangeLog from v1-v4:
- Code clean up and formatting style.
ChangeLog from v5-v6
- Change hard code value into MARCO definitions.
- ftsmc010
- Fix FTSMC020_TPR_AT2 from 1 to 3 (0xff3ff)
- ftsdmc021
- Fix hardcoded address of CR1, CR2, TR1, TR2, BANK0 registers.
- Fix the default configuration value of FTSDMC and FTSMC controller.
- Remove some ftpmu010 and flash probe code to C functions.
arch/nds32/cpu/n1213/ag101/lowlevel_init.S | 160 ++++++++++++++++++++++++++++
1 files changed, 160 insertions(+), 0 deletions(-)
create mode 100644 arch/nds32/cpu/n1213/ag101/lowlevel_init.S
diff --git a/arch/nds32/cpu/n1213/ag101/lowlevel_init.S b/arch/nds32/cpu/n1213/ag101/lowlevel_init.S
new file mode 100644
index 0000000..96969ba
--- /dev/null
+++ b/arch/nds32/cpu/n1213/ag101/lowlevel_init.S
@@ -0,0 +1,160 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+.text
+
+#include <common.h>
+#include <config.h>
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+.globl lowlevel_init
+lowlevel_init:
+ move $r10, $lp
+ jal mem_init
+ jal remap
+
+ ret $r10
+
+mem_init:
+ move $r11, $lp
+
+ /*
+ * mem_init:
+ * There are 2 bank connected to FTSMC020 on AG101
+ * BANK0: FLASH/ROM (SW5, J16), BANK1: OnBoard SDRAM.
+ * we need to set onboard SDRAM before remap and relocation.
+ */
+ li $r0, (CONFIG_FTSMC020_BASE+FTSMC020_BANK0_CR)
+ li $r1, (FTSMC020_BANK1_CONFIG) ! 0x10000052
+ swi $r1, [$r0]
+ li $r1, (FTSMC020_BANK1_TIMING) ! 0x00151151
+ swi $r1, [$r0+FTSMC020_BANK0_TPR]
+
+ /*
+ * config AHB Controller
+ */
+ li $r0, (CONFIG_FTAHBC020S_BASE + FTAHBC020S_SLAVE_BSR_6)
+ li $r1, (CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6)
+ swi $r1, [$r0]
+
+ /*
+ * config PMU
+ */
+ li $r0, (CONFIG_FTPMU010_BASE + FTPMU010_PDLLCR0)
+ lwi $r1, [$r0]
+ ! ftpmu010_dlldis_disable, must do it in lowleve_init
+ li $r2, FTPMU010_PDLLCR0_DLLDIS ! 0x00010000
+ or $r1, $r1, $r2
+ swi $r1, [$r0]
+
+ /*
+ * config SDRAM controller
+ */
+ li $r0, (CONFIG_FTSDMC021_BASE)
+ li $r1, (CONFIG_SYS_FTSDMC021_TP1) ! 0x00011312
+ swi $r1, [$r0]
+ li $r1, (CONFIG_SYS_FTSDMC021_TP2) ! 0x00480180
+ swi $r1, [$r0+FTSDMC021_OFFSET_TP2]
+ li $r1, (CONFIG_SYS_FTSDMC021_CR1) ! 0x00002326
+ swi $r1, [$r0+FTSDMC021_OFFSET_CR1]
+ li $r1, (FTSDMC021_CR2_IPREC) ! 0x00000010
+ swi $r1, [$r0+FTSDMC021_OFFSET_CR2]
+1:
+ lwi $r1, [$r0+FTSDMC021_OFFSET_CR2]
+ andi $r1, $r1, (CONFIG_SYS_FTSDMC021_CR2) ! 0x1C
+ bnez $r1, 1b
+
+ li $r1, (FTSDMC021_CR2_ISMR) ! 0x00000004
+ swi $r1, [$r0+FTSDMC021_OFFSET_CR2]
+2:
+ lwi $r1, [$r0+FTSDMC021_OFFSET_CR2]
+ bnez $r1, 2b
+
+ li $r1, (FTSDMC021_CR2_IREF) ! 0x00000008
+ swi $r1, [$r0+FTSDMC021_OFFSET_CR2]
+3:
+ lwi $r1, [$r0+FTSDMC021_OFFSET_CR2]
+ bnez $r1, 3b
+
+ move $lp, $r11
+ ret
+
+remap:
+ move $r11, $lp
+#ifdef __NDS32_N1213_43U1H__ /* AG101 */
+ bal 2f
+relo_base:
+ move $r0, $lp
+#else
+relo_base:
+ mfusr $r0, $pc
+#endif
+
+ /*
+ * relocation, copy ROM code to SDRAM (current at 0x10000000)
+ */
+ li $r4, CONFIG_SYS_RELO_ADDR ! 0x10000000
+ li $r5, 0x0
+ la $r1, relo_base
+ sub $r2, $r0, $r1
+ sethi $r6, hi20(andesboot_end)
+ ori $r6, $r6, lo12(andesboot_end)
+ add $r6, $r6, $r2
+1:
+ lwi $r7, [$r5]
+ swi $r7, [$r4]
+ addi $r5, $r5, #4
+ addi $r4, $r4, #4
+ blt $r5, $r6, 1b
+
+ /*
+ * Remapping
+ */
+ li $r0, (CONFIG_FTSDMC021_BASE + FTSDMC021_OFFSET_TP1)
+ li $r1, (CONFIG_SYS_FTSDMC021_BANK0_BSR) ! 0x00001100
+ swi $r1, [$r0+FTSDMC021_OFFSET_BANK0_BSR]
+ li $r1, 0x0
+ swi $r1, [$r0+FTSDMC021_OFFSET_BANK1_BSR]
+ swi $r1, [$r0+FTSDMC021_OFFSET_BANK2_BSR]
+ swi $r1, [$r0+FTSDMC021_OFFSET_BANK3_BSR]
+ li $r1, (FTSDMC021_BANK_ENABLE) ! 0x00001000
+ swi $r1, [$r0+FTSDMC021_OFFSET_BANK0_BSR]
+
+ li $r0, (CONFIG_FTAHBC020S_BASE + FTAHBC020S_CR)
+ lwi $r1, [$r0]
+ ori $r1, $r1, FTAHBC020S_CR_REMAP ! 0x1
+ swi $r1, [$r0]
+
+ li $r0, (CONFIG_FTSMC020_BASE)
+
+ move $lp, $r11
+2:
+ ret
+
+.globl show_led
+show_led:
+ li $r8, (CONFIG_DEBUG_LED)
+ swi $r7, [$r8]
+ ret
+#endif
--
1.7.3.5
^ permalink raw reply related [flat|nested] 10+ messages in thread* [U-Boot] [PATCH v8 06/10] nds32/ag101: cpu and init funcs of SoC ag101
2011-04-11 2:46 [U-Boot] [PATCH v8 01/10] nds32: add header files support for nds32 Macpaul Lin
` (3 preceding siblings ...)
2011-04-11 2:47 ` [U-Boot] [PATCH v8 05/10] nds32/ag101: lowlevel_init.S of ag101 Macpaul Lin
@ 2011-04-11 2:47 ` Macpaul Lin
2011-04-11 2:47 ` [U-Boot] [PATCH v8 07/10] nds32/lib: add generic funcs in NDS32 lib Macpaul Lin
` (3 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Macpaul Lin @ 2011-04-11 2:47 UTC (permalink / raw)
To: u-boot
Add main function of SoC ag101 based on NDS32 n1213 core.
cpu.c
According to the bootstrap procedure in n1213 Core,
to turn off watchdog timer is suggested after the
cpu is in superuser mdoe.
1. bootstrap
1.1 reset - start of Andesboot
1.2 to superuser mode - as is when reset
1.3 Turn off watchdog timer
If you take look into the start.S in n1213, you will find that
system will turn off watchdog after start.S has been retunred
from lowlevel_init.
Since the watchdog device is depends on the SoC is choosed.
It should be belonged to the SoC (ag101) folder.
watchdog.S:
If you've ran another bootloader before u-boot was started
the watchdog might have been enabled already.
Signed-off-by: Macpaul Lin <macpaul@andestech.com>
---
Changes for v5-v6:
- Split watchdog.S from lowlevel_init.S.
- Fix hardware reset by using watchdog reset in do_reset() in cpu.c.
- reset_cpu was remove inside do_reset().
Changes for v7:
- clean up.
arch/nds32/cpu/n1213/ag101/Makefile | 58 +++++++++
arch/nds32/cpu/n1213/ag101/cpu.c | 207 +++++++++++++++++++++++++++++++++
arch/nds32/cpu/n1213/ag101/timer.c | 204 ++++++++++++++++++++++++++++++++
arch/nds32/cpu/n1213/ag101/watchdog.S | 48 ++++++++
4 files changed, 517 insertions(+), 0 deletions(-)
create mode 100644 arch/nds32/cpu/n1213/ag101/Makefile
create mode 100644 arch/nds32/cpu/n1213/ag101/cpu.c
create mode 100644 arch/nds32/cpu/n1213/ag101/timer.c
create mode 100644 arch/nds32/cpu/n1213/ag101/watchdog.S
diff --git a/arch/nds32/cpu/n1213/ag101/Makefile b/arch/nds32/cpu/n1213/ag101/Makefile
new file mode 100644
index 0000000..e96b1e4
--- /dev/null
+++ b/arch/nds32/cpu/n1213/ag101/Makefile
@@ -0,0 +1,58 @@
+#
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+#
+# Copyright (C) 2011 Andes Technology Corporation
+# Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+# Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(SOC).o
+
+COBJS-y := cpu.o timer.o
+
+ifndef CONFIG_SKIP_LOWLEVEL_INIT
+SOBJS := lowlevel_init.o
+endif
+
+ifndef CONFIG_SKIP_TRUNOFF_WATCHDOG
+SOBJS += watchdog.o
+endif
+
+SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y))
+
+all: $(obj).depend $(LIB)
+
+$(LIB): $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/arch/nds32/cpu/n1213/ag101/cpu.c b/arch/nds32/cpu/n1213/ag101/cpu.c
new file mode 100644
index 0000000..8e7eb0a
--- /dev/null
+++ b/arch/nds32/cpu/n1213/ag101/cpu.c
@@ -0,0 +1,207 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* CPU specific code */
+#include <common.h>
+#include <command.h>
+#include <watchdog.h>
+#include <asm/cache.h>
+
+#include <faraday/ftwdt010_wdt.h>
+
+/* setup up stack if necessary */
+/* it makes no sense to use the caches if the MMU also isn't used */
+void cpu_init(void)
+{
+ _andesboot_real_end = _andesboot_end + CONFIG_STACKSIZE;
+}
+
+/*
+ * cleanup_before_linux() is called just before we call linux
+ * it prepares the processor for linux
+ *
+ * we disable interrupt and caches.
+ */
+int cleanup_before_linux(void)
+{
+#ifdef CONFIG_MMU
+ unsigned long i;
+#endif
+
+ disable_interrupts();
+
+#ifdef CONFIG_MMU
+ /* turn off I/D-cache */
+ icache_disable();
+ dcache_disable();
+
+ /* flush I/D-cache */
+ invalidate_icac();
+ invalidate_dcac();
+#endif
+
+ return 0;
+}
+
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ disable_interrupts();
+
+ /*
+ * reset to the base addr of andesboot.
+ * currently no ROM loader at addr 0.
+ * do not use reset_cpu(0);
+ */
+#ifdef CONFIG_FTWDT010_WATCHDOG
+ /*
+ * workaround: if we use CONFIG_HW_WATCHDOG with ftwdt010, will lead
+ * automatic hardware reset when booting Linux.
+ * Please do not use CONFIG_HW_WATCHDOG and WATCHDOG_RESET() here.
+ */
+ ftwdt010_wdt_reset();
+ while (1)
+ ;
+#endif /* CONFIG_FTWDT010_WATCHDOG */
+
+ /*NOTREACHED*/
+}
+
+static inline unsigned long CACHE_LINE_SIZE(enum cache_t cache)
+{
+ if (cache == ICACHE)
+ return 8 << (((GET_ICM_CFG() & ICM_CFG_MSK_ISZ) \
+ >> ICM_CFG_OFF_ISZ) - 1);
+ else
+ return 8 << (((GET_DCM_CFG() & DCM_CFG_MSK_DSZ) \
+ >> DCM_CFG_OFF_DSZ) - 1);
+}
+
+void dcache_flush_range(unsigned long start, unsigned long end)
+{
+ unsigned long line_size;
+
+ line_size = CACHE_LINE_SIZE(DCACHE);
+
+ while (end > start) {
+ __asm__ volatile ("\n\tcctl %0, L1D_VA_WB" : : "r"(start));
+ __asm__ volatile ("\n\tcctl %0, L1D_VA_INVAL" : : "r"(start));
+ start += line_size;
+ }
+}
+
+void icache_inval_range(unsigned long start, unsigned long end)
+{
+ unsigned long line_size;
+
+ line_size = CACHE_LINE_SIZE(ICACHE);
+ while (end > start) {
+ __asm__ volatile ("\n\tcctl %0, L1I_VA_INVAL" : : "r"(start));
+ start += line_size;
+ }
+}
+
+void flush_cache(unsigned long addr, unsigned long size)
+{
+ dcache_flush_range(addr , addr + size);
+ icache_inval_range(addr , addr + size);
+}
+
+void icache_enable(void)
+{
+ __asm__ __volatile__ (
+ "mfsr $p0, $mr8\n\t"
+ "ori $p0, $p0, 0x01\n\t"
+ "mtsr $p0, $mr8\n\t"
+ "isb\n\t"
+ );
+}
+
+void icache_disable(void)
+{
+ __asm__ __volatile__ (
+ "mfsr $p0, $mr8\n\t"
+ "li $p1, ~0x01\n\t"
+ "and $p0, $p0, $p1\n\t"
+ "mtsr $p0, $mr8\n\t"
+ "isb\n\t"
+ );
+}
+
+int icache_status(void)
+{
+ int ret;
+
+ __asm__ __volatile__ (
+ "mfsr $p0, $mr8\n\t"
+ "andi %0, $p0, 0x01\n\t"
+ : "=r" (ret)
+ :
+ : "memory"
+ );
+
+ return ret;
+}
+
+void dcache_enable(void)
+{
+ __asm__ __volatile__ (
+ "mfsr $p0, $mr8\n\t"
+ "ori $p0, $p0, 0x02\n\t"
+ "mtsr $p0, $mr8\n\t"
+ "isb\n\t"
+ );
+}
+
+void dcache_disable(void)
+{
+ __asm__ __volatile__ (
+ "mfsr $p0, $mr8\n\t"
+ "li $p1, ~0x02\n\t"
+ "and $p0, $p0, $p1\n\t"
+ "mtsr $p0, $mr8\n\t"
+ "isb\n\t"
+ );
+}
+
+int dcache_status(void)
+{
+ int ret;
+
+ __asm__ __volatile__ (
+ "mfsr $p0, $mr8\n\t"
+ "andi %0, $p0, 0x02\n\t"
+ : "=r" (ret)
+ :
+ : "memory"
+ );
+
+ return ret;
+}
diff --git a/arch/nds32/cpu/n1213/ag101/timer.c b/arch/nds32/cpu/n1213/ag101/timer.c
new file mode 100644
index 0000000..87275eb
--- /dev/null
+++ b/arch/nds32/cpu/n1213/ag101/timer.c
@@ -0,0 +1,204 @@
+/*
+ * (C) Copyright 2009 Faraday Technology
+ * Po-Yu Chuang <ratbert@faraday-tech.com>
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <faraday/fttmr010.h>
+
+static ulong timestamp;
+static ulong lastdec;
+
+int timer_init(void)
+{
+ static struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE;
+ unsigned int cr;
+
+ debug("%s()\n", __func__);
+
+ /* disable timers */
+ writel(0, &tmr->cr);
+
+#ifdef CONFIG_FTTMR010_EXT_CLK
+ /* use 32768Hz oscillator for RTC, WDT, TIMER */
+ ftpmu010_32768osc_enable();
+#endif
+
+ /* setup timer */
+ writel(TIMER_LOAD_VAL, &tmr->timer3_load);
+ writel(TIMER_LOAD_VAL, &tmr->timer3_counter);
+ writel(0, &tmr->timer3_match1);
+ writel(0, &tmr->timer3_match2);
+
+ /* we don't want timer to issue interrupts */
+ writel(FTTMR010_TM3_MATCH1 |
+ FTTMR010_TM3_MATCH2 |
+ FTTMR010_TM3_OVERFLOW,
+ &tmr->interrupt_mask);
+
+ cr = readl(&tmr->cr);
+#ifdef CONFIG_FTTMR010_EXT_CLK
+ cr |= FTTMR010_TM3_CLOCK; /* use external clock */
+#endif
+ cr |= FTTMR010_TM3_ENABLE;
+ writel(cr, &tmr->cr);
+
+ /* init the timestamp and lastdec value */
+ reset_timer_masked();
+
+ return 0;
+}
+
+/*
+ * timer without interrupts
+ */
+
+/*
+ * reset time
+ */
+void reset_timer_masked(void)
+{
+ static struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE;
+
+ /* capure current decrementer value time */
+#ifdef CONFIG_FTTMR010_EXT_CLK
+ lastdec = readl(&tmr->timer3_counter) / (TIMER_CLOCK / CONFIG_SYS_HZ);
+#else
+ lastdec = readl(&tmr->timer3_counter) / (APB_CLK);
+#endif
+ timestamp = 0; /* start "advancing" time stamp from 0 */
+
+ debug("%s(): lastdec = %lx\n", __func__, lastdec);
+}
+
+void reset_timer(void)
+{
+ debug("%s()\n", __func__);
+ reset_timer_masked();
+}
+
+/*
+ * return timer ticks
+ */
+ulong get_timer_masked(void)
+{
+ static struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE;
+
+ /* current tick value */
+#ifdef CONFIG_FTTMR010_EXT_CLK
+ ulong now = readl(&tmr->timer3_counter) / (TIMER_CLOCK / CONFIG_SYS_HZ);
+#else
+ ulong now = readl(&tmr->timer3_counter) / (APB_CLK);
+#endif
+
+ debug("%s(): now = %lx, lastdec = %lx\n", __func__, now, lastdec);
+
+ if (lastdec >= now) {
+ /*
+ * normal mode (non roll)
+ * move stamp fordward with absoulte diff ticks
+ */
+ timestamp += lastdec - now;
+ } else {
+ /*
+ * we have overflow of the count down timer
+ *
+ * nts = ts + ld + (TLV - now)
+ * ts=old stamp, ld=time that passed before passing through -1
+ * (TLV-now) amount of time after passing though -1
+ * nts = new "advancing time stamp"...it could also roll and
+ * cause problems.
+ */
+ timestamp += lastdec + TIMER_LOAD_VAL - now;
+ }
+
+ lastdec = now;
+
+ debug("%s() returns %lx\n", __func__, timestamp);
+
+ return timestamp;
+}
+
+/*
+ * return difference between timer ticks and base
+ */
+ulong get_timer(ulong base)
+{
+ debug("%s(%lx)\n", __func__, base);
+ return get_timer_masked() - base;
+}
+
+void set_timer(ulong t)
+{
+ debug("%s(%lx)\n", __func__, t);
+ timestamp = t;
+}
+
+/* delay x useconds AND preserve advance timestamp value */
+void __udelay(unsigned long usec)
+{
+ static struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE;
+
+#ifdef CONFIG_FTTMR010_EXT_CLK
+ long tmo = usec * (TIMER_CLOCK / 1000) / 1000;
+#else
+ long tmo = usec * (APB_CLK / 1000) / 1000;
+#endif
+ unsigned long now, last = readl(&tmr->timer3_counter);
+
+ debug("%s(%lu)\n", __func__, usec);
+ while (tmo > 0) {
+ now = readl(&tmr->timer3_counter);
+ if (now > last) /* count down timer overflow */
+ tmo -= TIMER_LOAD_VAL + last - now;
+ else
+ tmo -= last - now;
+ last = now;
+ }
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+ debug("%s()\n", __func__);
+ return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+ debug("%s()\n", __func__);
+#ifdef CONFIG_FTTMR010_EXT_CLK
+ return CONFIG_SYS_HZ;
+#else
+ return CONFIG_SYS_CLK_FREQ;
+#endif
+}
diff --git a/arch/nds32/cpu/n1213/ag101/watchdog.S b/arch/nds32/cpu/n1213/ag101/watchdog.S
new file mode 100644
index 0000000..fc39f3f
--- /dev/null
+++ b/arch/nds32/cpu/n1213/ag101/watchdog.S
@@ -0,0 +1,48 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm/arch-ag101/ag101.h>
+
+.text
+
+#ifndef CONFIG_SKIP_TRUNOFF_WATCHDOG
+.globl turnoff_watchdog
+turnoff_watchdog:
+
+#define WD_CR 0xC
+#define WD_ENABLE 0x1
+
+ ! Turn off the watchdog, according to Faraday FTWDT010 spec
+ li $p0, (CONFIG_FTWDT010_BASE+WD_CR) ! Get the addr of WD CR
+ lwi $p1, [$p0] ! Get the config of WD
+ andi $p1, $p1, 0x1f ! Wipe out useless bits
+ li $r0, ~WD_ENABLE
+ and $p1, $p1, $r0 ! Set WD disable
+ sw $p1, [$p0] ! Write back to WD CR
+
+ ! Disable Interrupts by clear GIE in $PSW reg
+ setgie.d
+
+ ret
+
+#endif
--
1.7.3.5
^ permalink raw reply related [flat|nested] 10+ messages in thread* [U-Boot] [PATCH v8 07/10] nds32/lib: add generic funcs in NDS32 lib
2011-04-11 2:46 [U-Boot] [PATCH v8 01/10] nds32: add header files support for nds32 Macpaul Lin
` (4 preceding siblings ...)
2011-04-11 2:47 ` [U-Boot] [PATCH v8 06/10] nds32/ag101: cpu and init funcs of SoC ag101 Macpaul Lin
@ 2011-04-11 2:47 ` Macpaul Lin
2011-04-11 2:47 ` [U-Boot] [PATCH v8 08/10] nds32: standalone support Macpaul Lin
` (2 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Macpaul Lin @ 2011-04-11 2:47 UTC (permalink / raw)
To: u-boot
Add Makefile, board.c, interrupts.c and bootm.c functions
to nds32 architecture.
Signed-off-by: Macpaul Lin <macpaul@andestech.com>
---
Changes for v1-v4:
- code clean up and formatting style.
Changes for v5-v6:
- board.c
- Do some clean up and add code
- Remove display banner which hasn't support.
- Add ftpmu010 related power management unit code.
- Remove useless LED related code.
- Move SDRAM init to board sepecific files. (ex. adp-ag101.c)
- Remove CONFIG_SOFT_I2C which hasn't been support.
- Remove CONFIG_FSL_ESDHC which hasn't been support.
- clean up.
Changes for v7:
- clean up.
- move single file patch arch/nds32/config.mk to this commit.
- interrupts.c refine origin interrupt enable and disable.
Changes for v8:
- interrups.c: fix up for new ptraces.h.
arch/nds32/config.mk | 35 +++++
arch/nds32/lib/Makefile | 52 +++++++
arch/nds32/lib/board.c | 346 +++++++++++++++++++++++++++++++++++++++++++
arch/nds32/lib/bootm.c | 241 ++++++++++++++++++++++++++++++
arch/nds32/lib/interrupts.c | 131 ++++++++++++++++
5 files changed, 805 insertions(+), 0 deletions(-)
create mode 100644 arch/nds32/config.mk
create mode 100644 arch/nds32/lib/Makefile
create mode 100644 arch/nds32/lib/board.c
create mode 100644 arch/nds32/lib/bootm.c
create mode 100644 arch/nds32/lib/interrupts.c
diff --git a/arch/nds32/config.mk b/arch/nds32/config.mk
new file mode 100644
index 0000000..ac5d0cf
--- /dev/null
+++ b/arch/nds32/config.mk
@@ -0,0 +1,35 @@
+#
+# (C) Copyright 2000-2002
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# (C) Copyright 2011
+# Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+# Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+
+CROSS_COMPILE ?= nds32le-linux-
+
+STANDALONE_LOAD_ADDR = 0x300000 -T nds32.lds
+
+PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common
+PLATFORM_RELFLAGS += -gdwarf-2
+PLATFORM_CPPFLAGS += -DCONFIG_NDS32 -D__nds32__ -G0 -ffixed-8
+
+LDSCRIPT := $(SRCTREE)/$(CPUDIR)/u-boot.lds
diff --git a/arch/nds32/lib/Makefile b/arch/nds32/lib/Makefile
new file mode 100644
index 0000000..eca4324
--- /dev/null
+++ b/arch/nds32/lib/Makefile
@@ -0,0 +1,52 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# Copyright (C) 2011 Andes Technology Corporation
+# Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+# Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(ARCH).o
+
+OBJS := board.o bootm.o interrupts.o
+
+all: $(LIB)
+
+$(LIB): $(OBJS) $(SOBJS)
+ $(AR) crv $@ $^
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/arch/nds32/lib/board.c b/arch/nds32/lib/board.c
new file mode 100644
index 0000000..6ed4194
--- /dev/null
+++ b/arch/nds32/lib/board.c
@@ -0,0 +1,346 @@
+/*
+ * (C) Copyright 2002-2006
+ * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <malloc.h>
+#include <stdio_dev.h>
+#include <timestamp.h>
+#include <version.h>
+#include <net.h>
+#include <serial.h>
+#include <nand.h>
+#include <onenand_uboot.h>
+#include <mmc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern ulong __bss_end;
+ulong monitor_flash_len;
+
+#ifndef CONFIG_IDENT_STRING
+#define CONFIG_IDENT_STRING ""
+#endif
+
+const char version_string[] =
+ U_BOOT_VERSION" (" U_BOOT_DATE " - " U_BOOT_TIME ")"CONFIG_IDENT_STRING;
+
+/*
+ * Init Utilities
+ */
+
+#if !defined(CONFIG_BAUDRATE)
+#define CONFIG_BAUDRATE 38400
+#endif
+static int init_baudrate(void)
+{
+ char tmp[64]; /* long enough for environment variables */
+ int i = getenv_f("baudrate", tmp, sizeof(tmp));
+
+ gd->bd->bi_baudrate = gd->baudrate = (i > 0)
+ ? (int) simple_strtoul(tmp, NULL, 10)
+ : CONFIG_BAUDRATE;
+
+ return 0;
+}
+
+/*
+ * WARNING: this code looks "cleaner" than the PowerPC version, but
+ * has the disadvantage that you either get nothing, or everything.
+ * On PowerPC, you might see "DRAM: " before the system hangs - which
+ * gives a simple yet clear indication which part of the
+ * initialization if failing.
+ */
+static int display_dram_config(void)
+{
+ int i;
+
+#ifdef DEBUG
+ puts("RAM Configuration:\n");
+
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+ printf("Bank #%d: %08lx ", i, gd->bd->bi_dram[i].start);
+ print_size(gd->bd->bi_dram[i].size, "\n");
+ }
+#else
+ ulong size = 0;
+
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
+ size += gd->bd->bi_dram[i].size;
+
+ puts("DRAM: ");
+ print_size(size, "\n");
+#endif
+
+ return 0;
+}
+
+#ifndef CONFIG_SYS_NO_FLASH
+static void display_flash_config(ulong size)
+{
+ puts("Flash: ");
+ print_size(size, "\n");
+}
+#endif /* CONFIG_SYS_NO_FLASH */
+
+#if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI)
+#include <pci.h>
+static int nds32_pci_init(void)
+{
+ pci_init();
+ return 0;
+}
+#endif /* CONFIG_CMD_PCI || CONFIG_PCI */
+
+#if defined(CONFIG_PMU) || defined(CONFIG_PCU)
+static int pmu_init(void)
+{
+#if defined(CONFIG_FTPMU010_POWER)
+#ifdef __NDS32_N1213_43U1H__ /* AG101: internal definition in toolchain */
+ ftpmu010_sdram_clk_disable(CONFIG_SYS_FTPMU010_PDLLCR0_HCLKOUTDIS);
+ ftpmu010_mfpsr_select_dev(FTPMU010_MFPSR_AC97CLKSEL);
+ ftpmu010_sdramhtc_set(CONFIG_SYS_FTPMU010_SDRAMHTC);
+#endif /* __NDS32_N1213_43U1H__ */
+#endif
+ return 0;
+}
+#endif
+
+/*
+ * Breathe some life into the board...
+ *
+ * Initialize a serial port as console, and carry out some hardware
+ * tests.
+ *
+ * The first part of initialization is running from Flash memory;
+ * its main purpose is to initialize the RAM so that we
+ * can relocate the monitor code to RAM.
+ */
+
+/*
+ * All attempts to come up with a "common" initialization sequence
+ * that works for all boards and architectures failed: some of the
+ * requirements are just _too_ different. To get rid of the resulting
+ * mess of board dependent #ifdef'ed code we now make the whole
+ * initialization sequence configurable to the user.
+ *
+ * The requirements for any new initalization function is simple: it
+ * receives a pointer to the "global data" structure as it's only
+ * argument, and returns an integer return code, where 0 means
+ * "continue" and != 0 means "fatal error, hang the system".
+ */
+typedef int (init_fnc_t)(void);
+
+init_fnc_t *init_sequence[] = {
+#if defined(CONFIG_ARCH_CPU_INIT)
+ arch_cpu_init, /* basic arch cpu dependent setup */
+#endif
+#if defined(CONFIG_PMU) || defined(CONFIG_PCU)
+ pmu_init,
+#endif
+ board_init, /* basic board dependent setup */
+#if defined(CONFIG_USE_IRQ)
+ interrupt_init, /* set up exceptions */
+#endif
+ timer_init, /* initialize timer */
+ env_init, /* initialize environment */
+ init_baudrate, /* initialze baudrate settings */
+ serial_init, /* serial communications setup */
+ console_init_f, /* stage 1 init of console */
+#if defined(CONFIG_DISPLAY_BOARDINFO)
+ checkboard, /* display board info */
+#endif
+#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
+ init_func_i2c,
+#endif
+ dram_init, /* configure available RAM banks */
+#if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI)
+ nds32_pci_init,
+#endif
+ display_dram_config,
+ NULL,
+};
+
+void start_andesboot(void)
+{
+ init_fnc_t **init_fnc_ptr;
+ char *s;
+#if defined(CONFIG_VFD) || defined(CONFIG_LCD)
+ unsigned long addr;
+#endif
+
+ /* Pointer is writable since we allocated a register for it */
+ gd = (gd_t *)(_andesboot_start - CONFIG_SYS_MALLOC_LEN - sizeof(gd_t));
+ /* compiler optimization barrier needed for GCC >= 3.4 */
+ __asm__ __volatile__("" : : : "memory");
+
+ memset((void *)gd, 0, sizeof(gd_t));
+ gd->bd = (bd_t *)((char *)gd - sizeof(bd_t));
+ memset(gd->bd, 0, sizeof(bd_t));
+
+ gd->flags |= GD_FLG_RELOC;
+
+ for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) {
+ if ((*init_fnc_ptr)() != 0)
+ hang();
+ }
+
+ /* andesboot_start is defined in the board-specific linker script */
+ mem_malloc_init(_andesboot_start - CONFIG_SYS_MALLOC_LEN,
+ CONFIG_SYS_MALLOC_LEN);
+
+#ifndef CONFIG_SYS_NO_FLASH
+ /* configure available FLASH banks */
+ gd->bd->bi_flashstart = CONFIG_SYS_FLASH_BASE;
+ gd->bd->bi_flashsize = flash_init();
+ gd->bd->bi_flashoffset = CONFIG_SYS_FLASH_BASE + gd->bd->bi_flashsize;
+
+ if (gd->bd->bi_flashsize)
+ display_flash_config(gd->bd->bi_flashsize);
+#endif /* CONFIG_SYS_NO_FLASH */
+
+#ifdef CONFIG_VFD
+# ifndef PAGE_SIZE
+# define PAGE_SIZE 4096
+# endif
+ /*
+ * reserve memory for VFD display (always full pages)
+ */
+ /* bss_end is defined in the board-specific linker script */
+ addr = (__bss_end + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1);
+ vfd_setmem(addr);
+ gd->fb_base = addr;
+#endif /* CONFIG_VFD */
+
+#ifdef CONFIG_LCD
+ /* board init may have inited fb_base */
+ if (!gd->fb_base) {
+# ifndef PAGE_SIZE
+# define PAGE_SIZE 4096
+# endif
+ /*
+ * reserve memory for LCD display (always full pages)
+ */
+ /* bss_end is defined in the board-specific linker script */
+ addr = (__bss_end + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1);
+ lcd_setmem(addr);
+ gd->fb_base = addr;
+ }
+#endif /* CONFIG_LCD */
+
+#if defined(CONFIG_CMD_NAND)
+ puts("NAND: ");
+ nand_init(); /* go init the NAND */
+#endif
+
+#if defined(CONFIG_CMD_ONENAND)
+ onenand_init();
+#endif
+
+ /* initialize environment */
+ env_relocate();
+
+#ifdef CONFIG_VFD
+ /* must do this after the framebuffer is allocated */
+ drv_vfd_init();
+#endif /* CONFIG_VFD */
+
+#ifdef CONFIG_SERIAL_MULTI
+ serial_initialize();
+#endif
+
+ /* IP Address */
+ gd->bd->bi_ip_addr = getenv_IPaddr("ipaddr");
+
+ stdio_init(); /* get the devices list going. */
+
+ jumptable_init();
+
+#if defined(CONFIG_API)
+ /* Initialize API */
+ api_init();
+#endif
+
+ console_init_r(); /* fully init console as a device */
+
+#if defined(CONFIG_ARCH_MISC_INIT)
+ /* miscellaneous arch dependent initialisations */
+ arch_misc_init();
+#endif
+#if defined(CONFIG_MISC_INIT_R)
+ /* miscellaneous platform dependent initialisations */
+ misc_init_r();
+#endif
+
+ /* enable exceptions */
+ enable_interrupts();
+
+ /* Perform network card initialisation if necessary */
+
+ /* Initialize from environment */
+ s = getenv("loadaddr");
+ if (s != NULL)
+ load_addr = simple_strtoul(s, NULL, 16);
+
+#if defined(CONFIG_CMD_NET)
+ s = getenv("bootfile");
+ if (s != NULL)
+ copy_filename(BootFile, s, sizeof(BootFile));
+#endif
+
+#ifdef BOARD_LATE_INIT
+ board_late_init();
+#endif
+
+#ifdef CONFIG_GENERIC_MMC
+ puts("MMC: ");
+ mmc_initialize(gd->bd);
+#endif
+
+#if defined(CONFIG_CMD_NET)
+#if defined(CONFIG_NET_MULTI)
+ puts("Net: ");
+#endif
+ eth_initialize(gd->bd);
+#if defined(CONFIG_RESET_PHY_R)
+ debug("Reset Ethernet PHY\n");
+ reset_phy();
+#endif
+#endif
+ /* main_loop() can return to retry autoboot, if so just run it again. */
+ for (;;)
+ main_loop();
+
+ /* NOTREACHED - no way out of command loop except booting */
+}
+
+void hang(void)
+{
+ puts("### ERROR ### Please RESET the board ###\n");
+ for (;;)
+ ;
+}
diff --git a/arch/nds32/lib/bootm.c b/arch/nds32/lib/bootm.c
new file mode 100644
index 0000000..b0a5a0d
--- /dev/null
+++ b/arch/nds32/lib/bootm.c
@@ -0,0 +1,241 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <command.h>
+#include <image.h>
+#include <u-boot/zlib.h>
+#include <asm/byteorder.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_SETUP_MEMORY_TAGS) || \
+ defined(CONFIG_CMDLINE_TAG) || \
+ defined(CONFIG_INITRD_TAG) || \
+ defined(CONFIG_SERIAL_TAG) || \
+ defined(CONFIG_REVISION_TAG)
+static void setup_start_tag(bd_t *bd);
+
+# ifdef CONFIG_SETUP_MEMORY_TAGS
+static void setup_memory_tags(bd_t *bd);
+# endif
+static void setup_commandline_tag(bd_t *bd, char *commandline);
+
+# ifdef CONFIG_INITRD_TAG
+static void setup_initrd_tag(bd_t *bd, ulong initrd_start, ulong initrd_end);
+# endif
+static void setup_end_tag(bd_t *bd);
+
+static struct tag *params;
+#endif /* CONFIG_SETUP_MEMORY_TAGS || CONFIG_CMDLINE_TAG || CONFIG_INITRD_TAG */
+
+int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images)
+{
+ bd_t *bd = gd->bd;
+ char *s;
+ int machid = bd->bi_arch_number;
+ void (*theKernel)(int zero, int arch, uint params);
+
+#ifdef CONFIG_CMDLINE_TAG
+ char *commandline = getenv("bootargs");
+#endif
+
+ if ((flag != 0) && (flag != BOOTM_STATE_OS_GO))
+ return 1;
+
+ theKernel = (void (*)(int, int, uint))images->ep;
+
+ s = getenv("machid");
+ if (s) {
+ machid = simple_strtoul(s, NULL, 16);
+ printf("Using machid 0x%x from environment\n", machid);
+ }
+
+ show_boot_progress(15);
+
+ debug("## Transferring control to Linux (at address %08lx) ...\n",
+ (ulong)theKernel);
+
+#if defined(CONFIG_SETUP_MEMORY_TAGS) || \
+ defined(CONFIG_CMDLINE_TAG) || \
+ defined(CONFIG_INITRD_TAG) || \
+ defined(CONFIG_SERIAL_TAG) || \
+ defined(CONFIG_REVISION_TAG)
+ setup_start_tag(bd);
+#ifdef CONFIG_SERIAL_TAG
+ setup_serial_tag(¶ms);
+#endif
+#ifdef CONFIG_REVISION_TAG
+ setup_revision_tag(¶ms);
+#endif
+#ifdef CONFIG_SETUP_MEMORY_TAGS
+ setup_memory_tags(bd);
+#endif
+#ifdef CONFIG_CMDLINE_TAG
+ setup_commandline_tag(bd, commandline);
+#endif
+#ifdef CONFIG_INITRD_TAG
+ if (images->rd_start && images->rd_end)
+ setup_initrd_tag(bd, images->rd_start, images->rd_end);
+#endif
+ setup_end_tag(bd);
+#endif
+
+ /* we assume that the kernel is in place */
+ printf("\nStarting kernel ...\n\n");
+
+#ifdef CONFIG_USB_DEVICE
+ {
+ extern void udc_disconnect(void);
+ udc_disconnect();
+ }
+#endif
+
+ cleanup_before_linux();
+
+ theKernel(0, machid, bd->bi_boot_params);
+ /* does not return */
+
+ return 1;
+}
+
+
+#if defined(CONFIG_SETUP_MEMORY_TAGS) || \
+ defined(CONFIG_CMDLINE_TAG) || \
+ defined(CONFIG_INITRD_TAG) || \
+ defined(CONFIG_SERIAL_TAG) || \
+ defined(CONFIG_REVISION_TAG)
+static void setup_start_tag(bd_t *bd)
+{
+ params = (struct tag *)bd->bi_boot_params;
+
+ params->hdr.tag = ATAG_CORE;
+ params->hdr.size = tag_size(tag_core);
+
+ params->u.core.flags = 0;
+ params->u.core.pagesize = 0;
+ params->u.core.rootdev = 0;
+
+ params = tag_next(params);
+}
+
+
+#ifdef CONFIG_SETUP_MEMORY_TAGS
+static void setup_memory_tags(bd_t *bd)
+{
+ int i;
+
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+ params->hdr.tag = ATAG_MEM;
+ params->hdr.size = tag_size(tag_mem32);
+
+ params->u.mem.start = bd->bi_dram[i].start;
+ params->u.mem.size = bd->bi_dram[i].size;
+
+ params = tag_next(params);
+ }
+}
+#endif /* CONFIG_SETUP_MEMORY_TAGS */
+
+
+static void setup_commandline_tag(bd_t *bd, char *commandline)
+{
+ char *p;
+
+ if (!commandline)
+ return;
+
+ /* eat leading white space */
+ for (p = commandline; *p == ' '; p++)
+ ;
+
+ /* skip non-existent command lines so the kernel will still
+ * use its default command line.
+ */
+ if (*p == '\0')
+ return;
+
+ params->hdr.tag = ATAG_CMDLINE;
+ params->hdr.size =
+ (sizeof(struct tag_header) + strlen(p) + 1 + 4) >> 2;
+
+ strcpy(params->u.cmdline.cmdline, p)
+ ;
+
+ params = tag_next(params);
+}
+
+
+#ifdef CONFIG_INITRD_TAG
+static void setup_initrd_tag(bd_t *bd, ulong initrd_start, ulong initrd_end)
+{
+ /* an ATAG_INITRD node tells the kernel where the compressed
+ * ramdisk can be found. ATAG_RDIMG is a better name, actually.
+ */
+ params->hdr.tag = ATAG_INITRD2;
+ params->hdr.size = tag_size(tag_initrd);
+
+ params->u.initrd.start = initrd_start;
+ params->u.initrd.size = initrd_end - initrd_start;
+
+ params = tag_next(params);
+}
+#endif /* CONFIG_INITRD_TAG */
+
+#ifdef CONFIG_SERIAL_TAG
+void setup_serial_tag(struct tag **tmp)
+{
+ struct tag *params = *tmp;
+ struct tag_serialnr serialnr;
+ void get_board_serial(struct tag_serialnr *serialnr);
+
+ get_board_serial(&serialnr);
+ params->hdr.tag = ATAG_SERIAL;
+ params->hdr.size = tag_size(tag_serialnr);
+ params->u.serialnr.low = serialnr.low;
+ params->u.serialnr.high = serialnr.high;
+ params = tag_next(params);
+ *tmp = params;
+}
+#endif
+
+#ifdef CONFIG_REVISION_TAG
+void setup_revision_tag(struct tag **in_params)
+{
+ u32 rev = 0;
+ u32 get_board_rev(void);
+
+ rev = get_board_rev();
+ params->hdr.tag = ATAG_REVISION;
+ params->hdr.size = tag_size(tag_revision);
+ params->u.revision.rev = rev;
+ params = tag_next(params);
+}
+#endif /* CONFIG_REVISION_TAG */
+
+
+static void setup_end_tag(bd_t *bd)
+{
+ params->hdr.tag = ATAG_NONE;
+ params->hdr.size = 0;
+}
+
+#endif /* CONFIG_SETUP_MEMORY_TAGS || CONFIG_CMDLINE_TAG || CONFIG_INITRD_TAG */
diff --git a/arch/nds32/lib/interrupts.c b/arch/nds32/lib/interrupts.c
new file mode 100644
index 0000000..c42ad2b
--- /dev/null
+++ b/arch/nds32/lib/interrupts.c
@@ -0,0 +1,131 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/ptrace.h>
+#include <asm/system.h>
+#undef INTERRUPT_MODE
+
+extern void reset_cpu(ulong addr);
+
+static int int_flag;
+
+int irq_flags; /* needed by asm-nds32/system.h */
+
+int GIE_STATUS(void)
+{
+ int ret;
+
+ __asm__ __volatile__ (
+ "mfsr $p0, $psw\n\t"
+ "andi %0, %0, 0x1\n\t"
+ : "=r" (ret)
+ :
+ : "memory"
+ );
+ return ret;
+}
+
+#ifdef CONFIG_USE_INTERRUPT
+
+/* enable interrupts */
+void enable_interrupts(void)
+{
+ local_irq_restore(int_flag);
+}
+
+/*
+ * disable interrupts
+ * Return TRUE if GIE is enabled before we disable it.
+ */
+int disable_interrupts(void)
+{
+
+ int gie_ori_status;
+
+ gie_ori_status = GIE_STATUS();
+
+ local_irq_save(int_flag);
+
+ return gie_ori_status;
+}
+#endif
+
+void bad_mode(void)
+{
+ panic("Resetting CPU ...\n");
+ reset_cpu(0);
+}
+
+void show_regs(struct pt_regs *regs)
+{
+ const char *processor_modes[] = {"USER", "SuperUser" , "HyperVisor"};
+
+ printf("\n");
+ printf("pc : [<%08lx>] sp: [<%08lx>]\n"
+ "lp : %08lx gp : %08lx fp : %08lx\n",
+ regs->ipc, regs->sp, regs->lp, regs->gp, regs->fp);
+ printf("D1H: %08lx D1L: %08lx D0H: %08lx D0L: %08lx\n",
+ regs->d1hi, regs->d1lo, regs->d0hi, regs->d0lo);
+ printf("r27: %08lx r26: %08lx r25: %08lx r24: %08lx\n",
+ regs->r[27], regs->r[26], regs->r[25], regs->r[24]);
+ printf("r23: %08lx r22: %08lx r21: %08lx r20: %08lx\n",
+ regs->r[23], regs->r[22], regs->r[21], regs->r[20]);
+ printf("r19: %08lx r18: %08lx r17: %08lx r16: %08lx\n",
+ regs->r[19], regs->r[18], regs->r[17], regs->r[16]);
+ printf("r15: %08lx r14: %08lx r13: %08lx r12: %08lx\n",
+ regs->r[15], regs->r[14], regs->r[13], regs->r[12]);
+ printf("r11: %08lx r10: %08lx r9 : %08lx r8 : %08lx\n",
+ regs->r[11], regs->r[10], regs->r[9], regs->r[8]);
+ printf("r7 : %08lx r6 : %08lx r5 : %08lx r4 : %08lx\n",
+ regs->r[7], regs->r[6], regs->r[5], regs->r[4]);
+ printf("r3 : %08lx r2 : %08lx r1 : %08lx r0 : %08lx\n",
+ regs->r[3], regs->r[2], regs->r[1], regs->r[0]);
+ printf(" Interrupts %s Mode %s\n",
+ interrupts_enabled(regs) ? "on" : "off",
+ processor_modes[processor_mode(regs)]);
+}
+
+void do_interruption(struct pt_regs *pt_regs, int EVIC_num)
+{
+ const char *interruption_type[] = {
+ "Reset",
+ "TLB Fill",
+ "TLB Not Present",
+ "TLB Misc",
+ "VLPT Miss",
+ "Cache Parity Error",
+ "Debug",
+ "General Exception",
+ "External Interrupt"
+ };
+
+ printf("%s\n", interruption_type[EVIC_num]);
+ show_regs(pt_regs);
+ bad_mode();
+}
--
1.7.3.5
^ permalink raw reply related [flat|nested] 10+ messages in thread* [U-Boot] [PATCH v8 08/10] nds32: standalone support
2011-04-11 2:46 [U-Boot] [PATCH v8 01/10] nds32: add header files support for nds32 Macpaul Lin
` (5 preceding siblings ...)
2011-04-11 2:47 ` [U-Boot] [PATCH v8 07/10] nds32/lib: add generic funcs in NDS32 lib Macpaul Lin
@ 2011-04-11 2:47 ` Macpaul Lin
2011-04-11 2:47 ` [U-Boot] [PATCH v8 09/10] nds32: common bdinfo, bootm, image support Macpaul Lin
2011-04-11 2:47 ` [U-Boot] [PATCH v8 10/10] adp-ag101: add board adp-ag101 support Macpaul Lin
8 siblings, 0 replies; 10+ messages in thread
From: Macpaul Lin @ 2011-04-11 2:47 UTC (permalink / raw)
To: u-boot
Add standalone program related support for nds32 architecture.
Signed-off-by: Macpaul Lin <macpaul@andestech.com>
---
examples/standalone/nds32.lds | 64 +++++++++++++++++++++++++++++++++++++
examples/standalone/stubs.c | 17 +++++++++-
examples/standalone/x86-testapp.c | 12 +++++++
3 files changed, 92 insertions(+), 1 deletions(-)
create mode 100644 examples/standalone/nds32.lds
diff --git a/examples/standalone/nds32.lds b/examples/standalone/nds32.lds
new file mode 100644
index 0000000..c2ac107
--- /dev/null
+++ b/examples/standalone/nds32.lds
@@ -0,0 +1,64 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-nds32", "elf32-nds32", "elf32-nds32")
+OUTPUT_ARCH(nds32)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0x00000000;
+
+ . = ALIGN(4);
+ .text :
+ {
+ *(.text)
+ }
+
+ . = ALIGN(4);
+ .data : { *(.data) }
+
+ . = ALIGN(4);
+ .data : { *(.data) }
+
+ . = ALIGN(4);
+
+ .got : {
+ __got_start = .;
+ *(.got)
+ __got_end = .;
+ }
+
+ . = ALIGN(4);
+ __bss_start = .;
+ .bss : { *(.bss) }
+ __bss_end = .;
+
+ . = ALIGN(4);
+ .rela.text : { *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) }
+
+ _end = .;
+
+ . = 0x02000000;
+ .u_boot_ohci_data_st : { *(.u_boot_ohci_data_st) }
+}
diff --git a/examples/standalone/stubs.c b/examples/standalone/stubs.c
index 2d2e709..b711926 100644
--- a/examples/standalone/stubs.c
+++ b/examples/standalone/stubs.c
@@ -167,8 +167,23 @@ gd_t *global_data;
" jmp %%g1\n" \
" nop\n" \
: : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x * sizeof(void *)) : "g1" );
-
+#elif defined(CONFIG_NDS32)
+/*
+ * r16 holds the pointer to the global_data. gp is call clobbered.
+ * not support reduced register (16 GPR).
+ */
+#define EXPORT_FUNC(x) \
+ asm volatile ( \
+" .globl " #x "\n" \
+#x ":\n" \
+" lwi $r16, [$gp + (%0)]\n" \
+" lwi $r16, [$r16 + (%1)]\n" \
+" jr $r16\n" \
+ : : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x * sizeof(void *)) : "$r16");
#else
+/*" addi $sp, $sp, -24\n" \
+" br $r16\n" \*/
+
#error stubs definition missing for this architecture
#endif
diff --git a/examples/standalone/x86-testapp.c b/examples/standalone/x86-testapp.c
index e8603d9..a4ac6f8 100644
--- a/examples/standalone/x86-testapp.c
+++ b/examples/standalone/x86-testapp.c
@@ -52,6 +52,16 @@ asm volatile ( \
" lw $25, %1($25)\n" \
" jr $25\n" \
: : "i"(offsetof(xxx_t, pfunc)), "i"(XF_ ## x * sizeof(void *)) : "t9");
+#elif defined(__nds32__)
+#define EXPORT_FUNC(x) \
+asm volatile ( \
+" .globl mon_" #x "\n" \
+"mon_" #x ":\n" \
+" lwi $r16, [$gp + (%0)]\n" \
+" lwi $r16, [$r16 + (%1)]\n" \
+" jr $r16\n" \
+ : : "i"(offsetof(xxx_t, pfunc)), "i"(XF_ ## x * sizeof(void *)) : "$r16");
+
#else
#error [No stub code for this arch]
#endif
@@ -72,6 +82,8 @@ int main(void)
register volatile xxx_t *pq asm("r8");
#elif defined(__mips__)
register volatile xxx_t *pq asm("k0");
+#elif defined(__nds32__)
+ register volatile xxx_t *pq asm("$r16");
#endif
char buf[32];
--
1.7.3.5
^ permalink raw reply related [flat|nested] 10+ messages in thread* [U-Boot] [PATCH v8 09/10] nds32: common bdinfo, bootm, image support
2011-04-11 2:46 [U-Boot] [PATCH v8 01/10] nds32: add header files support for nds32 Macpaul Lin
` (6 preceding siblings ...)
2011-04-11 2:47 ` [U-Boot] [PATCH v8 08/10] nds32: standalone support Macpaul Lin
@ 2011-04-11 2:47 ` Macpaul Lin
2011-04-11 2:47 ` [U-Boot] [PATCH v8 10/10] adp-ag101: add board adp-ag101 support Macpaul Lin
8 siblings, 0 replies; 10+ messages in thread
From: Macpaul Lin @ 2011-04-11 2:47 UTC (permalink / raw)
To: u-boot
Add support of NDS32 to common commands bdinfo, bootm, and image format.
Signed-off-by: Macpaul Lin <macpaul@andestech.com>
---
common/cmd_bdinfo.c | 28 +++++++++++++++++++++++++++-
common/cmd_bootm.c | 2 ++
common/image.c | 1 +
include/image.h | 5 +++++
4 files changed, 35 insertions(+), 1 deletions(-)
diff --git a/common/cmd_bdinfo.c b/common/cmd_bdinfo.c
index bba7374..908091d 100644
--- a/common/cmd_bdinfo.c
+++ b/common/cmd_bdinfo.c
@@ -411,13 +411,39 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
return 0;
}
+#elif defined(CONFIG_NDS32)
+
+int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ int i;
+ bd_t *bd = gd->bd;
+
+ print_num("arch_number", bd->bi_arch_number);
+ print_num("env_t", (ulong)bd->bi_env);
+ print_num("boot_params", (ulong)bd->bi_boot_params);
+
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {
+ print_num("DRAM bank", i);
+ print_num("-> start", bd->bi_dram[i].start);
+ print_num("-> size", bd->bi_dram[i].size);
+ }
+
+#if defined(CONFIG_CMD_NET)
+ print_eth(0);
+ printf("ip_addr = %pI4\n", &bd->bi_ip_addr);
+#endif
+ printf("baudrate = %d bps\n", bd->bi_baudrate);
+
+ return 0;
+}
+
#else
#error "a case for this architecture does not exist!"
#endif
static void print_num(const char *name, ulong value)
{
- printf ("%-12s= 0x%08lX\n", name, value);
+ printf("%-12s= 0x%08lX\n", name, value);
}
#if !(defined(CONFIG_ARM) || defined(CONFIG_M68K)) || defined(CONFIG_CMD_NET)
diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c
index 18019d6..59fbc45 100644
--- a/common/cmd_bootm.c
+++ b/common/cmd_bootm.c
@@ -187,6 +187,8 @@ void arch_preboot_os(void) __attribute__((weak, alias("__arch_preboot_os")));
#define IH_INITRD_ARCH IH_ARCH_SH
#elif defined(__sparc__)
#define IH_INITRD_ARCH IH_ARCH_SPARC
+#elif defined(__nds32__)
+ #define IH_INITRD_ARCH IH_ARCH_NDS32
#else
# error Unknown CPU type
#endif
diff --git a/common/image.c b/common/image.c
index f63a2ff..afe5957 100644
--- a/common/image.c
+++ b/common/image.c
@@ -93,6 +93,7 @@ static const table_entry_t uimage_arch[] = {
{ IH_ARCH_SPARC64, "sparc64", "SPARC 64 Bit", },
{ IH_ARCH_BLACKFIN, "blackfin", "Blackfin", },
{ IH_ARCH_AVR32, "avr32", "AVR32", },
+ { IH_ARCH_NDS32, "nds32", "NDS32", },
{ -1, "", "", },
};
diff --git a/include/image.h b/include/image.h
index 005e0d2..1a2be5e 100644
--- a/include/image.h
+++ b/include/image.h
@@ -106,6 +106,7 @@
#define IH_ARCH_BLACKFIN 16 /* Blackfin */
#define IH_ARCH_AVR32 17 /* AVR32 */
#define IH_ARCH_ST200 18 /* STMicroelectronics ST200 */
+#define IH_ARCH_NDS32 19 /* ANDES Technology - NDS32 */
/*
* Image Types
@@ -504,6 +505,8 @@ static inline int image_check_target_arch (const image_header_t *hdr)
if (!image_check_arch (hdr, IH_ARCH_SH))
#elif defined(__sparc__)
if (!image_check_arch (hdr, IH_ARCH_SPARC))
+#elif defined(__nds32__)
+ if (!image_check_arch(hdr, IH_ARCH_NDS32))
#else
# error Unknown CPU type
#endif
@@ -656,6 +659,8 @@ static inline int fit_image_check_target_arch (const void *fdt, int node)
if (!fit_image_check_arch (fdt, node, IH_ARCH_SH))
#elif defined(__sparc__)
if (!fit_image_check_arch (fdt, node, IH_ARCH_SPARC))
+#elif defined(__nds32__)
+ if (!fit_image_check_arch(fdt, node, IH_ARCH_NDS32))
#else
# error Unknown CPU type
#endif
--
1.7.3.5
^ permalink raw reply related [flat|nested] 10+ messages in thread* [U-Boot] [PATCH v8 10/10] adp-ag101: add board adp-ag101 support
2011-04-11 2:46 [U-Boot] [PATCH v8 01/10] nds32: add header files support for nds32 Macpaul Lin
` (7 preceding siblings ...)
2011-04-11 2:47 ` [U-Boot] [PATCH v8 09/10] nds32: common bdinfo, bootm, image support Macpaul Lin
@ 2011-04-11 2:47 ` Macpaul Lin
8 siblings, 0 replies; 10+ messages in thread
From: Macpaul Lin @ 2011-04-11 2:47 UTC (permalink / raw)
To: u-boot
Add evaluation board "adp-ag101" aconfiguration file adp-ag101.h.
Add adp-ag101.c board config and related settings.
Add board adp-ag101 into boards.cfg
Signed-off-by: Macpaul Lin <macpaul@andestech.com>
---
Changes for v1-v4:
- code clean up
Changes for v5-v6:
- Refine the definitions and parameters about CLK,
AHB controller, SDRAM controller, Static memory controllers.
- Add APB_CLK, AHB_CLK, SYS_CLK definitions for backward compatible.
- ftahbc010:
- Update include path of ftahbc010.
- ftsdmc021:
- Update include path of ftsdmc021.
- ftsmc020:
- Update include path of ftsmc020.
- ftwdt010:
- Fix WDT define and update include path.
- Fix ftwdt010 for hardware reset.
- ftpmu010:
- Remove duplicate PMU definitions.
- Add related configurations.
- Fix MAX malloc len and fix saveenv.
- clean up.
Changes for v7:
- adp-ag101.c
- Fix Makefile and remove config.mk
- adp-ag101.h:
- clean up.
- Move CONFIG_SYS_TEXT_BASE from board/config.mk.
MAINTAINERS | 11 +
MAKEALL | 6 +
board/AndesTech/adp-ag101/Makefile | 57 +++++
board/AndesTech/adp-ag101/adp-ag101.c | 81 +++++++
boards.cfg | 1 +
include/configs/adp-ag101.h | 378 +++++++++++++++++++++++++++++++++
6 files changed, 534 insertions(+), 0 deletions(-)
create mode 100644 board/AndesTech/adp-ag101/Makefile
create mode 100644 board/AndesTech/adp-ag101/adp-ag101.c
create mode 100644 include/configs/adp-ag101.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 8af9b09..0390c40 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1123,5 +1123,16 @@ Chong Huang <chuang@ucrobotics.com>
bf525-ucr2 BF525
#########################################################################
+# NDS32 Systems: #
+# #
+# Maintainer Name, Email Address #
+# Board CPU #
+#########################################################################
+
+Macpaul Lin <macpaul@andestech.com>
+
+ ADP-AG101 N1213 (AG101 SoC)
+
+#########################################################################
# End of MAINTAINERS list #
#########################################################################
diff --git a/MAKEALL b/MAKEALL
index e1b928f..286d158 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -610,6 +610,12 @@ LIST_sh="$(boards_by_arch sh)"
LIST_sparc="$(boards_by_arch sparc)"
+#########################################################################
+## NDS32 Systems
+#########################################################################
+
+LIST_nds32="$(boards_by_arch nds32)"
+
#-----------------------------------------------------------------------
build_target() {
diff --git a/board/AndesTech/adp-ag101/Makefile b/board/AndesTech/adp-ag101/Makefile
new file mode 100644
index 0000000..5a403b1
--- /dev/null
+++ b/board/AndesTech/adp-ag101/Makefile
@@ -0,0 +1,57 @@
+#
+# Copyright (C) 2011 Andes Technology Corporation
+# Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+# Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS := adp-ag101.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+ifdef CONFIG_SYS_LDSCRIPT
+LDSCRIPT := $(subst ",,$(CONFIG_SYS_LDSCRIPT))
+else
+LDSCRIPT := $(SRCTREE)/arch/$(ARCH)/cpu/$(CPU)/u-boot.lds
+endif
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/AndesTech/adp-ag101/adp-ag101.c b/board/AndesTech/adp-ag101/adp-ag101.c
new file mode 100644
index 0000000..b31b785
--- /dev/null
+++ b/board/AndesTech/adp-ag101/adp-ag101.c
@@ -0,0 +1,81 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/io.h>
+
+#include <faraday/ftsmc020.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Miscellaneous platform dependent initializations
+ */
+
+int board_init(void)
+{
+ /*
+ * refer to BOOT_PARAMETER_PA_BASE within
+ * "linux/arch/nds32/include/asm/misc_spec.h"
+ */
+ gd->bd->bi_arch_number = MACH_TYPE_ADPAG101;
+ gd->bd->bi_boot_params = PHYS_SDRAM_0 + 0x400;
+
+ ftsmc020_init(); /* initialize Flash */
+ return 0;
+}
+
+int dram_init(void)
+{
+ unsigned long sdram_base = PHYS_SDRAM_0;
+ unsigned long expected_size = PHYS_SDRAM_0_SIZE;
+ unsigned long actual_size;
+
+ actual_size = get_ram_size((void *)sdram_base, expected_size);
+
+ gd->bd->bi_dram[0].start = sdram_base;
+ gd->bd->bi_dram[0].size = actual_size;
+
+ if (expected_size != actual_size)
+ printf("Warning: Only %lu of %lu MiB SDRAM is working\n",
+ actual_size >> 20, expected_size >> 20);
+
+ return 0;
+}
+
+int board_eth_init(bd_t *bd)
+{
+ return ftmac100_initialize(bd);
+}
+
+ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
+{
+ if (banknum == 0) { /* non-CFI boot flash */
+ info->portwidth = FLASH_CFI_8BIT;
+ info->chipwidth = FLASH_CFI_BY8;
+ info->interface = FLASH_CFI_X8;
+ return 1;
+ } else
+ return 0;
+}
diff --git a/boards.cfg b/boards.cfg
index a45bd83..e3d1c16 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -245,6 +245,7 @@ vct_platinumavc mips mips32 vct microna
vct_platinumavc_small mips mips32 vct micronas - vct:VCT_PLATINUMAVC,VCT_SMALL_IMAGE
vct_platinumavc_onenand mips mips32 vct micronas - vct:VCT_PLATINUMAVC,VCT_ONENAND
vct_platinumavc_onenand_small mips mips32 vct micronas - vct:VCT_PLATINUMAVC,VCT_ONENAND,VCT_SMALL_IMAGE
+adp-ag101 nds32 n1213 adp-ag101 AndesTech ag101
PCI5441 nios2 nios2 pci5441 psyent
PK1C20 nios2 nios2 pk1c20 psyent
EVB64260 powerpc 74xx_7xx evb64260 - - EVB64260
diff --git a/include/configs/adp-ag101.h b/include/configs/adp-ag101.h
new file mode 100644
index 0000000..9e1d50e
--- /dev/null
+++ b/include/configs/adp-ag101.h
@@ -0,0 +1,378 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/ag101.h>
+
+/*
+ * CPU and Board Configuration Options
+ */
+#define CONFIG_ADP_AG101
+
+#define CONFIG_USE_INTERRUPT
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+/*
+ * Timer
+ */
+
+/*
+ * ag101: CONFIG_SYS_HZ: APB_CLK (ag101 original timer clock frequency)
+ *
+ * According to the discussion in u-boot mailing list before,
+ * CONFIG_SYS_HZ at 1000 is mandatory.
+ */
+
+/*
+ * APB_CLK, AHB_CLK, SYS_CLK are from an old configuration
+ * in the earlist nds32 bootloader.
+ *
+ * CONFIG_SYS_HZ = APB_CLK = SYS_CLK = CONFIG_SYS_CLK_FREQ /2
+ *
+ * Since the power management (PWM) Timer 4 uses a counter of
+ * 15625 for 10 ms, so we need it to wrap 100 times
+ * (total 1562500) to get 1 sec.
+ *
+ * #define CONFIG_HZ 1562500
+ * 1562500*25=3906250
+ */
+#define SYS_CLK CONFIG_SYS_CLK_FREQ
+#define AHB_CLK SYS_CLK
+#define APB_CLK (SYS_CLK / 2)
+
+#define CONFIG_SYS_HZ 1000
+#define VERSION_CLOCK CONFIG_SYS_CLK_FREQ
+
+#define CONFIG_SYS_TEXT_BASE 0x03200000
+
+/*
+ * System Clock
+ * Suggested frequency lists:
+ * 16000000 -> 16.000000 MHz
+ * 18432000 -> 18.432000 MHz
+ * 22118400 -> 22.118400 MHz
+ * 83000000 -> 83.000000 MHz
+ * 33000000 -> 33.000000 MHz
+ * 36864000 -> 36.864000 MHz
+ * 48000000 -> 48.000000 MHz CONFIG_ADP_AG101
+ * 39062500 -> 39.062500 MHz CONFIG_ADP_AG101P
+ */
+#ifdef CONFIG_ADP_AG101
+#define CONFIG_SYS_CLK_FREQ 48000000
+#endif
+
+/*
+ * Use Externel CLOCK or PCLK
+ */
+#undef CONFIG_FTRTC010_EXTCLK
+
+#ifndef CONFIG_FTRTC010_EXTCLK
+#define CONFIG_FTRTC010_PCLK
+#endif
+
+#ifdef CONFIG_FTRTC010_EXTCLK
+#define TIMER_CLOCK 32768 /* CONFIG_FTRTC010_EXTCLK */
+#else
+#define TIMER_CLOCK CONFIG_SYS_HZ /* CONFIG_FTRTC010_PCLK */
+#endif
+
+#define TIMER_LOAD_VAL 0xffffffff
+
+/*
+ * Real Time Clock
+ */
+#define CONFIG_RTC_FTRTC010
+
+/*
+ * Real Time Clock Divider
+ * RTC_DIV_COUNT (OSC_CLK/OSC_5MHZ)
+ */
+#ifdef CONFIG_ADP_AG101
+#define OSC_5MHZ (5*1000000)
+#define OSC_CLK (2*OSC_5MHZ)
+#define RTC_DIV_COUNT (OSC_CLK/OSC_5MHZ)
+#endif
+
+/*
+ * Serial console configuration
+ */
+
+/* FTUART is a high speed NS 16C550A compatible UART */
+#define CONFIG_BAUDRATE 38400
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_COM1 CONFIG_FTUART010_02_BASE /* 0x99600000 */
+#define CONFIG_SYS_NS16550_REG_SIZE -4
+
+#ifdef CONFIG_ADP_AG101
+#define CONFIG_SYS_NS16550_CLK ((46080000 * 20) / 25) /* AG101 */
+#endif
+
+/* valid baudrates */
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Ethernet
+ */
+#define CONFIG_NET_MULTI
+#define CONFIG_FTMAC100
+
+#define CONFIG_BOOTDELAY 3
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_PING
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_PROMPT "NDS32 # " /* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE \
+ (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/* max number of command args */
+#define CONFIG_SYS_MAXARGS 16
+
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+/*
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
+
+/*
+ * Size of malloc() pool
+ */
+/* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */
+#define CONFIG_SYS_MALLOC_LEN (512 << 10)
+
+/*
+ * size in bytes reserved for initial data
+ */
+#define CONFIG_SYS_GBL_DATA_SIZE 128
+
+/*
+ * AHB Controller configuration
+ */
+#define CONFIG_FTAHBC020S
+
+#ifdef CONFIG_FTAHBC020S
+#include <faraday/ftahbc020s.h>
+
+#define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE 0x100
+
+#define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6 (FTAHBC020S_SLAVE_BSR_BASE(CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE) | \
+ FTAHBC020S_SLAVE_BSR_SIZE(FTAHBC020S_SLAVE_BSR_SIZE_2G))
+#endif
+
+/*
+ * Watchdog
+ */
+#define CONFIG_FTWDT010_WATCHDOG
+
+/*
+ * PMU Power controller configuration
+ */
+#define CONFIG_PMU
+#define CONFIG_FTPMU010_POWER
+
+#ifdef CONFIG_FTPMU010_POWER
+#include <faraday/ftpmu010.h>
+#define CONFIG_SYS_FTPMU010_PDLLCR0_HCLKOUTDIS 0x0E
+#define CONFIG_SYS_FTPMU010_SDRAMHTC (FTPMU010_SDRAMHTC_EBICTRL_DCSR | \
+ FTPMU010_SDRAMHTC_EBIDATA_DCSR | \
+ FTPMU010_SDRAMHTC_SDRAMCS_DCSR | \
+ FTPMU010_SDRAMHTC_SDRAMCTL_DCSR | \
+ FTPMU010_SDRAMHTC_CKE_DCSR | \
+ FTPMU010_SDRAMHTC_DQM_DCSR | \
+ FTPMU010_SDRAMHTC_SDCLK_DCSR)
+#endif
+
+/*
+ * SDRAM controller configuration
+ */
+#define CONFIG_FTSDMC021
+
+#ifdef CONFIG_FTSDMC021
+#include <faraday/ftsdmc021.h>
+
+#define CONFIG_SYS_FTSDMC021_TP1 (FTSDMC021_TP1_TRP(1) | \
+ FTSDMC021_TP1_TRCD(1) | \
+ FTSDMC021_TP1_TRF(3) | \
+ FTSDMC021_TP1_TWR(1) | \
+ FTSDMC021_TP1_TCL(2))
+
+#define CONFIG_SYS_FTSDMC021_TP2 (FTSDMC021_TP2_INI_PREC(4) | \
+ FTSDMC021_TP2_INI_REFT(8) | \
+ FTSDMC021_TP2_REF_INTV(0x180))
+
+#define CONFIG_SYS_FTSDMC021_CR1 (FTSDMC021_CR1_DDW(2) | \
+ FTSDMC021_CR1_DSZ(3) | \
+ FTSDMC021_CR1_MBW(2) | \
+ FTSDMC021_CR1_BNKSIZEF(6))
+
+#define CONFIG_SYS_FTSDMC021_CR2 (FTSDMC021_CR2_IPREC | \
+ FTSDMC021_CR2_IREF | \
+ FTSDMC021_CR2_ISMR)
+
+#define CONFIG_SYS_FTSDMC021_BANK0_BASE CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE
+#define CONFIG_SYS_FTSDMC021_BANK0_BSR (FTSDMC021_BANK_ENABLE | \
+ CONFIG_SYS_FTSDMC021_BANK0_BASE)
+
+#endif
+
+/*
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
+#define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */
+#define PHYS_SDRAM_0_SIZE 0x04000000 /* 64 MB */
+
+/*
+ * Load address and memory test area should agree with
+ * board/faraday/a320/config.mk. Be careful not to overwrite U-boot itself.
+ */
+#define CONFIG_SYS_LOAD_ADDR 0x0CF00000
+
+/* memtest works on 63 MB in DRAM */
+#define CONFIG_SYS_MEMTEST_START 0x00000000
+#define CONFIG_SYS_MEMTEST_END 0x00200000
+
+/*
+ * Static memory controller configuration
+ */
+#define CONFIG_FTSMC020
+
+#ifdef CONFIG_FTSMC020
+#include <faraday/ftsmc020.h>
+
+#define CONFIG_SYS_FTSMC020_CONFIGS { \
+ { FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, }, \
+ { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, }, \
+}
+
+#ifdef CONFIG_ADP_AG101
+/*
+ * There are 2 bank connected to FTSMC020 on ADP_AG101
+ * BANK0: FLASH/ROM (SW5, J16), BANK1: OnBoard SDRAM.
+ *
+ * Note:
+ * FLASH on ADP_AG101P (FPGA version of ADP_AG101) is connected to BANK1
+ * Just disalbe the other BANK to avoid detection error.
+ */
+
+/* This FTSMC020_BANK1_SDRAM was used in lowlevel_init.S */
+#define FTSMC020_BANK1_SDRAM_CONFIG (FTSMC020_BANK_ENABLE | \
+ FTSMC020_BANK_SIZE_32M | \
+ FTSMC020_BANK_MBW_32)
+
+#define FTSMC020_BANK1_SDRAM_TIMING (FTSMC020_TPR_RBE | \
+ FTSMC020_TPR_AST(1) | \
+ FTSMC020_TPR_CTW(1) | \
+ FTSMC020_TPR_ATI(1) | \
+ FTSMC020_TPR_AT2(1) | \
+ FTSMC020_TPR_WTC(1) | \
+ FTSMC020_TPR_AHT(1) | \
+ FTSMC020_TPR_TRNA(1))
+
+#define FTSMC020_BANK1_CONFIG FTSMC020_BANK1_SDRAM_CONFIG
+#define FTSMC020_BANK1_TIMING FTSMC020_BANK1_SDRAM_TIMING
+
+/*
+ * This FTSMC020_BANK0_CONFIG indecates the setting of BANK0 (FLASH)
+ * PHYS_FLASH_1 should be 0x400000 (13 bits to store addr, 0x1000000)
+ */
+#define FTSMC020_BANK0_CONFIG (FTSMC020_BANK_ENABLE | \
+ FTSMC020_BANK_BASE(PHYS_FLASH_1) | \
+ FTSMC020_BANK_SIZE_32M | \
+ FTSMC020_BANK_MBW_32)
+
+#define FTSMC020_BANK0_TIMING (FTSMC020_TPR_AST(3) | \
+ FTSMC020_TPR_CTW(3) | \
+ FTSMC020_TPR_ATI(0xf) | \
+ FTSMC020_TPR_AT2(3) | \
+ FTSMC020_TPR_WTC(3) | \
+ FTSMC020_TPR_AHT(3) | \
+ FTSMC020_TPR_TRNA(0xf))
+#endif /* CONFIG_ADP_AG101 */
+#endif /* CONFIG_FTSMC020 */
+
+/*
+ * FLASH and environment organization
+ */
+
+/* use CFI framework */
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+
+/* support JEDEC */
+/* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */
+#define PHYS_FLASH_1 0x80400000
+
+#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
+#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, }
+#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* TO for Flash Erase (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* TO for Flash Write (ms) */
+
+/* max number of memory banks */
+/*
+ * There are 4 banks supported for this Controller,
+ * but we have only 1 bank connected to flash on board
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+
+/* max number of sectors on one chip */
+#define CONFIG_FLASH_SECTOR_SIZE (0x10000*2*2)
+#define CONFIG_ENV_SECT_SIZE CONFIG_FLASH_SECTOR_SIZE
+#define CONFIG_SYS_MAX_FLASH_SECT 128
+
+/* environments */
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x1C0000)
+#define CONFIG_ENV_SIZE 8192
+#define CONFIG_ENV_OVERWRITE
+
+/* relocation parameters */
+#define CONFIG_SYS_RELO_ADDR 0x10000000
+
+#endif /* __CONFIG_H */
--
1.7.3.5
^ permalink raw reply related [flat|nested] 10+ messages in thread