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From: Peter Zijlstra <peterz@infradead.org>
To: Christoph Lameter <cl@linux.com>
Cc: James Bottomley <James.bottomley@HansenPartnership.com>,
	Andrew Morton <akpm@linux-foundation.org>,
	Greg Thelen <gthelen@google.com>,
	linux-kernel@vger.kernel.org, linux-mm@kvack.org,
	KAMEZAWA Hiroyuki <kamezawa.hiroyu@jp.fujitsu.com>,
	Balbir Singh <bsingharora@gmail.com>,
	Daisuke Nishimura <nishimura@mxp.nes.nec.co.jp>,
	linux-arch@vger.kernel.org
Subject: Re: [PATCH] memcg: remove unneeded preempt_disable
Date: Thu, 25 Aug 2011 20:49:32 +0200	[thread overview]
Message-ID: <1314298173.27911.86.camel@twins> (raw)
In-Reply-To: <alpine.DEB.2.00.1108251341230.27407@router.home>

On Thu, 2011-08-25 at 13:46 -0500, Christoph Lameter wrote:
> 
> RISC cpus have instruction to construct complex atomic actions by the cpu
> as I have shown before for ARM. 

Right, but it only makes sense if the whole thing remains cheaper than
the trivial implementation already available.

For instance, the ARM LL/SC constraints pretty much mandate we do
preempt_disable()/preempt_enable() around them, at which point the point
of doing LL/SC is gone (except maybe for the irqsafe_this_cpu_* stuff).

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WARNING: multiple messages have this Message-ID (diff)
From: Peter Zijlstra <peterz@infradead.org>
To: Christoph Lameter <cl@linux.com>
Cc: James Bottomley <James.bottomley@HansenPartnership.com>,
	Andrew Morton <akpm@linux-foundation.org>,
	Greg Thelen <gthelen@google.com>,
	linux-kernel@vger.kernel.org, linux-mm@kvack.org,
	KAMEZAWA Hiroyuki <kamezawa.hiroyu@jp.fujitsu.com>,
	Balbir Singh <bsingharora@gmail.com>,
	Daisuke Nishimura <nishimura@mxp.nes.nec.co.jp>,
	linux-arch@vger.kernel.org
Subject: Re: [PATCH] memcg: remove unneeded preempt_disable
Date: Thu, 25 Aug 2011 20:49:32 +0200	[thread overview]
Message-ID: <1314298173.27911.86.camel@twins> (raw)
Message-ID: <20110825184932.zHXHKjotcpe6HvKgw0XKDeqbJyi-npnSafQ8tYIvfJk@z> (raw)
In-Reply-To: <alpine.DEB.2.00.1108251341230.27407@router.home>

On Thu, 2011-08-25 at 13:46 -0500, Christoph Lameter wrote:
> 
> RISC cpus have instruction to construct complex atomic actions by the cpu
> as I have shown before for ARM. 

Right, but it only makes sense if the whole thing remains cheaper than
the trivial implementation already available.

For instance, the ARM LL/SC constraints pretty much mandate we do
preempt_disable()/preempt_enable() around them, at which point the point
of doing LL/SC is gone (except maybe for the irqsafe_this_cpu_* stuff).

  reply	other threads:[~2011-08-25 18:49 UTC|newest]

Thread overview: 56+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2011-08-18  6:50 [PATCH] memcg: remove unneeded preempt_disable Greg Thelen
2011-08-18  6:50 ` Greg Thelen
2011-08-18  6:52 ` KAMEZAWA Hiroyuki
2011-08-18  6:52   ` KAMEZAWA Hiroyuki
2011-08-18  9:38 ` Johannes Weiner
2011-08-18  9:38   ` Johannes Weiner
2011-08-18 14:26   ` Valdis.Kletnieks
2011-08-18 14:41     ` Johannes Weiner
2011-08-18 14:41       ` Johannes Weiner
2011-08-18 18:27       ` Valdis.Kletnieks
2011-08-18 21:40 ` Andrew Morton
2011-08-18 21:40   ` Andrew Morton
2011-08-19  0:00   ` Greg Thelen
2011-08-19  0:00     ` Greg Thelen
2011-08-25 14:57   ` Peter Zijlstra
2011-08-25 14:57     ` Peter Zijlstra
2011-08-25 15:11     ` Christoph Lameter
2011-08-25 15:11       ` Christoph Lameter
2011-08-25 16:20       ` James Bottomley
2011-08-25 16:20         ` James Bottomley
2011-08-25 16:31         ` Christoph Lameter
2011-08-25 16:31           ` Christoph Lameter
2011-08-25 16:34           ` James Bottomley
2011-08-25 16:34             ` James Bottomley
2011-08-25 17:07             ` Christoph Lameter
2011-08-25 17:07               ` Christoph Lameter
2011-08-25 18:34               ` James Bottomley
2011-08-25 18:34                 ` James Bottomley
2011-08-25 18:46                 ` Christoph Lameter
2011-08-25 18:46                   ` Christoph Lameter
2011-08-25 18:49                   ` Peter Zijlstra [this message]
2011-08-25 18:49                     ` Peter Zijlstra
2011-08-25 18:53                   ` Peter Zijlstra
2011-08-25 18:53                     ` Peter Zijlstra
2011-08-25 19:05                   ` Peter Zijlstra
2011-08-25 19:05                     ` Peter Zijlstra
2011-08-25 19:19                     ` Christoph Lameter
2011-08-25 19:19                       ` Christoph Lameter
2011-08-25 22:56                       ` Peter Zijlstra
2011-08-25 22:56                         ` Peter Zijlstra
2011-08-25 19:29                   ` James Bottomley
2011-08-25 19:29                     ` James Bottomley
2011-08-25 23:01                     ` Peter Zijlstra
2011-08-25 23:01                       ` Peter Zijlstra
2011-08-25 18:40           ` Peter Zijlstra
2011-08-25 18:40             ` Peter Zijlstra
2011-09-06  9:58 ` Johannes Weiner
2011-09-06  9:58   ` Johannes Weiner
2011-09-06 10:04   ` KAMEZAWA Hiroyuki
2011-09-06 10:04     ` KAMEZAWA Hiroyuki
2011-09-06 10:49     ` Johannes Weiner
2011-09-06 10:49       ` Johannes Weiner
2011-09-06 10:45       ` KAMEZAWA Hiroyuki
2011-09-06 10:45         ` KAMEZAWA Hiroyuki
2011-09-06 18:04   ` Greg Thelen
2011-09-06 18:04     ` Greg Thelen

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