[U-Boot] [PATCH 1/5] powerpc/85xx: fix definition of MAS register macros

[U-Boot] [PATCH 1/5] powerpc/85xx: fix definition of MAS register macros

[Timur Tabi]

Some of the MAS register macros do not protect the parameter with
parentheses, which could cause wrong values if the parameter includes
operators.

Also fix the definition of TSIZE_TO_BYTES() so that it actually uses
the parameter.  This hasn't caused any problems to date because the
parameter was always been 'tsize'.

Signed-off-by: Timur Tabi <timur@freescale.com>
---
 arch/powerpc/include/asm/mmu.h |   10 +++++-----
 1 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/arch/powerpc/include/asm/mmu.h b/arch/powerpc/include/asm/mmu.h
index ef5076b..209103e 100644
--- a/arch/powerpc/include/asm/mmu.h
+++ b/arch/powerpc/include/asm/mmu.h
@@ -392,17 +392,17 @@ extern void print_bats(void);
  */
 
 #define MAS0_TLBSEL_MSK	0x30000000
-#define MAS0_TLBSEL(x)	((x << 28) & MAS0_TLBSEL_MSK)
+#define MAS0_TLBSEL(x)	(((x) << 28) & MAS0_TLBSEL_MSK)
 #define MAS0_ESEL_MSK	0x0FFF0000
-#define MAS0_ESEL(x)	((x << 16) & MAS0_ESEL_MSK)
+#define MAS0_ESEL(x)	(((x) << 16) & MAS0_ESEL_MSK)
 #define MAS0_NV(x)	((x) & 0x00000FFF)
 
 #define MAS1_VALID	0x80000000
 #define MAS1_IPROT	0x40000000
-#define MAS1_TID(x)	((x << 16) & 0x3FFF0000)
+#define MAS1_TID(x)	(((x) << 16) & 0x3FFF0000)
 #define MAS1_TS		0x00001000
-#define MAS1_TSIZE(x)	((x << 8) & 0x00000F00)
-#define TSIZE_TO_BYTES(x) ((phys_addr_t)(1UL << ((tsize * 2) + 10)))
+#define MAS1_TSIZE(x)	(((x) << 8) & 0x00000F00)
+#define TSIZE_TO_BYTES(x) (1ULL << (((x) * 2) + 10))
 
 #define MAS2_EPN	0xFFFFF000
 #define MAS2_X0		0x00000040
-- 
1.7.3.4

[U-Boot] [PATCH 2/5] powerpc/85xx: fix some comments in the CCSR relocation code

[Timur Tabi]

Signed-off-by: Timur Tabi <timur@freescale.com>
---
 arch/powerpc/cpu/mpc85xx/start.S |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S
index 528abc9..b5bf1fa 100644
--- a/arch/powerpc/cpu/mpc85xx/start.S
+++ b/arch/powerpc/cpu/mpc85xx/start.S
@@ -398,7 +398,7 @@ create_ccsr_new_tlb:
 	tlbwe
 
 	/*
-	 * Create a TLB for the old location of CCSR.  Register R9 is reserved
+	 * Create a TLB for the current location of CCSR.  Register R9 is reserved
 	 * for the virtual address of this TLB (CONFIG_SYS_CCSRBAR + 0x1000).
 	 */
 create_ccsr_old_tlb:
@@ -457,7 +457,7 @@ create_temp_law:
 	 */
 read_old_ccsrbar:
 	lwz	r0, 0(r9)	/* CCSRBARH */
-	lwz	r0, 4(r9)	/* CCSRBARH */
+	lwz	r0, 4(r9)	/* CCSRBARL */
 	isync
 
 	/*
-- 
1.7.3.4

[U-Boot] [PATCH 2/5] powerpc/85xx: fix some comments in the CCSR relocation code

[Kumar Gala]

On Oct 31, 2011, at 1:30 PM, Timur Tabi wrote:

> Signed-off-by: Timur Tabi <timur@freescale.com>
> ---
> arch/powerpc/cpu/mpc85xx/start.S |    4 ++--
> 1 files changed, 2 insertions(+), 2 deletions(-)

applied to 85xx

- k

[U-Boot] [PATCH 3/5] powerpc/85xx: add some missing sync instructions in the CCSR relocation code

[Timur Tabi]

Calls to tlbwe and tlbsx should be preceded with an isync/msync pair.

Signed-off-by: Timur Tabi <timur@freescale.com>
---
 arch/powerpc/cpu/mpc85xx/start.S |    4 ++++
 1 files changed, 4 insertions(+), 0 deletions(-)

diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S
index b5bf1fa..ccb331a 100644
--- a/arch/powerpc/cpu/mpc85xx/start.S
+++ b/arch/powerpc/cpu/mpc85xx/start.S
@@ -363,6 +363,8 @@ purge_old_ccsr_tlb:
 
 	li	r1, 0
 	mtspr	MAS6, r1	/* Search the current address space and PID */
+	isync
+	msync
 	tlbsx	0, r8
 	mfspr	r1, MAS1
 	andis.  r2, r1, MAS1_VALID at h	/* Check for the Valid bit */
@@ -370,6 +372,8 @@ purge_old_ccsr_tlb:
 
 	rlwinm	r1, r1, 0, 1, 31	/* Clear Valid bit */
 	mtspr	MAS1, r1
+	isync
+	msync
 	tlbwe
 1:
 
-- 
1.7.3.4

[U-Boot] [PATCH 3/5] powerpc/85xx: add some missing sync instructions in the CCSR relocation code

[Kumar Gala]

On Oct 31, 2011, at 1:30 PM, Timur Tabi wrote:

> Calls to tlbwe and tlbsx should be preceded with an isync/msync pair.
> 
> Signed-off-by: Timur Tabi <timur@freescale.com>
> ---
> arch/powerpc/cpu/mpc85xx/start.S |    4 ++++
> 1 files changed, 4 insertions(+), 0 deletions(-)

applied to 85xx

- k

[U-Boot] [PATCH 4/5] powerpc/85xx: verify the current address of CCSR before relocating it

[Timur Tabi]

Verify that CCSR is actually located where it is supposed to be before
we relocate it.  This is useful in detecting U-Boot configurations that
are broken (e.g. an incorrect value for CONFIG_SYS_CCSRBAR_DEFAULT).
If the current value is wrong, we enter an infinite loop, which is handy
for debuggers.

Signed-off-by: Timur Tabi <timur@freescale.com>
---
 arch/powerpc/cpu/mpc85xx/start.S |   27 +++++++++++++++++++++++++++
 1 files changed, 27 insertions(+), 0 deletions(-)

diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S
index ccb331a..6de8765 100644
--- a/arch/powerpc/cpu/mpc85xx/start.S
+++ b/arch/powerpc/cpu/mpc85xx/start.S
@@ -422,6 +422,33 @@ create_ccsr_old_tlb:
 	msync
 	tlbwe
 
+	/*
+	 * We have a TLB for what we think is the current (old) CCSR.  Let's
+	 * verify that, otherwise we won't be able to move it.
+	 * CONFIG_SYS_CCSRBAR_DEFAULT is always a 32-bit number, so we only
+	 * need to compare the lower 32 bits of CCSRBAR on CoreNet systems.
+	 */
+verify_old_ccsr:
+	lis     r0, CONFIG_SYS_CCSRBAR_DEFAULT at h
+	ori     r0, r0, CONFIG_SYS_CCSRBAR_DEFAULT at l
+#ifdef CONFIG_FSL_CORENET
+	lwz	r1, 4(r9)		/* CCSRBARL */
+#else
+	lwz	r1, 0(r9)		/* CCSRBAR, shifted right by 12 */
+	slwi	r1, r1, 12
+#endif
+
+	cmpl	0, r0, r1
+
+	/*
+	 * If the value we read from CCSRBARL is not what we expect, then
+	 * enter an infinite loop.  This will at least allow a debugger to
+	 * halt execution and examine TLBs, etc.  There's no point in going
+	 * on.
+	 */
+infinite_debug_loop:
+	bne	infinite_debug_loop
+
 #ifdef CONFIG_FSL_CORENET
 
 #define CCSR_LAWBARH0	(CONFIG_SYS_CCSRBAR + 0x1000)
-- 
1.7.3.4

[U-Boot] [PATCH 4/5] powerpc/85xx: verify the current address of CCSR before relocating it

[Kumar Gala]

On Oct 31, 2011, at 1:30 PM, Timur Tabi wrote:

> Verify that CCSR is actually located where it is supposed to be before
> we relocate it.  This is useful in detecting U-Boot configurations that
> are broken (e.g. an incorrect value for CONFIG_SYS_CCSRBAR_DEFAULT).
> If the current value is wrong, we enter an infinite loop, which is handy
> for debuggers.
> 
> Signed-off-by: Timur Tabi <timur@freescale.com>
> ---
> arch/powerpc/cpu/mpc85xx/start.S |   27 +++++++++++++++++++++++++++
> 1 files changed, 27 insertions(+), 0 deletions(-)

applied to 85xx

- k

[U-Boot] [PATCH 5/5] powerpc/85xx: resize the boot page TLB before relocating CCSR

[Timur Tabi]

On some Freescale systems (e.g. those booted from the on-chip ROM), the
TLB that covers the boot page can also cover CCSR, which breaks the CCSR
relocation code.  To fix this, we resize the boot page TLB so that it only
covers the 4KB boot page.

Signed-off-by: Timur Tabi <timur@freescale.com>
---
 arch/powerpc/cpu/mpc85xx/start.S |   49 ++++++++++++++++++++++++++++++++++++++
 1 files changed, 49 insertions(+), 0 deletions(-)

diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S
index 6de8765..39f1438 100644
--- a/arch/powerpc/cpu/mpc85xx/start.S
+++ b/arch/powerpc/cpu/mpc85xx/start.S
@@ -330,6 +330,55 @@ l2_disabled:
 #endif /* CONFIG_MPC8569 */
 
 /*
+ * Search for the TLB that covers the code we're executing, and shrink it
+ * so that it covers only this 4K page.  That will ensure that any other
+ * TLB we create won't interfere with it.  We assume that the TLB exists,
+ * which is why we don't check the Valid bit of MAS1.
+ *
+ * This is necessary, for example, when booting from the on-chip ROM,
+ * which (oddly) creates a single 4GB TLB that covers CCSR and DDR.
+ * If we don't shrink this TLB now, then we'll accidentally delete it
+ * in "purge_old_ccsr_tlb" below.
+ */
+	bl	nexti		/* Find our address */
+nexti:	mflr	r1		/* R1 = our PC */
+	li	r2, 0
+	mtspr	MAS6, r2	/* Assume the current PID and AS are 0 */
+	isync
+	msync
+	tlbsx	0, r1		/* This must succeed */
+
+	/* Set the size of the TLB to 4KB */
+	mfspr	r3, MAS1
+	li	r2, 0xF00
+	andc	r3, r3, r2	/* Clear the TSIZE bits */
+	ori	r3, r3, MAS1_TSIZE(BOOKE_PAGESZ_4K)@l
+	mtspr	MAS1, r3
+
+	/*
+	 * Set the base address of the TLB to our PC.  We assume that
+	 * virtual == physical.  We also assume that MAS2_EPN == MAS3_RPN.
+	 */
+	lis	r3, MAS2_EPN at h
+	ori	r3, r3, MAS2_EPN at l	/* R3 = MAS2_EPN */
+
+	and	r1, r1, r3	/* Our PC, rounded down to the nearest page */
+
+	mfspr	r2, MAS2
+	andc	r2, r2, r3
+	or	r2, r2, r1
+	mtspr	MAS2, r2	/* Set the EPN to our PC base address */
+
+	mfspr	r2, MAS3
+	andc	r2, r2, r3
+	or	r2, r2, r1
+	mtspr	MAS3, r2	/* Set the RPN to our PC base address */
+
+	isync
+	msync
+	tlbwe
+
+/*
  * Relocate CCSR, if necessary.  We relocate CCSR if (obviously) the default
  * location is not where we want it.  This typically happens on a 36-bit
  * system, where we want to move CCSR to near the top of 36-bit address space.
-- 
1.7.3.4

[U-Boot] [PATCH 5/5] powerpc/85xx: resize the boot page TLB before relocating CCSR

[Kumar Gala]

On Oct 31, 2011, at 1:30 PM, Timur Tabi wrote:

> On some Freescale systems (e.g. those booted from the on-chip ROM), the
> TLB that covers the boot page can also cover CCSR, which breaks the CCSR
> relocation code.  To fix this, we resize the boot page TLB so that it only
> covers the 4KB boot page.
> 
> Signed-off-by: Timur Tabi <timur@freescale.com>
> ---
> arch/powerpc/cpu/mpc85xx/start.S |   49 ++++++++++++++++++++++++++++++++++++++
> 1 files changed, 49 insertions(+), 0 deletions(-)

applied to 85xx

- k

[U-Boot] [PATCH 1/5] powerpc/85xx: fix definition of MAS register macros

[Kumar Gala]

On Oct 31, 2011, at 1:30 PM, Timur Tabi wrote:

> Some of the MAS register macros do not protect the parameter with
> parentheses, which could cause wrong values if the parameter includes
> operators.
> 
> Also fix the definition of TSIZE_TO_BYTES() so that it actually uses
> the parameter.  This hasn't caused any problems to date because the
> parameter was always been 'tsize'.
> 
> Signed-off-by: Timur Tabi <timur@freescale.com>
> ---
> arch/powerpc/include/asm/mmu.h |   10 +++++-----
> 1 files changed, 5 insertions(+), 5 deletions(-)

applied to 85xx

- k