[PATCH 1/2] ASoC: cs42l51: Clear CS42L51_MIC_POWER_CTL_AUTO bit for MODE_SLAVE and MODE_MASTER

[PATCH 1/2] ASoC: cs42l51: Clear CS42L51_MIC_POWER_CTL_AUTO bit for MODE_SLAVE and MODE_MASTER

[Axel Lin]

According to the datasheet:

MIC Power Control & Speed Control (Address 03h)
BIT[7] : Auto-Detect Speed Mode (AUTO)
        Default: 1
        0 - Disable
        1 - Enable

Function:
Enables the auto-detect circuitry for detecting the speed mode
of the CODEC when operating as a slave.
When AUTO is enabled, the MCLK/LRCK ratio must be implemented
according to Table 3 on page 39. The
SPEED[1:0] bits are ignored when this bit is enabled.
Speed is determined by the MCLK/LRCK ratio.

SPEED[1:0] bits are ignored when this bit is enabled.
Thus we need to clear this bit for MODE_SLAVE and MODE_MASTER
because the default of this bit is 1 (Enable).

Signed-off-by: Axel Lin <axel.lin@gmail.com>
---
 sound/soc/codecs/cs42l51.c |    3 ++-
 1 files changed, 2 insertions(+), 1 deletions(-)

diff --git a/sound/soc/codecs/cs42l51.c b/sound/soc/codecs/cs42l51.c
index 00718b5..35c5ac3 100644
--- a/sound/soc/codecs/cs42l51.c
+++ b/sound/soc/codecs/cs42l51.c
@@ -400,7 +400,8 @@ static int cs42l51_hw_params(struct snd_pcm_substream *substream,
 
 	intf_ctl &= ~(CS42L51_INTF_CTL_MASTER | CS42L51_INTF_CTL_ADC_I2S
 			| CS42L51_INTF_CTL_DAC_FORMAT(7));
-	power_ctl &= ~(CS42L51_MIC_POWER_CTL_SPEED(3)
+	power_ctl &= ~(CS42L51_MIC_POWER_CTL_AUTO
+			| CS42L51_MIC_POWER_CTL_SPEED(3)
 			| CS42L51_MIC_POWER_CTL_MCLK_DIV2);
 
 	switch (cs42l51->func) {
-- 
1.7.5.4

[PATCH 2/2] ASoC: cs42l51: Fix off-by-one for reg_cache_size

[Axel Lin]

Just checking the code in cs42l51_fill_cache():
The cache pointer points to codec->reg_cache + 1.
I think it is because CS42L51_FIRSTREG is 0x01,
so codec->reg_cache[0] is not used here.

Then we read CS42L51_NUMREGS bytes to cache.
So we need reg_cache_size to be CS42L51_NUMREGS + 1.

Signed-off-by: Axel Lin <axel.lin@gmail.com>
---
 sound/soc/codecs/cs42l51.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/sound/soc/codecs/cs42l51.c b/sound/soc/codecs/cs42l51.c
index 35c5ac3..c0b0a39 100644
--- a/sound/soc/codecs/cs42l51.c
+++ b/sound/soc/codecs/cs42l51.c
@@ -553,7 +553,7 @@ static int cs42l51_probe(struct snd_soc_codec *codec)
 
 static struct snd_soc_codec_driver soc_codec_device_cs42l51 = {
 	.probe =	cs42l51_probe,
-	.reg_cache_size = CS42L51_NUMREGS,
+	.reg_cache_size = CS42L51_NUMREGS + 1,
 	.reg_word_size = sizeof(u8),
 };
 
-- 
1.7.5.4

Re: [PATCH 2/2] ASoC: cs42l51: Fix off-by-one for reg_cache_size

[Mark Brown]

On Wed, Nov 23, 2011 at 12:46:11PM +0800, Axel Lin wrote:
> Just checking the code in cs42l51_fill_cache():
> The cache pointer points to codec->reg_cache + 1.
> I think it is because CS42L51_FIRSTREG is 0x01,
> so codec->reg_cache[0] is not used here.

Applied, thanks.

Re: [PATCH 1/2] ASoC: cs42l51: Clear CS42L51_MIC_POWER_CTL_AUTO bit for MODE_SLAVE and MODE_MASTER

[Mark Brown]

On Wed, Nov 23, 2011 at 12:44:45PM +0800, Axel Lin wrote:

> Enables the auto-detect circuitry for detecting the speed mode
> of the CODEC when operating as a slave.
> When AUTO is enabled, the MCLK/LRCK ratio must be implemented
> according to Table 3 on page 39. The
> SPEED[1:0] bits are ignored when this bit is enabled.
> Speed is determined by the MCLK/LRCK ratio.

> SPEED[1:0] bits are ignored when this bit is enabled.
> Thus we need to clear this bit for MODE_SLAVE and MODE_MASTER
> because the default of this bit is 1 (Enable).

It's not clear to me that putting the device into manual mode is the
best thing here - if the device can figure things out automatically it
seems like from a defensiveness point of view it'd be better to let it
do that.  According to the above it'll ignore the setting in the
register in slave mode so there's no harm in setting it (and it
simplifies the code) but I don't see a pressing need to actually pay
attention to it if we don't have to.