[U-Boot] [PATCH 02/16] Blackfin: bf609-ezkit: new board port

[Bob Liu <lliubbo@gmail.com>]

From: Mike Frysinger <vapier@gentoo.org>

Add basic support for new board bf609-ezkit.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Bob Liu <lliubbo@gmail.com>
---
 arch/blackfin/cpu/initcode.c                   |   96 ++++++++++-----
 arch/blackfin/cpu/initcode.h                   |    9 ++
 arch/blackfin/cpu/serial1.h                    |   19 +++
 arch/blackfin/cpu/serial4.h                    |   35 +++++-
 arch/blackfin/include/asm/mach-bf609/portmux.h |    5 +
 arch/blackfin/include/asm/mach-bf609/ports.h   |   56 +++++++--
 board/bf609-ezkit/Makefile                     |   54 +++++++++
 board/bf609-ezkit/bf609-ezkit.c                |   63 ++++++++++
 boards.cfg                                     |    1 +
 common/cmd_reginfo.c                           |    4 +-
 include/configs/bf609-ezkit.h                  |  148 ++++++++++++++++++++++++
 11 files changed, 446 insertions(+), 44 deletions(-)
 create mode 100644 board/bf609-ezkit/Makefile
 create mode 100644 board/bf609-ezkit/bf609-ezkit.c
 create mode 100644 include/configs/bf609-ezkit.h

diff --git a/arch/blackfin/cpu/initcode.c b/arch/blackfin/cpu/initcode.c
index ae3fe7a..9888f10 100644
--- a/arch/blackfin/cpu/initcode.c
+++ b/arch/blackfin/cpu/initcode.c
@@ -23,16 +23,18 @@
 
 #include "serial.h"
 
-#if 0
-
+#ifndef __ADSPBF60x__
 #include <asm/mach-common/bits/pll.h>
+#else
+#include <asm/mach-common/bits/cgu.h>
+#endif
 
 __attribute__((always_inline))
 static inline void serial_init(void)
 {
 	uint32_t uart_base = UART_BASE;
 
-#ifdef __ADSPBF54x__
+#if defined(__ADSPBF54x__) || defined(__ADSPBF60x__)
 # ifdef BFIN_BOOT_UART_USE_RTS
 #  define BFIN_UART_USE_RTS 1
 # else
@@ -42,7 +44,11 @@ static inline void serial_init(void)
 		size_t i;
 
 		/* force RTS rather than relying on auto RTS */
+#if BFIN_UART_HW_VER < 4
 		bfin_write16(&pUART->mcr, bfin_read16(&pUART->mcr) | FCPOL);
+#else
+		bfin_write32(&pUART->control, bfin_read32(&pUART->control) | FCPOL);
+#endif
 
 		/* Wait for the line to clear up.  We cannot rely on UART
 		 * registers as none of them reflect the status of the RSR.
@@ -86,12 +92,16 @@ static inline void serial_init(void)
 __attribute__((always_inline))
 static inline void serial_deinit(void)
 {
-#ifdef __ADSPBF54x__
+#if defined(__ADSPBF54x__) || defined(__ADSPBF60x__)
 	uint32_t uart_base = UART_BASE;
 
 	if (BFIN_UART_USE_RTS && CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) {
 		/* clear forced RTS rather than relying on auto RTS */
+#if BFIN_UART_HW_VER < 4
 		bfin_write16(&pUART->mcr, bfin_read16(&pUART->mcr) & ~FCPOL);
+#else
+		bfin_write32(&pUART->control, bfin_read32(&pUART->control) & ~FCPOL);
+#endif
 	}
 #endif
 }
@@ -107,7 +117,7 @@ static inline void serial_putc(char c)
 	if (c == '\n')
 		serial_putc('\r');
 
-	bfin_write16(&pUART->thr, c);
+	bfin_write(&pUART->thr, c);
 
 	while (!(_lsr_read(pUART) & TEMT))
 		continue;
@@ -156,6 +166,25 @@ program_nmi_handler(void)
 # define bfin_write_SPI_BAUD bfin_write_SPI0_BAUD
 #endif
 
+#ifdef __ADSPBF60x__
+
+#ifndef CONFIG_CGU_CTL_VAL
+# define CONFIG_CGU_CTL_VAL ((CONFIG_VCO_MULT << 8) | CONFIG_CLKIN_HALF)
+#endif
+
+#ifndef CONFIG_CGU_DIV_VAL
+# define CONFIG_CGU_DIV_VAL \
+	(1 << UPDT_P) | \
+	((CONFIG_CCLK_DIV   << CSEL_P)   | \
+	 (CONFIG_SCLK0_DIV  << S0SEL_P)  | \
+	 (CONFIG_SCLK_DIV << SYSSEL_P) | \
+	 (CONFIG_SCLK1_DIV  << S1SEL_P)  | \
+	 (CONFIG_DCLK_DIV   << DSEL_P)   | \
+	 (CONFIG_OCLK_DIV   << OSEL_P))
+#endif
+
+#else /* __ADSPBF60x__ */
+
 /* PLL_DIV defines */
 #ifndef CONFIG_PLL_DIV_VAL
 # if (CONFIG_CCLK_DIV == 1)
@@ -279,6 +308,8 @@ program_nmi_handler(void)
 # endif
 #endif
 
+#endif /*  __ADSPBF60x__ */
+
 __attribute__((always_inline)) static inline void
 program_early_devices(ADI_BOOT_DATA *bs, uint *sdivB, uint *divB, uint *vcoB)
 {
@@ -287,8 +318,12 @@ program_early_devices(ADI_BOOT_DATA *bs, uint *sdivB, uint *divB, uint *vcoB)
 	/* Save the clock pieces that are used in baud rate calculation */
 	if (BFIN_DEBUG_EARLY_SERIAL || CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) {
 		serial_putc('b');
+#ifdef __ADSPBF60x__
+
+#else
 		*sdivB = bfin_read_PLL_DIV() & 0xf;
 		*vcoB = (bfin_read_PLL_CTL() >> 9) & 0x3f;
+#endif
 		*divB = serial_early_get_div();
 		serial_putc('c');
 	}
@@ -341,6 +376,10 @@ maybe_self_refresh(ADI_BOOT_DATA *bs)
 	if (!CONFIG_MEM_SIZE)
 		return false;
 
+#ifdef __ADSPBF60x__
+
+#else /* __ADSPBF60x__ */
+
 	/* If external memory is enabled, put it into self refresh first. */
 #if defined(EBIU_RSTCTL)
 	if (bfin_read_EBIU_RSTCTL() & DDR_SRESET) {
@@ -356,6 +395,7 @@ maybe_self_refresh(ADI_BOOT_DATA *bs)
 	}
 #endif
 
+#endif /* __ADSPBF60x__ */
 	serial_putc('c');
 
 	return false;
@@ -368,6 +408,15 @@ program_clocks(ADI_BOOT_DATA *bs, bool put_into_srfs)
 
 	serial_putc('a');
 
+#ifdef __ADSPBF60x__
+
+	bfin_write_CGU_CTL(CONFIG_CGU_CTL_VAL);
+	bfin_write_CGU_DIV(CONFIG_CGU_DIV_VAL);
+	while (!(bfin_read_CGU_STAT() & CLKSALGN))
+		continue;
+
+#else /* __ADSPBF60x__ */
+
 	vr_ctl = bfin_read_VR_CTL();
 
 	serial_putc('b');
@@ -495,6 +544,8 @@ program_clocks(ADI_BOOT_DATA *bs, bool put_into_srfs)
 		serial_putc('n');
 	}
 
+#endif /* __ADSPBF60x__ */
+
 	serial_putc('o');
 
 	return vr_ctl;
@@ -513,14 +564,18 @@ update_serial_clocks(ADI_BOOT_DATA *bs, uint sdivB, uint divB, uint vcoB)
 	if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) {
 		serial_putc('b');
 		unsigned int sdivR, vcoR;
+#ifdef __ADSPBF60x__
+
+#else
 		sdivR = bfin_read_PLL_DIV() & 0xf;
 		vcoR = (bfin_read_PLL_CTL() >> 9) & 0x3f;
+#endif
 		int dividend = sdivB * divB * vcoR;
 		int divisor = vcoB * sdivR;
 		unsigned int quotient;
 		for (quotient = 0; dividend > 0; ++quotient)
 			dividend -= divisor;
-		serial_early_put_div(UART_BASE, quotient - ANOMALY_05000230);
+		serial_early_put_div(quotient - ANOMALY_05000230);
 		serial_putc('c');
 	}
 
@@ -537,6 +592,10 @@ program_memory_controller(ADI_BOOT_DATA *bs, bool put_into_srfs)
 
 	serial_putc('b');
 
+#ifdef __ADSPBF60x__
+
+#else /* __ADSPBF60x__ */
+
 	/* Program the external memory controller before we come out of
 	 * self-refresh.  This only works with our SDRAM controller.
 	 */
@@ -589,6 +648,7 @@ program_memory_controller(ADI_BOOT_DATA *bs, bool put_into_srfs)
 # endif
 #endif
 
+#endif /* __ADSPBF60x__ */
 	serial_putc('e');
 }
 
@@ -696,27 +756,3 @@ void initcode(ADI_BOOT_DATA *bs)
 	serial_deinit();
 }
 
-#else
-
-#include <asm/mach-common/bits/cgu.h>
-
-#ifndef CONFIG_CGU_CTL_VAL
-# define CONFIG_CGU_CTL_VAL ((CONFIG_VCO_MULT << 8) | CONFIG_CLKIN_HALF)
-#endif
-
-#ifndef CONFIG_CGU_DIV_VAL
-# define CONFIG_CGU_DIV_VAL \
-	((CONFIG_CCLK_DIV   << CSEL_P)   | \
-	 (CONFIG_SCLK0_DIV  << S0SEL_P)  | \
-	 (CONFIG_SYSCLK_DIV << SYSSEL_P) | \
-	 (CONFIG_SCLK1_DIV  << S1SEL_P)  | \
-	 (CONFIG_DCLK_DIV   << DSEL_P)   | \
-	 (CONFIG_OCLK_DIV   << OSEL_P))
-#endif
-
-BOOTROM_CALLED_FUNC_ATTR
-void initcode(ADI_BOOT_DATA *bs)
-{
-}
-
-#endif
diff --git a/arch/blackfin/cpu/initcode.h b/arch/blackfin/cpu/initcode.h
index e0aad6d..d263ab3 100644
--- a/arch/blackfin/cpu/initcode.h
+++ b/arch/blackfin/cpu/initcode.h
@@ -15,6 +15,8 @@
 # define serial_putc(c)
 #endif
 
+#ifndef __ADSPBF60x__
+
 #ifndef CONFIG_EBIU_RSTCTL_VAL
 # define CONFIG_EBIU_RSTCTL_VAL 0 /* only MDDRENABLE is useful */
 #endif
@@ -30,6 +32,8 @@
 # error invalid EBIU_DDRQUE value: must not set reserved bits
 #endif
 
+#endif /* __ADSPBF60x__ */
+
 __attribute__((always_inline)) static inline void
 program_async_controller(ADI_BOOT_DATA *bs)
 {
@@ -45,6 +49,10 @@ program_async_controller(ADI_BOOT_DATA *bs)
 
 	serial_putc('a');
 
+#ifdef __ADSPBF60x__
+
+#else /* __ADSPBF60x__ */
+
 	/* Program the async banks controller. */
 	bfin_write_EBIU_AMBCTL0(CONFIG_EBIU_AMBCTL0_VAL);
 	bfin_write_EBIU_AMBCTL1(CONFIG_EBIU_AMBCTL1_VAL);
@@ -65,6 +73,7 @@ program_async_controller(ADI_BOOT_DATA *bs)
 # endif
 #endif
 
+#endif
 	serial_putc('c');
 }
 
diff --git a/arch/blackfin/cpu/serial1.h b/arch/blackfin/cpu/serial1.h
index eb169e2..0d038d5 100644
--- a/arch/blackfin/cpu/serial1.h
+++ b/arch/blackfin/cpu/serial1.h
@@ -212,6 +212,25 @@ static inline void serial_early_set_baud(uint32_t uart_base, uint32_t baud)
 }
 
 __attribute__((always_inline))
+static inline void serial_early_put_div(uint16_t divisor)
+{
+	uint32_t uart_base = UART_BASE;
+
+	/* Set DLAB in LCR to Access DLL and DLH */
+	ACCESS_LATCH();
+	SSYNC();
+
+	/* Program the divisor to get the baud rate we want */
+	bfin_write(&pUART->dll, LOB(divisor));
+	bfin_write(&pUART->dlh, HIB(divisor));
+	SSYNC();
+
+	/* Clear DLAB in LCR to Access THR RBR IER */
+	ACCESS_PORT_IER();
+	SSYNC();
+}
+
+__attribute__((always_inline))
 static inline uint16_t serial_early_get_div(void)
 {
 	uint32_t uart_base = UART_BASE;
diff --git a/arch/blackfin/cpu/serial4.h b/arch/blackfin/cpu/serial4.h
index 088363a..bf4db6f 100644
--- a/arch/blackfin/cpu/serial4.h
+++ b/arch/blackfin/cpu/serial4.h
@@ -43,6 +43,26 @@ typedef uint32_t uart_lsr_t;
 __attribute__((always_inline))
 static inline void serial_early_do_portmux(void)
 {
+#if defined(__ADSPBF60x__)
+# define DO_MUX(port, tx, rx, func) do \
+{\
+	bfin_write_PORT##port##_MUX((bfin_read_PORT##port##_MUX() & ~(PORT_x_MUX_##tx##_MASK | PORT_x_MUX_##rx##_MASK)) | PORT_x_MUX_##tx##_FUNC_##func | PORT_x_MUX_##rx##_FUNC_##func); \
+	bfin_write_PORT##port##_FER_SET(P##port##tx | P##port##rx);\
+} while (0);
+	switch (CONFIG_UART_CONSOLE) {
+	case 0:
+		DO_MUX(D, 7, 8, 2);
+		break; /* Port D; PD7 and PD8; function 2 */
+	case 1:
+		DO_MUX(G, 15, 14, 1);
+		break; /* Port G; PG15 and PH14; function 1 */
+	}
+	SSYNC();
+#else
+# if (P_UART(RX) & P_DEFINED) || (P_UART(TX) & P_DEFINED)
+#  error "missing portmux logic for UART"
+# endif
+#endif
 }
 
 __attribute__((always_inline))
@@ -50,7 +70,7 @@ static inline uint32_t uart_sclk(void)
 {
 #if defined(BFIN_IN_INITCODE) || defined(CONFIG_DEBUG_EARLY_SERIAL)
 	/* We cannot use get_sclk() early on as it uses caches in external memory */
-	return (CONFIG_CLKIN_HZ * CONFIG_VCO_MULT / CONFIG_SYSCLK_DIV / CONFIG_SCLK0_DIV);
+	return (CONFIG_CLKIN_HZ * CONFIG_VCO_MULT / CONFIG_SCLK_DIV / CONFIG_SCLK0_DIV);
 #else
 	return get_sclk0();
 #endif
@@ -94,15 +114,22 @@ static inline int serial_early_enabled(uint32_t uart_base)
 __attribute__((always_inline))
 static inline void serial_early_set_baud(uint32_t uart_base, uint32_t baud)
 {
-	uint32_t divisor = uart_sclk() / baud;
+	uint32_t divisor = uart_sclk() / (baud * 16);
 
 	/* Program the divisor to get the baud rate we want */
-	bfin_write(&pUART->clock, divisor | 0x80000000);
+	bfin_write(&pUART->clock, divisor);
 	SSYNC();
 }
 
 __attribute__((always_inline))
-static inline uint16_t serial_early_get_div(void)
+static inline void serial_early_put_div(uint32_t divisor)
+{
+	uint32_t uart_base = UART_BASE;
+	bfin_write(&pUART->clock, divisor);
+}
+
+__attribute__((always_inline))
+static inline uint32_t serial_early_get_div(void)
 {
 	uint32_t uart_base = UART_BASE;
 	return bfin_read(&pUART->clock);
diff --git a/arch/blackfin/include/asm/mach-bf609/portmux.h b/arch/blackfin/include/asm/mach-bf609/portmux.h
index 5356334..1cf6fd8 100644
--- a/arch/blackfin/include/asm/mach-bf609/portmux.h
+++ b/arch/blackfin/include/asm/mach-bf609/portmux.h
@@ -33,6 +33,8 @@
 	P_MII0_PHYINT, \
 	P_MII0_CRS, \
 	P_MII0_MDC, \
+	P_PTP0_PPS, \
+	P_PTP1_PPS, \
 	P_MII0_MDIO, 0}
 
 #define P_MII1_MDC	(P_DEFINED | P_IDENT(GPIO_PE10) | P_FUNCT(0))
@@ -244,6 +246,9 @@
 #define P_AMS2		(P_DEFINED | P_IDENT(GPIO_PB4) | P_FUNCT(0))
 #define P_AMS3		(P_DEFINED | P_IDENT(GPIO_PB5) | P_FUNCT(0))
 
+#define P_ABE0		(P_DEFINED | P_IDENT(GPIO_PB4) | P_FUNCT(1))
+#define P_ABE1		(P_DEFINED | P_IDENT(GPIO_PB5) | P_FUNCT(1))
+
 /* CAN */
 #define P_CAN0_TX	(P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(2))
 #define P_CAN0_RX	(P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(2))
diff --git a/arch/blackfin/include/asm/mach-bf609/ports.h b/arch/blackfin/include/asm/mach-bf609/ports.h
index cb536bc..b361c7b 100644
--- a/arch/blackfin/include/asm/mach-bf609/ports.h
+++ b/arch/blackfin/include/asm/mach-bf609/ports.h
@@ -6,14 +6,22 @@
 #define __BFIN_PERIPHERAL_PORT__
 
 /* PORTx_MUX Masks */
-#define PORT_x_MUX_0_MASK	0x0003
-#define PORT_x_MUX_1_MASK	0x000C
-#define PORT_x_MUX_2_MASK	0x0030
-#define PORT_x_MUX_3_MASK	0x00C0
-#define PORT_x_MUX_4_MASK	0x0300
-#define PORT_x_MUX_5_MASK	0x0C00
-#define PORT_x_MUX_6_MASK	0x3000
-#define PORT_x_MUX_7_MASK	0xC000
+#define PORT_x_MUX_0_MASK	0x00000003
+#define PORT_x_MUX_1_MASK	0x0000000C
+#define PORT_x_MUX_2_MASK	0x00000030
+#define PORT_x_MUX_3_MASK	0x000000C0
+#define PORT_x_MUX_4_MASK	0x00000300
+#define PORT_x_MUX_5_MASK	0x00000C00
+#define PORT_x_MUX_6_MASK	0x00003000
+#define PORT_x_MUX_7_MASK	0x0000C000
+#define PORT_x_MUX_8_MASK	0x00030000
+#define PORT_x_MUX_9_MASK	0x000C0000
+#define PORT_x_MUX_10_MASK	0x00300000
+#define PORT_x_MUX_11_MASK	0x00C00000
+#define PORT_x_MUX_12_MASK	0x03000000
+#define PORT_x_MUX_13_MASK	0x0C000000
+#define PORT_x_MUX_14_MASK	0x30000000
+#define PORT_x_MUX_15_MASK	0xC0000000
 
 #define PORT_x_MUX_FUNC_1	(0x0)
 #define PORT_x_MUX_FUNC_2	(0x1)
@@ -51,6 +59,38 @@
 #define PORT_x_MUX_7_FUNC_2	(PORT_x_MUX_FUNC_2 << 14)
 #define PORT_x_MUX_7_FUNC_3	(PORT_x_MUX_FUNC_3 << 14)
 #define PORT_x_MUX_7_FUNC_4	(PORT_x_MUX_FUNC_4 << 14)
+#define PORT_x_MUX_8_FUNC_1	(PORT_x_MUX_FUNC_1 << 16)
+#define PORT_x_MUX_8_FUNC_2	(PORT_x_MUX_FUNC_2 << 16)
+#define PORT_x_MUX_8_FUNC_3	(PORT_x_MUX_FUNC_3 << 16)
+#define PORT_x_MUX_8_FUNC_4	(PORT_x_MUX_FUNC_4 << 16)
+#define PORT_x_MUX_9_FUNC_1	(PORT_x_MUX_FUNC_1 << 18)
+#define PORT_x_MUX_9_FUNC_2	(PORT_x_MUX_FUNC_2 << 18)
+#define PORT_x_MUX_9_FUNC_3	(PORT_x_MUX_FUNC_3 << 18)
+#define PORT_x_MUX_9_FUNC_4	(PORT_x_MUX_FUNC_4 << 18)
+#define PORT_x_MUX_10_FUNC_1	(PORT_x_MUX_FUNC_1 << 20)
+#define PORT_x_MUX_10_FUNC_2	(PORT_x_MUX_FUNC_2 << 20)
+#define PORT_x_MUX_10_FUNC_3	(PORT_x_MUX_FUNC_3 << 20)
+#define PORT_x_MUX_10_FUNC_4	(PORT_x_MUX_FUNC_4 << 20)
+#define PORT_x_MUX_11_FUNC_1	(PORT_x_MUX_FUNC_1 << 22)
+#define PORT_x_MUX_11_FUNC_2	(PORT_x_MUX_FUNC_2 << 22)
+#define PORT_x_MUX_11_FUNC_3	(PORT_x_MUX_FUNC_3 << 22)
+#define PORT_x_MUX_11_FUNC_4	(PORT_x_MUX_FUNC_4 << 22)
+#define PORT_x_MUX_12_FUNC_1	(PORT_x_MUX_FUNC_1 << 24)
+#define PORT_x_MUX_12_FUNC_2	(PORT_x_MUX_FUNC_2 << 24)
+#define PORT_x_MUX_12_FUNC_3	(PORT_x_MUX_FUNC_3 << 24)
+#define PORT_x_MUX_12_FUNC_4	(PORT_x_MUX_FUNC_4 << 24)
+#define PORT_x_MUX_13_FUNC_1	(PORT_x_MUX_FUNC_1 << 26)
+#define PORT_x_MUX_13_FUNC_2	(PORT_x_MUX_FUNC_2 << 26)
+#define PORT_x_MUX_13_FUNC_3	(PORT_x_MUX_FUNC_3 << 26)
+#define PORT_x_MUX_13_FUNC_4	(PORT_x_MUX_FUNC_4 << 26)
+#define PORT_x_MUX_14_FUNC_1	(PORT_x_MUX_FUNC_1 << 28)
+#define PORT_x_MUX_14_FUNC_2	(PORT_x_MUX_FUNC_2 << 28)
+#define PORT_x_MUX_14_FUNC_3	(PORT_x_MUX_FUNC_3 << 28)
+#define PORT_x_MUX_14_FUNC_4	(PORT_x_MUX_FUNC_4 << 28)
+#define PORT_x_MUX_15_FUNC_1	(PORT_x_MUX_FUNC_1 << 30)
+#define PORT_x_MUX_15_FUNC_2	(PORT_x_MUX_FUNC_2 << 30)
+#define PORT_x_MUX_15_FUNC_3	(PORT_x_MUX_FUNC_3 << 30)
+#define PORT_x_MUX_15_FUNC_4	(PORT_x_MUX_FUNC_4 << 30)
 
 #include "../mach-common/bits/ports-a.h"
 #include "../mach-common/bits/ports-b.h"
diff --git a/board/bf609-ezkit/Makefile b/board/bf609-ezkit/Makefile
new file mode 100644
index 0000000..cde8168
--- /dev/null
+++ b/board/bf609-ezkit/Makefile
@@ -0,0 +1,54 @@
+#
+# U-boot - Makefile
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y	:= $(BOARD).o
+
+SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS-y))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/bf609-ezkit/bf609-ezkit.c b/board/bf609-ezkit/bf609-ezkit.c
new file mode 100644
index 0000000..ceb2eb9
--- /dev/null
+++ b/board/bf609-ezkit/bf609-ezkit.c
@@ -0,0 +1,63 @@
+/*
+ * U-boot - main board file
+ *
+ * Copyright (c) 2008-2011 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/blackfin.h>
+#include <asm/io.h>
+#include <asm/portmux.h>
+
+int checkboard(void)
+{
+	printf("Board: ADI BF609 EZ-Kit board\n");
+	printf("       Support: http://blackfin.uclinux.org/\n");
+	return 0;
+}
+
+int board_early_init_f(void)
+{
+	static const unsigned short pins[] = {
+		P_A4, P_A5, P_A6, P_A7, P_A8, P_A9, P_A10, P_A11, P_A12, P_A13,
+		P_A14, P_A15, P_A16, P_A17, P_A18, P_A19, P_A20, P_A21, P_A22,
+		P_A23, P_A24, P_A25, P_AMS1, P_ABE0, P_ABE1, 0,
+	};
+	peripheral_request_list(pins, "smc");
+
+	return 0;
+}
+
+#ifdef CONFIG_DESIGNWARE_ETH
+#define TWI_ADDR 0x20
+int board_eth_init(bd_t *bis)
+{
+	int ret = 0;
+	uchar idira = 0x0;
+	uchar lata = 0xff;
+
+	if (CONFIG_DW_PORTS & 1) {
+		static const unsigned short pins[] = P_RMII0;
+		if (!peripheral_request_list(pins, "emac0")) {
+			/* enable phy clk */
+			ret = i2c_write(TWI_ADDR, 0x0, 1, &idira, 1);
+			if (!ret) {
+				ret = i2c_write(TWI_ADDR, 0x14, 1, &lata, 1);
+				if (!ret)
+					ret += designware_initialize(0, EMAC0_MACCFG, 1, 0);
+			}
+		}
+	}
+
+	if (CONFIG_DW_PORTS & 2) {
+		static const unsigned short pins[] = P_RMII1;
+		if (!peripheral_request_list(pins, "emac1"))
+			ret += designware_initialize(1, EMAC1_MACCFG, 1, 0, 1);
+	}
+
+	return ret;
+}
+#endif
diff --git a/boards.cfg b/boards.cfg
index 2d36d83..8d275a3 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -313,6 +313,7 @@ bf538f-ezkit                 blackfin    blackfin
 bf548-ezkit                  blackfin    blackfin
 bf561-acvilon                blackfin    blackfin
 bf561-ezkit                  blackfin    blackfin
+bf609-ezkit                  blackfin    blackfin
 blackstamp                   blackfin    blackfin
 blackvme                     blackfin    blackfin
 br4                          blackfin    blackfin
diff --git a/common/cmd_reginfo.c b/common/cmd_reginfo.c
index 908876c..bf94119 100644
--- a/common/cmd_reginfo.c
+++ b/common/cmd_reginfo.c
@@ -190,7 +190,7 @@ int do_reginfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 
 #elif defined(CONFIG_BLACKFIN)
 	puts("\nSystem Configuration registers\n");
-
+#ifndef __ADSPBF60x__
 	puts("\nPLL Registers\n");
 	printf("\tPLL_DIV:   0x%04x   PLL_CTL:      0x%04x\n",
 		bfin_read_PLL_DIV(), bfin_read_PLL_CTL());
@@ -226,7 +226,7 @@ int do_reginfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	printf("\tEBIU_SDSTAT:  0x%04x   EBIU_SDGCTL:  0x%08x\n",
 		bfin_read_EBIU_SDSTAT(), bfin_read_EBIU_SDGCTL());
 # endif
-
+#endif
 #endif /* CONFIG_BLACKFIN */
 
 	return 0;
diff --git a/include/configs/bf609-ezkit.h b/include/configs/bf609-ezkit.h
new file mode 100644
index 0000000..9b1f6c2
--- /dev/null
+++ b/include/configs/bf609-ezkit.h
@@ -0,0 +1,148 @@
+/*
+ * U-boot - Configuration file for BF609 EZ-Kit board
+ */
+
+#ifndef __CONFIG_BF609_EZKIT_H__
+#define __CONFIG_BF609_EZKIT_H__
+
+#include <asm/config-pre.h>
+
+
+/*
+ * Processor Settings
+ */
+#define __ADSPBF60x__ 1
+#define __ADSPBF609__ 1
+#undef __ADSPBF592__
+#undef __ADSPBF59x__
+#define CONFIG_BFIN_CPU             bf609-0.0
+#define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_PARA
+
+
+/*
+ * Clock Settings
+ *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
+ *	SCLK = (CLKIN * VCO_MULT) / SYSCLK_DIV
+ *	SCLK0 = SCLK / SCLK0_DIV
+ *	SCLK1 = SCLK / SCLK1_DIV
+ */
+/* CONFIG_CLKIN_HZ is any value in Hz					*/
+#define CONFIG_CLKIN_HZ			25000000
+/* CLKIN_HALF controls the DF bit in PLL_CTL      0 = CLKIN		*/
+/*                                                1 = CLKIN / 2		*/
+#define CONFIG_CLKIN_HALF		0
+
+/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL		*/
+/* Values can range from 0-127 (where 0 means 128)			*/
+#define CONFIG_VCO_MULT			15
+
+/* CCLK_DIV controls the core clock divider				*/
+/* Values can range from 0-31 (where 0 means 32)			*/
+#define CONFIG_CCLK_DIV			1
+/* SCLK_DIV controls the system clock divider				*/
+/* Values can range from 0-31 (where 0 means 32)			*/
+#define CONFIG_SYSCLK_DIV		3
+/* Values can range from 0-7 (where 0 means 8)				*/
+#define CONFIG_SCLK0_DIV		1
+#define CONFIG_SCLK1_DIV		2
+/* DCLK_DIV controls the DDR clock divider				*/
+/* Values can range from 0-31 (where 0 means 32)			*/
+#define CONFIG_DCLK_DIV			2
+/* OCLK_DIV controls the output clock divider				*/
+/* Values can range from 0-127 (where 0 means 128)			*/
+#define CONFIG_OCLK_DIV			16
+
+#define CONFIG_BFIN_GET_VCO CONFIG_CLKIN_HZ
+#define CONFIG_PLL_CLK  (get_vco()*CONFIG_VCO_MULT)
+
+#define CONFIG_BFIN_GET_CCLK (CONFIG_PLL_CLK/CONFIG_CCLK_DIV)
+#define CONFIG_CCLK_HZ CONFIG_BFIN_GET_CCLK
+
+#define CONFIG_BFIN_GET_SCLK (CONFIG_PLL_CLK/CONFIG_SYSCLK_DIV)
+#define CONFIG_BFIN_GET_SCLK0 (get_sclk()/CONFIG_SCLK0_DIV)
+#define CONFIG_BFIN_GET_SCLK1 (get_sclk()/CONFIG_SCLK1_DIV)
+
+
+/*
+ * Memory Settings
+ */
+#define CONFIG_MEM_SIZE		32
+
+#define CONFIG_SMC_GCTL_VAL	0x00000010
+#define CONFIG_SMC_B1CTL_VAL	0x01002001
+#define CONFIG_SMC_B1TIM_VAL	0x08070977
+#define CONFIG_SMC_B1ETIM_VAL	0x00092231
+
+#define CONFIG_SYS_MONITOR_LEN	(256 * 1024)
+#define CONFIG_SYS_MALLOC_LEN	(256 * 1024)
+
+#define CONFIG_ICACHE_OFF
+#define CONFIG_DCACHE_OFF
+
+/*
+ * Network Settings
+ */
+#define ADI_CMDS_NETWORK	1
+#define CONFIG_NETCONSOLE	1
+#define CONFIG_NET_MULTI	1
+#define CONFIG_HOSTNAME		bf609-ezkit
+#define CONFIG_DESIGNWARE_ETH
+#define CONFIG_DW_PORTS		1
+#define CONFIG_DW_AUTONEG
+#define CONFIG_DW_ALTDESCRIPTOR
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_MII
+#define CONFIG_MII
+#define CONFIG_ETHADDR	02:80:ad:20:31:e8
+
+/* i2c Settings */
+#define CONFIG_BFIN_TWI_I2C	1
+#define CONFIG_HARD_I2C		1
+
+/*
+ * Flash Settings
+ */
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_JFFS2
+#define CONFIG_SYS_FLASH_CFI_WIDTH     2
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_BASE          0xb0000000
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_SYS_MAX_FLASH_BANKS     1
+#define CONFIG_SYS_MAX_FLASH_SECT      131
+
+/*
+ * Env Storage Settings
+ */
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_SIZE 0x600
+#undef CONFIG_CMD_EXPORTENV
+#undef CONFIG_CMD_IMPORTENV
+
+/*
+ * Misc Settings
+ */
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_UART_CONSOLE	0
+#define CONFIG_BAUDRATE 57600
+
+#define CONFIG_DEBUG_DUMP	1
+#define CONFIG_KALLSYMS		1
+
+#define CONFIG_CMD_MEMORY
+
+#define CONFIG_SYS_MEMTEST_END (CONFIG_STACKBASE - 20*1024*1024 + 4)
+
+#if 0
+#define CONFIG_UART_MEM 1024
+#undef CONFIG_UART_CONSOLE
+#undef CONFIG_JTAG_CONSOLE
+#undef CONFIG_UART_CONSOLE_IS_JTAG
+#endif
+
+/*
+ * Pull in common ADI header for remaining command/environment setup
+ */
+#include <configs/bfin_adi_common.h>
+#endif
-- 
1.7.9.5