From: Jia Liu <proljc@gmail.com>
To: qemu-devel@nongnu.org
Cc: aurelien@aurel32.net
Subject: [Qemu-devel] [PATCH v9 09/14] target-mips-ase-dsp: Add bit/manipulation instructions
Date: Thu, 27 Sep 2012 21:24:46 +0800 [thread overview]
Message-ID: <1348752291-6041-10-git-send-email-proljc@gmail.com> (raw)
In-Reply-To: <1348752291-6041-1-git-send-email-proljc@gmail.com>
Add MIPS ASE DSP Bit/Manipulation instructions.
Signed-off-by: Jia Liu <proljc@gmail.com>
---
target-mips/dsp_helper.c | 55 ++++++++++
target-mips/helper.h | 7 ++
target-mips/translate.c | 268 ++++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 330 insertions(+)
diff --git a/target-mips/dsp_helper.c b/target-mips/dsp_helper.c
index b98be0d..7516242 100644
--- a/target-mips/dsp_helper.c
+++ b/target-mips/dsp_helper.c
@@ -3186,6 +3186,61 @@ DM_OPERATE(dmsubu, mul_u32_u32, 0, 0);
#undef DM_OPERATE
#endif
+/** DSP Bit/Manipulation Sub-class insns **/
+target_ulong helper_bitrev(target_ulong rt)
+{
+ int32_t temp;
+ uint32_t rd;
+ int i;
+
+ temp = rt & MIPSDSP_LO;
+ rd = 0;
+ for (i = 0; i < 16; i++) {
+ rd = (rd << 1) | (temp & 1);
+ temp = temp >> 1;
+ }
+
+ return (target_ulong)rd;
+}
+
+#define BIT_INSV(name, posfilter, sizefilter, ret_type) \
+target_ulong helper_##name(CPUMIPSState *env, target_ulong rs, \
+ target_ulong rt) \
+{ \
+ uint32_t pos, size, msb, lsb; \
+ target_ulong filter; \
+ target_ulong temp, temprs, temprt; \
+ target_ulong dspc; \
+ \
+ dspc = env->active_tc.DSPControl; \
+ \
+ pos = dspc & posfilter; \
+ size = (dspc >> 7) & sizefilter; \
+ \
+ msb = pos + size - 1; \
+ lsb = pos; \
+ \
+ if (lsb > msb || (msb > TARGET_LONG_BITS)) { \
+ return rt; \
+ } \
+ \
+ filter = ((int32_t)0x01 << size) - 1; \
+ filter = filter << pos; \
+ temprs = rs & filter; \
+ temprt = rt & ~filter; \
+ temp = temprs | temprt; \
+ \
+ return (target_long)(ret_type)temp; \
+}
+
+BIT_INSV(insv, 0x1F, 0x1F, int32_t);
+#ifdef TARGET_MIPS64
+BIT_INSV(dinsv, 0x7F, 0x3F, target_long);
+#endif
+
+#undef BIT_INSV
+
+
#undef MIPSDSP_LHI
#undef MIPSDSP_LLO
#undef MIPSDSP_HI
diff --git a/target-mips/helper.h b/target-mips/helper.h
index 6a6ca99..31475a2 100644
--- a/target-mips/helper.h
+++ b/target-mips/helper.h
@@ -617,4 +617,11 @@ DEF_HELPER_FLAGS_4(dmsub, 0, void, tl, tl, i32, env)
DEF_HELPER_FLAGS_4(dmsubu, 0, void, tl, tl, i32, env)
#endif
+/* DSP Bit/Manipulation Sub-class insns */
+DEF_HELPER_FLAGS_1(bitrev, TCG_CALL_CONST | TCG_CALL_PURE, tl, tl)
+DEF_HELPER_FLAGS_3(insv, 0, tl, env, tl, tl)
+#if defined(TARGET_MIPS64)
+DEF_HELPER_FLAGS_3(dinsv, 0, tl, env, tl, tl);
+#endif
+
#include "def-helper.h"
diff --git a/target-mips/translate.c b/target-mips/translate.c
index 1ec6edc..d5c2419 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -343,6 +343,11 @@ enum {
#if defined(TARGET_MIPS64)
OPC_DPAQ_W_QH_DSP = 0x34 | OPC_SPECIAL3,
#endif
+ /* DSP Bit/Manipulation Sub-class */
+ OPC_INSV_DSP = 0x0C | OPC_SPECIAL3,
+#if defined(TARGET_MIPS64)
+ OPC_DINSV_DSP = 0x0D | OPC_SPECIAL3,
+#endif
};
/* BSHFL opcodes */
@@ -450,6 +455,12 @@ enum {
OPC_PRECEU_PH_QBR = (0x1D << 6) | OPC_ABSQ_S_PH_DSP,
OPC_PRECEU_PH_QBLA = (0x1E << 6) | OPC_ABSQ_S_PH_DSP,
OPC_PRECEU_PH_QBRA = (0x1F << 6) | OPC_ABSQ_S_PH_DSP,
+ /* DSP Bit/Manipulation Sub-class */
+ OPC_BITREV = (0x1B << 6) | OPC_ABSQ_S_PH_DSP,
+ OPC_REPL_QB = (0x02 << 6) | OPC_ABSQ_S_PH_DSP,
+ OPC_REPLV_QB = (0x03 << 6) | OPC_ABSQ_S_PH_DSP,
+ OPC_REPL_PH = (0x0A << 6) | OPC_ABSQ_S_PH_DSP,
+ OPC_REPLV_PH = (0x0B << 6) | OPC_ABSQ_S_PH_DSP,
};
#define MASK_CMPU_EQ_QB(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
@@ -518,6 +529,12 @@ enum {
OPC_MULSA_W_PH = (0x02 << 6) | OPC_DPA_W_PH_DSP,
};
+#define MASK_INSV(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
+enum {
+ /* DSP Bit/Manipulation Sub-class */
+ OPC_INSV = (0x00 << 6) | OPC_INSV_DSP,
+};
+
#if defined(TARGET_MIPS64)
#define MASK_ABSQ_S_QH(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
enum {
@@ -539,6 +556,13 @@ enum {
OPC_ABSQ_S_OB = (0x01 << 6) | OPC_ABSQ_S_QH_DSP,
OPC_ABSQ_S_PW = (0x11 << 6) | OPC_ABSQ_S_QH_DSP,
OPC_ABSQ_S_QH = (0x09 << 6) | OPC_ABSQ_S_QH_DSP,
+ /* DSP Bit/Manipulation Sub-class */
+ OPC_REPL_OB = (0x02 << 6) | OPC_ABSQ_S_QH_DSP,
+ OPC_REPL_PW = (0x12 << 6) | OPC_ABSQ_S_QH_DSP,
+ OPC_REPL_QH = (0x0A << 6) | OPC_ABSQ_S_QH_DSP,
+ OPC_REPLV_OB = (0x03 << 6) | OPC_ABSQ_S_QH_DSP,
+ OPC_REPLV_PW = (0x13 << 6) | OPC_ABSQ_S_QH_DSP,
+ OPC_REPLV_QH = (0x0B << 6) | OPC_ABSQ_S_QH_DSP,
};
#endif
@@ -592,6 +616,14 @@ enum {
#endif
#if defined(TARGET_MIPS64)
+#define MASK_DINSV(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
+enum {
+ /* DSP Bit/Manipulation Sub-class */
+ OPC_DINSV = (0x00 << 6) | OPC_DINSV_DSP,
+};
+#endif
+
+#if defined(TARGET_MIPS64)
#define MASK_DPAQ_W_QH(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
enum {
/* MIPS DSP Multiply Sub-class insns */
@@ -13682,6 +13714,189 @@ static void gen_mipsdsp_multiply(DisasContext *ctx, uint32_t op1, uint32_t op2,
}
+static void gen_mipsdsp_bitinsn(CPUMIPSState *env, DisasContext *ctx,
+ uint32_t op1, uint32_t op2,
+ int ret, int val)
+{
+ const char *opn = "mipsdsp Bit/ Manipulation";
+ TCGv t0 = tcg_temp_new();
+ int16_t imm;
+
+ if (ret == 0) {
+ /* Treat as NOP. */
+ MIPS_DEBUG("NOP");
+ return;
+ }
+
+ switch (op1) {
+ case OPC_ABSQ_S_PH_DSP:
+ switch (op2) {
+ case OPC_BITREV:
+ check_dsp(ctx);
+ gen_helper_bitrev(cpu_gpr[ret], cpu_gpr[val]);
+ break;
+ case OPC_REPL_QB:
+ check_dsp(ctx);
+ {
+ target_long result;
+ imm = (ctx->opcode >> 16) & 0xFF;
+ result = (uint32_t)imm << 24 | \
+ (uint32_t)imm << 16 | \
+ (uint32_t)imm << 8 | \
+ (uint32_t)imm;
+#ifdef TARGET_MIPS64
+ result = (target_long)(result << 32) >> 32;
+#endif
+ tcg_gen_movi_tl(cpu_gpr[ret], result);
+ }
+ break;
+ case OPC_REPLV_QB:
+ check_dsp(ctx);
+ {
+ TCGv temp_rd;
+
+ temp_rd = tcg_temp_new();
+
+ /* we need t0 to save gpr[val] 7..0 bits. */
+ tcg_gen_ext8u_tl(t0, cpu_gpr[val]);
+ tcg_gen_mov_tl(temp_rd, t0);
+ tcg_gen_shli_tl(t0, t0, 8);
+ tcg_gen_or_tl(temp_rd, temp_rd, t0);
+ tcg_gen_mov_tl(t0, temp_rd);
+ tcg_gen_shli_tl(t0, t0, 16);
+ tcg_gen_or_tl(temp_rd, temp_rd, t0);
+#if defined(TARGET_MIPS64)
+ tcg_gen_ext32s_i64(temp_rd, temp_rd);
+#endif
+ tcg_gen_mov_tl(cpu_gpr[ret], temp_rd);
+
+ tcg_temp_free(temp_rd);
+ }
+ break;
+ case OPC_REPL_PH:
+ check_dsp(ctx);
+ {
+ imm = (ctx->opcode >> 16) & 0x03FF;
+ tcg_gen_movi_tl(cpu_gpr[ret], \
+ (target_long)((int32_t)imm << 16 | \
+ (uint32_t)(uint16_t)imm));
+ }
+ break;
+ case OPC_REPLV_PH:
+ check_dsp(ctx);
+ {
+ TCGv temp_rd;
+
+ temp_rd = tcg_temp_new();
+
+ tcg_gen_ext16u_tl(t0, cpu_gpr[val]);
+ tcg_gen_ext16s_tl(temp_rd, cpu_gpr[val]);
+ tcg_gen_shli_tl(temp_rd, temp_rd, 16);
+ tcg_gen_or_tl(temp_rd, temp_rd, t0);
+ tcg_gen_mov_tl(cpu_gpr[ret], temp_rd);
+
+ tcg_temp_free(temp_rd);
+ }
+ break;
+ }
+ break;
+#ifdef TARGET_MIPS64
+ case OPC_ABSQ_S_QH_DSP:
+ switch (op2) {
+ case OPC_REPL_OB:
+ check_dsp(ctx);
+ {
+ target_long temp;
+
+ imm = (ctx->opcode >> 16) & 0xFF;
+ temp = imm;
+ temp = (temp << 8) | temp;
+ temp = (temp << 16) | temp;
+ temp = (temp << 32) | temp;
+ tcg_gen_movi_tl(cpu_gpr[ret], temp);
+ break;
+ }
+ case OPC_REPL_PW:
+ check_dsp(ctx);
+ {
+ target_long temp;
+
+ imm = (ctx->opcode >> 16) & 0x03FF;
+ imm = (int16_t)(imm << 6) >> 6;
+ temp = ((target_long)imm << 32) \
+ | ((target_long)imm & 0xFFFFFFFF);
+ tcg_gen_movi_tl(cpu_gpr[ret], temp);
+ break;
+ }
+ case OPC_REPL_QH:
+ check_dsp(ctx);
+ {
+ target_long temp;
+
+ imm = (ctx->opcode >> 16) & 0x03FF;
+ imm = (int16_t)(imm << 6) >> 6;
+
+ temp = ((uint64_t)(uint16_t)imm << 48) | \
+ ((uint64_t)(uint16_t)imm << 32) | \
+ ((uint64_t)(uint16_t)imm << 16) | \
+ (uint64_t)(uint16_t)imm;
+ tcg_gen_movi_tl(cpu_gpr[ret], temp);
+ break;
+ }
+ case OPC_REPLV_OB:
+ check_dsp(ctx);
+ {
+ TCGv temp_rd;
+
+ temp_rd = tcg_temp_new();
+
+ tcg_gen_ext8u_tl(t0, cpu_gpr[val]);
+ tcg_gen_mov_tl(temp_rd, t0);
+ tcg_gen_shli_tl(temp_rd, temp_rd, 8);
+ tcg_gen_or_tl(temp_rd, temp_rd, t0);
+ tcg_gen_mov_tl(t0, temp_rd);
+ tcg_gen_shli_tl(temp_rd, temp_rd, 16);
+ tcg_gen_or_tl(temp_rd, temp_rd, t0);
+ tcg_gen_concat_tl_i64(temp_rd, temp_rd, temp_rd);
+
+ gen_store_gpr(temp_rd, ret);
+
+ tcg_temp_free(temp_rd);
+ break;
+ }
+ case OPC_REPLV_PW:
+ check_dsp(ctx);
+ {
+ tcg_gen_ext32u_i64(t0, cpu_gpr[val]);
+ tcg_gen_concat_tl_i64(cpu_gpr[ret], t0, t0);
+ break;
+ }
+ case OPC_REPLV_QH:
+ check_dsp(ctx);
+ {
+ TCGv temp_rd;
+
+ temp_rd = tcg_temp_new();
+
+ tcg_gen_ext16u_tl(t0, cpu_gpr[val]);
+ tcg_gen_mov_tl(temp_rd, t0);
+ tcg_gen_shli_tl(temp_rd, temp_rd, 16);
+ tcg_gen_or_tl(temp_rd, temp_rd, t0);
+ tcg_gen_concat_tl_i64(cpu_gpr[ret], temp_rd, temp_rd);
+
+ tcg_temp_free(temp_rd);
+ break;
+ }
+ }
+ break;
+#endif
+ }
+ tcg_temp_free(t0);
+
+ (void)opn; /* avoid a compiler warning */
+ MIPS_DEBUG("%s", opn);
+}
+
/* End MIPSDSP functions. */
static void decode_opc (CPUMIPSState *env, DisasContext *ctx, int *is_branch)
@@ -14108,6 +14323,13 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, int *is_branch)
case OPC_PRECEU_PH_QBRA:
gen_mipsdsp_arith(ctx, op1, op2, rd, rs, rt);
break;
+ case OPC_BITREV:
+ case OPC_REPL_QB:
+ case OPC_REPLV_QB:
+ case OPC_REPL_PH:
+ case OPC_REPLV_PH:
+ gen_mipsdsp_bitinsn(env, ctx, op1, op2, rd, rt);
+ break;
default:
MIPS_INVAL("MASK ABSQ_S.PH");
generate_exception(ctx, EXCP_RI);
@@ -14208,6 +14430,26 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, int *is_branch)
break;
}
break;
+ case OPC_INSV_DSP:
+ op2 = MASK_INSV(ctx->opcode);
+ switch (op2) {
+ case OPC_INSV:
+ check_dsp(ctx);
+ {
+ if (rt == 0) {
+ MIPS_DEBUG("NOP");
+ break;
+ }
+ gen_helper_insv(cpu_gpr[rt], cpu_env,
+ cpu_gpr[rs], cpu_gpr[rt]);
+ break;
+ }
+ default: /* Invalid */
+ MIPS_INVAL("MASK INSV");
+ generate_exception(ctx, EXCP_RI);
+ break;
+ }
+ break;
#if defined(TARGET_MIPS64)
case OPC_DEXTM ... OPC_DEXT:
case OPC_DINSM ... OPC_DINS:
@@ -14249,6 +14491,14 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, int *is_branch)
case OPC_ABSQ_S_QH:
gen_mipsdsp_arith(ctx, op1, op2, rd, rs, rt);
break;
+ case OPC_REPL_OB:
+ case OPC_REPL_PW:
+ case OPC_REPL_QH:
+ case OPC_REPLV_OB:
+ case OPC_REPLV_PW:
+ case OPC_REPLV_QH:
+ gen_mipsdsp_bitinsn(env, ctx, op1, op2, rd, rt);
+ break;
default: /* Invalid */
MIPS_INVAL("MASK ABSQ_S.QH");
generate_exception(ctx, EXCP_RI);
@@ -14355,6 +14605,24 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, int *is_branch)
break;
}
break;
+ case OPC_DINSV_DSP:
+ op2 = MASK_INSV(ctx->opcode);
+ switch (op2) {
+ case OPC_DINSV:
+ check_dsp(ctx);
+ if (rt == 0) {
+ MIPS_DEBUG("NOP");
+ break;
+ }
+ gen_helper_dinsv(cpu_gpr[rt], cpu_env,
+ cpu_gpr[rs], cpu_gpr[rt]);
+ break;
+ default: /* Invalid */
+ MIPS_INVAL("MASK DINSV");
+ generate_exception(ctx, EXCP_RI);
+ break;
+ }
+ break;
case OPC_SHLL_OB_DSP:
gen_mipsdsp_shift(ctx, op1, rd, rs, rt);
break;
--
1.7.10.2 (Apple Git-33)
next prev parent reply other threads:[~2012-09-27 13:26 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-09-27 13:24 [Qemu-devel] [PATCH v9 00/14] QEMU MIPS ASE DSP support Jia Liu
2012-09-27 13:24 ` [Qemu-devel] [PATCH v9 01/14] target-mips-ase-dsp: Add internal funtions Jia Liu
2012-10-06 14:51 ` Aurelien Jarno
2012-09-27 13:24 ` [Qemu-devel] [PATCH v9 02/14] target-mips-ase-dsp: Add dsp resources access check Jia Liu
2012-10-06 14:51 ` Aurelien Jarno
2012-09-27 13:24 ` [Qemu-devel] [PATCH v9 03/14] target-mips-ase-dsp: Use correct acc value to index cpu_HI/cpu_LO rather than using a fix number Jia Liu
2012-10-06 14:51 ` Aurelien Jarno
2012-09-27 13:24 ` [Qemu-devel] [PATCH v9 04/14] target-mips-ase-dsp: Add branch instructions Jia Liu
2012-10-06 14:51 ` Aurelien Jarno
2012-09-27 13:24 ` [Qemu-devel] [PATCH v9 05/14] target-mips-ase-dsp: Add load instructions Jia Liu
2012-10-06 14:51 ` Aurelien Jarno
2012-09-27 13:24 ` [Qemu-devel] [PATCH v9 06/14] target-mips-ase-dsp: Add arithmetic instructions Jia Liu
2012-10-06 14:51 ` Aurelien Jarno
2012-09-27 13:24 ` [Qemu-devel] [PATCH v9 07/14] target-mips-ase-dsp: Add GPR-based shift instructions Jia Liu
2012-10-06 14:51 ` Aurelien Jarno
2012-09-27 13:24 ` [Qemu-devel] [PATCH v9 08/14] target-mips-ase-dsp: Add multiply instructions Jia Liu
2012-10-06 14:51 ` Aurelien Jarno
2012-09-27 13:24 ` Jia Liu [this message]
2012-10-06 14:51 ` [Qemu-devel] [PATCH v9 09/14] target-mips-ase-dsp: Add bit/manipulation instructions Aurelien Jarno
2012-09-27 13:24 ` [Qemu-devel] [PATCH v9 10/14] target-mips-ase-dsp: Add compare-pick instructions Jia Liu
2012-10-06 14:51 ` Aurelien Jarno
2012-09-27 13:24 ` [Qemu-devel] [PATCH v9 11/14] target-mips-ase-dsp: Add DSP accumulator instructions Jia Liu
2012-10-06 14:51 ` Aurelien Jarno
2012-09-27 13:24 ` [Qemu-devel] [PATCH v9 12/14] target-mips-ase-dsp: Add MIPS DSP processors Jia Liu
2012-10-06 14:51 ` Aurelien Jarno
2012-09-27 13:24 ` [Qemu-devel] [PATCH v9 13/14] target-mips-ase-dsp: Add testcases Jia Liu
2012-10-06 14:51 ` Aurelien Jarno
2012-09-27 13:24 ` [Qemu-devel] [PATCH v9 14/14] target-mips-ase-dsp: Change TODO file Jia Liu
2012-10-06 14:52 ` Aurelien Jarno
2012-10-06 2:33 ` [Qemu-devel] [PATCH v9 00/14] QEMU MIPS ASE DSP support Jia Liu
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