Re: [PATCH v2 13/15] powerpc/85xx: add support for e6500 L1 cache operation

[Scott Wood <scottwood@freescale.com>]

On 04/19/2013 05:47:46 AM, Zhao Chenhui wrote:
> From: Chen-Hui Zhao <chenhui.zhao@freescale.com>
>=20
> The L1 Data Cache of e6500 contains no modified data, no flush
> is required.
>=20
> Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
> Signed-off-by: Li Yang <leoli@freescale.com>
> Signed-off-by: Andy Fleming <afleming@freescale.com>
> ---
>  arch/powerpc/kernel/fsl_booke_cache.S |   11 ++++++++++-
>  1 files changed, 10 insertions(+), 1 deletions(-)
>=20
> diff --git a/arch/powerpc/kernel/fsl_booke_cache.S =20
> b/arch/powerpc/kernel/fsl_booke_cache.S
> index 232c47b..24a52bb 100644
> --- a/arch/powerpc/kernel/fsl_booke_cache.S
> +++ b/arch/powerpc/kernel/fsl_booke_cache.S
> @@ -65,13 +65,22 @@ _GLOBAL(flush_dcache_L1)
>=20
>  	blr
>=20
> +#define PVR_E6500	0x8040
> +
>  /* Flush L1 d-cache, invalidate and disable d-cache and i-cache */
>  _GLOBAL(__flush_disable_L1)
> +/* L1 Data Cache of e6500 contains no modified data, no flush is =20
> required */
> +	mfspr	r3, SPRN_PVR
> +	rlwinm	r4, r3, 16, 0xffff
> +	lis	r5, 0
> +	ori	r5, r5, PVR_E6500@l
> +	cmpw	r4, r5
> +	beq	2f
>  	mflr	r10
>  	bl	flush_dcache_L1	/* Flush L1 d-cache */
>  	mtlr	r10
>=20
> -	msync
> +2:	msync
>  	mfspr	r4, SPRN_L1CSR0	/* Invalidate and disable d-cache */
>  	li	r5, 2
>  	rlwimi	r4, r5, 0, 3

Note that disabling the cache is a core operation, rather than a thread =20
operation.  Is this only called when the second thread is disabled?

-Scott=