[PATCH 1/2] drm/i915: set default value for config->pixel_multiplier

[PATCH 1/2] drm/i915: set default value for config->pixel_multiplier

[Daniel Vetter]

This way we can simplify the code quite a bit.

Also add a WARN in the sdvo code to complain about a bogus value
and kill the readout code in intel_ddi.c that Jesse sneaked in.
HW state readout for the pixel multiplier will work a bit differently
in the end.

v2: Rebase on top of the fdi pixel mutliplier handling fix.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/intel_ddi.c     |  1 -
 drivers/gpu/drm/i915/intel_display.c | 29 ++++++++++-------------------
 drivers/gpu/drm/i915/intel_sdvo.c    |  1 +
 3 files changed, 11 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 486c46b..224ce25 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1279,7 +1279,6 @@ static void intel_ddi_get_config(struct intel_encoder *encoder,
 		flags |= DRM_MODE_FLAG_NVSYNC;
 
 	pipe_config->adjusted_mode.flags |= flags;
-	pipe_config->pixel_multiplier = 1;
 }
 
 static void intel_ddi_destroy(struct drm_encoder *encoder)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 2b6e141..9f772eb 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4006,8 +4006,7 @@ retry:
 	link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
 
 	fdi_dotclock = adjusted_mode->clock;
-	if (pipe_config->pixel_multiplier > 1)
-		fdi_dotclock /= pipe_config->pixel_multiplier;
+	fdi_dotclock /= pipe_config->pixel_multiplier;
 
 	lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
 					   pipe_config->pipe_bpp);
@@ -4461,11 +4460,8 @@ static void vlv_update_pll(struct intel_crtc *crtc)
 	if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
 		DRM_ERROR("DPLL %d failed to lock\n", pipe);
 
-	dpll_md = 0;
-	if (crtc->config.pixel_multiplier > 1) {
-		dpll_md = (crtc->config.pixel_multiplier - 1)
-			<< DPLL_MD_UDI_MULTIPLIER_SHIFT;
-	}
+	dpll_md = (crtc->config.pixel_multiplier - 1)
+		<< DPLL_MD_UDI_MULTIPLIER_SHIFT;
 	I915_WRITE(DPLL_MD(pipe), dpll_md);
 	POSTING_READ(DPLL_MD(pipe));
 
@@ -4499,8 +4495,7 @@ static void i9xx_update_pll(struct intel_crtc *crtc,
 	else
 		dpll |= DPLLB_MODE_DAC_SERIAL;
 
-	if ((crtc->config.pixel_multiplier > 1) &&
-	    (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))) {
+	if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
 		dpll |= (crtc->config.pixel_multiplier - 1)
 			<< SDVO_MULTIPLIER_SHIFT_HIRES;
 	}
@@ -4563,11 +4558,8 @@ static void i9xx_update_pll(struct intel_crtc *crtc,
 	udelay(150);
 
 	if (INTEL_INFO(dev)->gen >= 4) {
-		u32 dpll_md = 0;
-		if (crtc->config.pixel_multiplier > 1) {
-			dpll_md = (crtc->config.pixel_multiplier - 1)
-				<< DPLL_MD_UDI_MULTIPLIER_SHIFT;
-		}
+		u32 dpll_md = (crtc->config.pixel_multiplier - 1)
+			<< DPLL_MD_UDI_MULTIPLIER_SHIFT;
 		I915_WRITE(DPLL_MD(pipe), dpll_md);
 	} else {
 		/* The pixel multiplier can only be updated once the
@@ -5616,10 +5608,8 @@ static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
 	else
 		dpll |= DPLLB_MODE_DAC_SERIAL;
 
-	if (intel_crtc->config.pixel_multiplier > 1) {
-		dpll |= (intel_crtc->config.pixel_multiplier - 1)
-			<< PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
-	}
+	dpll |= (intel_crtc->config.pixel_multiplier - 1)
+		<< PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
 
 	if (is_sdvo)
 		dpll |= DPLL_DVO_HIGH_SPEED;
@@ -7783,8 +7773,9 @@ intel_modeset_pipe_config(struct drm_crtc *crtc,
 		goto fail;
 
 encoder_retry:
-	/* Ensure the port clock default is reset when retrying. */
+	/* Ensure the port clock defaults are reset when retrying. */
 	pipe_config->port_clock = 0;
+	pipe_config->pixel_multiplier = 1;
 
 	/* Pass our mode to the connectors and the CRTC to give them a chance to
 	 * adjust it according to limitations or connector properties, and also
diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
index 7068195..f4588a2 100644
--- a/drivers/gpu/drm/i915/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/intel_sdvo.c
@@ -1219,6 +1219,7 @@ static void intel_sdvo_mode_set(struct intel_encoder *intel_encoder)
 
 	switch (intel_crtc->config.pixel_multiplier) {
 	default:
+		WARN(1, "unknown pixel mutlipler specified\n");
 	case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break;
 	case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break;
 	case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break;
-- 
1.7.11.7

[PATCH 2/2] drm/i915: hw state readout support for pixel_multiplier

[Daniel Vetter]

Incomplete since ilk+ support needs proper pch dpll tracking first.
SDVO get_config parts based on a patch from Jesse Barnes, but fixed up
to actually work.

Cc: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/intel_display.c | 25 +++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_sdvo.c    | 30 +++++++++++++++++++++++++++++-
 2 files changed, 54 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 9f772eb..f126e18 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4965,6 +4965,23 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
 
 	i9xx_get_pfit_config(crtc, pipe_config);
 
+	if (INTEL_INFO(dev)->gen >= 4) {
+		tmp = I915_READ(DPLL_MD(crtc->pipe));
+		pipe_config->pixel_multiplier =
+			((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
+			 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
+	} else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
+		tmp = I915_READ(DPLL(crtc->pipe));
+		pipe_config->pixel_multiplier =
+			((tmp & SDVO_MULTIPLIER_MASK)
+			 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
+	} else {
+		/* Note that on i915G/GM the pixel multiplier is in the sdvo
+		 * port and will be fixed up in the encoder->get_config
+		 * function. */
+		pipe_config->pixel_multiplier = 1;
+	}
+
 	return true;
 }
 
@@ -5828,6 +5845,12 @@ static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
 					  FDI_DP_PORT_WIDTH_SHIFT) + 1;
 
 		ironlake_get_fdi_m_n_config(crtc, pipe_config);
+
+		/* XXX: Can't properly read out the pch dpll pixel multiplier
+		 * since we don't have state tracking for pch clocks yet. */
+		pipe_config->pixel_multiplier = 1;
+	} else {
+		pipe_config->pixel_multiplier = 1;
 	}
 
 	intel_get_pipe_timings(crtc, pipe_config);
@@ -5980,6 +6003,8 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
 	pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
 				   (I915_READ(IPS_CTL) & IPS_ENABLE);
 
+	pipe_config->pixel_multiplier = 1;
+
 	return true;
 }
 
diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
index f4588a2..5c816dd 100644
--- a/drivers/gpu/drm/i915/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/intel_sdvo.c
@@ -1313,9 +1313,13 @@ static bool intel_sdvo_get_hw_state(struct intel_encoder *encoder,
 static void intel_sdvo_get_config(struct intel_encoder *encoder,
 				  struct intel_crtc_config *pipe_config)
 {
+	struct drm_device *dev = encoder->base.dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_sdvo *intel_sdvo = to_intel_sdvo(&encoder->base);
 	struct intel_sdvo_dtd dtd;
-	u32 flags = 0;
+	int encoder_pixel_multiplier = 0;
+	u32 flags = 0, sdvox;
+	u8 val;
 	bool ret;
 
 	ret = intel_sdvo_get_input_timing(intel_sdvo, &dtd);
@@ -1335,6 +1339,30 @@ static void intel_sdvo_get_config(struct intel_encoder *encoder,
 		flags |= DRM_MODE_FLAG_NVSYNC;
 
 	pipe_config->adjusted_mode.flags |= flags;
+
+	if (IS_I915G(dev) || IS_I915GM(dev)) {
+		sdvox = I915_READ(intel_sdvo->sdvo_reg);
+		pipe_config->pixel_multiplier =
+			((sdvox & SDVO_PORT_MULTIPLY_MASK)
+			 >> SDVO_PORT_MULTIPLY_SHIFT) + 1;
+	}
+
+	/* Cross check the port pixel multiplier with the sdvo encoder state. */
+	intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_CLOCK_RATE_MULT, &val, 1);
+	switch (val) {
+	case SDVO_CLOCK_RATE_MULT_1X:
+		encoder_pixel_multiplier = 1;
+		break;
+	case SDVO_CLOCK_RATE_MULT_2X:
+		encoder_pixel_multiplier = 2;
+		break;
+	case SDVO_CLOCK_RATE_MULT_4X:
+		encoder_pixel_multiplier = 4;
+		break;
+	}
+	WARN(encoder_pixel_multiplier != pipe_config->pixel_multiplier,
+	     "SDVO pixel multiplier mismatch, port: %i, encoder: %i\n",
+	     pipe_config->pixel_multiplier, encoder_pixel_multiplier);
 }
 
 static void intel_disable_sdvo(struct intel_encoder *encoder)
-- 
1.7.11.7

Re: [PATCH 2/2] drm/i915: hw state readout support for pixel_multiplier

[Imre Deak]

On Sat, 2013-06-01 at 17:17 +0200, Daniel Vetter wrote:
> Incomplete since ilk+ support needs proper pch dpll tracking first.
> SDVO get_config parts based on a patch from Jesse Barnes, but fixed up
> to actually work.
> 
> Cc: Jesse Barnes <jbarnes@virtuousgeek.org>
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> ---
>  drivers/gpu/drm/i915/intel_display.c | 25 +++++++++++++++++++++++++
>  drivers/gpu/drm/i915/intel_sdvo.c    | 30 +++++++++++++++++++++++++++++-
>  2 files changed, 54 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 9f772eb..f126e18 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -4965,6 +4965,23 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
>  
>  	i9xx_get_pfit_config(crtc, pipe_config);
>  
> +	if (INTEL_INFO(dev)->gen >= 4) {
> +		tmp = I915_READ(DPLL_MD(crtc->pipe));
> +		pipe_config->pixel_multiplier =
> +			((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
> +			 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
> +	} else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
> +		tmp = I915_READ(DPLL(crtc->pipe));
> +		pipe_config->pixel_multiplier =
> +			((tmp & SDVO_MULTIPLIER_MASK)
> +			 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
> +	} else {
> +		/* Note that on i915G/GM the pixel multiplier is in the sdvo
> +		 * port and will be fixed up in the encoder->get_config
> +		 * function. */
> +		pipe_config->pixel_multiplier = 1;
> +	}
> +
>  	return true;
>  }
>  
> @@ -5828,6 +5845,12 @@ static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
>  					  FDI_DP_PORT_WIDTH_SHIFT) + 1;
>  
>  		ironlake_get_fdi_m_n_config(crtc, pipe_config);
> +
> +		/* XXX: Can't properly read out the pch dpll pixel multiplier
> +		 * since we don't have state tracking for pch clocks yet. */
> +		pipe_config->pixel_multiplier = 1;
> +	} else {
> +		pipe_config->pixel_multiplier = 1;
>  	}
>  
>  	intel_get_pipe_timings(crtc, pipe_config);
> @@ -5980,6 +6003,8 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
>  	pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
>  				   (I915_READ(IPS_CTL) & IPS_ENABLE);
>  
> +	pipe_config->pixel_multiplier = 1;
> +
>  	return true;
>  }
>  
> diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
> index f4588a2..5c816dd 100644
> --- a/drivers/gpu/drm/i915/intel_sdvo.c
> +++ b/drivers/gpu/drm/i915/intel_sdvo.c
> @@ -1313,9 +1313,13 @@ static bool intel_sdvo_get_hw_state(struct intel_encoder *encoder,
>  static void intel_sdvo_get_config(struct intel_encoder *encoder,
>  				  struct intel_crtc_config *pipe_config)
>  {
> +	struct drm_device *dev = encoder->base.dev;
> +	struct drm_i915_private *dev_priv = dev->dev_private;
>  	struct intel_sdvo *intel_sdvo = to_intel_sdvo(&encoder->base);
>  	struct intel_sdvo_dtd dtd;
> -	u32 flags = 0;
> +	int encoder_pixel_multiplier = 0;
> +	u32 flags = 0, sdvox;
> +	u8 val;
>  	bool ret;
>  
>  	ret = intel_sdvo_get_input_timing(intel_sdvo, &dtd);
> @@ -1335,6 +1339,30 @@ static void intel_sdvo_get_config(struct intel_encoder *encoder,
>  		flags |= DRM_MODE_FLAG_NVSYNC;
>  
>  	pipe_config->adjusted_mode.flags |= flags;
> +
> +	if (IS_I915G(dev) || IS_I915GM(dev)) {
> +		sdvox = I915_READ(intel_sdvo->sdvo_reg);
> +		pipe_config->pixel_multiplier =
> +			((sdvox & SDVO_PORT_MULTIPLY_MASK)
> +			 >> SDVO_PORT_MULTIPLY_SHIFT) + 1;
> +	}
> +
> +	/* Cross check the port pixel multiplier with the sdvo encoder state. */
> +	intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_CLOCK_RATE_MULT, &val, 1);
> +	switch (val) {
> +	case SDVO_CLOCK_RATE_MULT_1X:
> +		encoder_pixel_multiplier = 1;
> +		break;
> +	case SDVO_CLOCK_RATE_MULT_2X:
> +		encoder_pixel_multiplier = 2;
> +		break;
> +	case SDVO_CLOCK_RATE_MULT_4X:
> +		encoder_pixel_multiplier = 4;
> +		break;
> +	}
> +	WARN(encoder_pixel_multiplier != pipe_config->pixel_multiplier,
> +	     "SDVO pixel multiplier mismatch, port: %i, encoder: %i\n",
> +	     pipe_config->pixel_multiplier, encoder_pixel_multiplier);
>  }

In intel_modeset_check_state() we call first encoder->get_config() and
only afterwards display->get_pipe_config(), so this won't work on
I915G/GM.

Other than that the 2 patches look ok:
Reviewed-by: Imre Deak <imre.deak@intel.com>

Related but not affecting my r-b:
The multiplier can take all values from 1-5, why aren't we handling all?
Should we add the proper check to intel_pipe_config_compare() too?

--Imre

Re: [PATCH 2/2] drm/i915: hw state readout support for pixel_multiplier

[Daniel Vetter]

On Wed, Jun 05, 2013 at 06:01:57PM +0300, Imre Deak wrote:
> On Sat, 2013-06-01 at 17:17 +0200, Daniel Vetter wrote:
> > Incomplete since ilk+ support needs proper pch dpll tracking first.
> > SDVO get_config parts based on a patch from Jesse Barnes, but fixed up
> > to actually work.
> > 
> > Cc: Jesse Barnes <jbarnes@virtuousgeek.org>
> > Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> > ---
> >  drivers/gpu/drm/i915/intel_display.c | 25 +++++++++++++++++++++++++
> >  drivers/gpu/drm/i915/intel_sdvo.c    | 30 +++++++++++++++++++++++++++++-
> >  2 files changed, 54 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index 9f772eb..f126e18 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -4965,6 +4965,23 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
> >  
> >  	i9xx_get_pfit_config(crtc, pipe_config);
> >  
> > +	if (INTEL_INFO(dev)->gen >= 4) {
> > +		tmp = I915_READ(DPLL_MD(crtc->pipe));
> > +		pipe_config->pixel_multiplier =
> > +			((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
> > +			 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
> > +	} else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
> > +		tmp = I915_READ(DPLL(crtc->pipe));
> > +		pipe_config->pixel_multiplier =
> > +			((tmp & SDVO_MULTIPLIER_MASK)
> > +			 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
> > +	} else {
> > +		/* Note that on i915G/GM the pixel multiplier is in the sdvo
> > +		 * port and will be fixed up in the encoder->get_config
> > +		 * function. */
> > +		pipe_config->pixel_multiplier = 1;
> > +	}
> > +
> >  	return true;
> >  }
> >  
> > @@ -5828,6 +5845,12 @@ static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
> >  					  FDI_DP_PORT_WIDTH_SHIFT) + 1;
> >  
> >  		ironlake_get_fdi_m_n_config(crtc, pipe_config);
> > +
> > +		/* XXX: Can't properly read out the pch dpll pixel multiplier
> > +		 * since we don't have state tracking for pch clocks yet. */
> > +		pipe_config->pixel_multiplier = 1;
> > +	} else {
> > +		pipe_config->pixel_multiplier = 1;
> >  	}
> >  
> >  	intel_get_pipe_timings(crtc, pipe_config);
> > @@ -5980,6 +6003,8 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
> >  	pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
> >  				   (I915_READ(IPS_CTL) & IPS_ENABLE);
> >  
> > +	pipe_config->pixel_multiplier = 1;
> > +
> >  	return true;
> >  }
> >  
> > diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
> > index f4588a2..5c816dd 100644
> > --- a/drivers/gpu/drm/i915/intel_sdvo.c
> > +++ b/drivers/gpu/drm/i915/intel_sdvo.c
> > @@ -1313,9 +1313,13 @@ static bool intel_sdvo_get_hw_state(struct intel_encoder *encoder,
> >  static void intel_sdvo_get_config(struct intel_encoder *encoder,
> >  				  struct intel_crtc_config *pipe_config)
> >  {
> > +	struct drm_device *dev = encoder->base.dev;
> > +	struct drm_i915_private *dev_priv = dev->dev_private;
> >  	struct intel_sdvo *intel_sdvo = to_intel_sdvo(&encoder->base);
> >  	struct intel_sdvo_dtd dtd;
> > -	u32 flags = 0;
> > +	int encoder_pixel_multiplier = 0;
> > +	u32 flags = 0, sdvox;
> > +	u8 val;
> >  	bool ret;
> >  
> >  	ret = intel_sdvo_get_input_timing(intel_sdvo, &dtd);
> > @@ -1335,6 +1339,30 @@ static void intel_sdvo_get_config(struct intel_encoder *encoder,
> >  		flags |= DRM_MODE_FLAG_NVSYNC;
> >  
> >  	pipe_config->adjusted_mode.flags |= flags;
> > +
> > +	if (IS_I915G(dev) || IS_I915GM(dev)) {
> > +		sdvox = I915_READ(intel_sdvo->sdvo_reg);
> > +		pipe_config->pixel_multiplier =
> > +			((sdvox & SDVO_PORT_MULTIPLY_MASK)
> > +			 >> SDVO_PORT_MULTIPLY_SHIFT) + 1;
> > +	}
> > +
> > +	/* Cross check the port pixel multiplier with the sdvo encoder state. */
> > +	intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_CLOCK_RATE_MULT, &val, 1);
> > +	switch (val) {
> > +	case SDVO_CLOCK_RATE_MULT_1X:
> > +		encoder_pixel_multiplier = 1;
> > +		break;
> > +	case SDVO_CLOCK_RATE_MULT_2X:
> > +		encoder_pixel_multiplier = 2;
> > +		break;
> > +	case SDVO_CLOCK_RATE_MULT_4X:
> > +		encoder_pixel_multiplier = 4;
> > +		break;
> > +	}
> > +	WARN(encoder_pixel_multiplier != pipe_config->pixel_multiplier,
> > +	     "SDVO pixel multiplier mismatch, port: %i, encoder: %i\n",
> > +	     pipe_config->pixel_multiplier, encoder_pixel_multiplier);
> >  }
> 
> In intel_modeset_check_state() we call first encoder->get_config() and
> only afterwards display->get_pipe_config(), so this won't work on
> I915G/GM.

Meh, I've forgotten about this. In setup_hw_state the order is the correct
one, but the check_state stuff is wrong. I'll do what I've asked Jesse to
do and move that encoder->get_config call into the crtc_get_config
functions so that we always have the same (hopefully right ordering).

> Other than that the 2 patches look ok:
> Reviewed-by: Imre Deak <imre.deak@intel.com>

Thanks for the review. I'll merge the first patch right away, imo it's a
nice stand-alone cleanup.

> Related but not affecting my r-b:
> The multiplier can take all values from 1-5, why aren't we handling all?
> Should we add the proper check to intel_pipe_config_compare() too?

intel_sdvo_get_pixel_multiplier in intel_sdvo.c only sets these 3 cases,
and iirc the sdvo spec mentions that those are the only ones. HDMI otoh
can take odd multipliers, too. I guess that's why the dpll_md (and other
fields) can take those values. But currently we don't support modes with
multiplied pixels.

Yours, Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

[PATCH] drm/i915: hw state readout support for pixel_multiplier

[Daniel Vetter]

Incomplete since ilk+ support needs proper pch dpll tracking first.
SDVO get_config parts based on a patch from Jesse Barnes, but fixed up
to actually work.

v2: Make sure that we call encoder->get_config _after_ we
get_pipe_config to be consistent in both setup_hw_state and the
modeset state checker. Otherwise the clever trick with handling the
pixel mutliplier on i915G/GM where the encoder overrides the default
value of 1 from the crtc get_pipe_config function doesn't work.
Spotted by Imre Deak.

v3: Actually cross-check the pixel mutliplier (but not on pch split
platforms for now). Now actually also tested on a i915G with a sdvo
encoder plugged in.

Cc: <imre.deak@intel.com>
Cc: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/intel_display.c | 38 ++++++++++++++++++++++++++++++++++--
 drivers/gpu/drm/i915/intel_sdvo.c    | 30 +++++++++++++++++++++++++++-
 2 files changed, 65 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 40d047e..a1a81b4 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4962,6 +4962,23 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
 
 	i9xx_get_pfit_config(crtc, pipe_config);
 
+	if (INTEL_INFO(dev)->gen >= 4) {
+		tmp = I915_READ(DPLL_MD(crtc->pipe));
+		pipe_config->pixel_multiplier =
+			((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
+			 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
+	} else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
+		tmp = I915_READ(DPLL(crtc->pipe));
+		pipe_config->pixel_multiplier =
+			((tmp & SDVO_MULTIPLIER_MASK)
+			 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
+	} else {
+		/* Note that on i915G/GM the pixel multiplier is in the sdvo
+		 * port and will be fixed up in the encoder->get_config
+		 * function. */
+		pipe_config->pixel_multiplier = 1;
+	}
+
 	return true;
 }
 
@@ -5825,6 +5842,12 @@ static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
 					  FDI_DP_PORT_WIDTH_SHIFT) + 1;
 
 		ironlake_get_fdi_m_n_config(crtc, pipe_config);
+
+		/* XXX: Can't properly read out the pch dpll pixel multiplier
+		 * since we don't have state tracking for pch clocks yet. */
+		pipe_config->pixel_multiplier = 1;
+	} else {
+		pipe_config->pixel_multiplier = 1;
 	}
 
 	intel_get_pipe_timings(crtc, pipe_config);
@@ -5959,6 +5982,8 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
 	pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
 				   (I915_READ(IPS_CTL) & IPS_ENABLE);
 
+	pipe_config->pixel_multiplier = 1;
+
 	return true;
 }
 
@@ -8048,6 +8073,9 @@ intel_pipe_config_compare(struct drm_device *dev,
 	PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
 	PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
 
+	if (!HAS_PCH_SPLIT(dev))
+		PIPE_CONF_CHECK_I(pixel_multiplier);
+
 	PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
 			      DRM_MODE_FLAG_INTERLACE);
 
@@ -8169,9 +8197,8 @@ intel_modeset_check_state(struct drm_device *dev)
 			enabled = true;
 			if (encoder->connectors_active)
 				active = true;
-			if (encoder->get_config)
-				encoder->get_config(encoder, &pipe_config);
 		}
+
 		WARN(active != crtc->active,
 		     "crtc's computed active state doesn't match tracked active state "
 		     "(expected %i, found %i)\n", active, crtc->active);
@@ -8181,6 +8208,13 @@ intel_modeset_check_state(struct drm_device *dev)
 
 		active = dev_priv->display.get_pipe_config(crtc,
 							   &pipe_config);
+		list_for_each_entry(encoder, &dev->mode_config.encoder_list,
+				    base.head) {
+			if (encoder->base.crtc != &crtc->base)
+				continue;
+			if (encoder->get_config)
+				encoder->get_config(encoder, &pipe_config);
+		}
 
 		/* hw state is inconsistent with the pipe A quirk */
 		if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
index 820f1ae..d4560ad 100644
--- a/drivers/gpu/drm/i915/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/intel_sdvo.c
@@ -1313,9 +1313,13 @@ static bool intel_sdvo_get_hw_state(struct intel_encoder *encoder,
 static void intel_sdvo_get_config(struct intel_encoder *encoder,
 				  struct intel_crtc_config *pipe_config)
 {
+	struct drm_device *dev = encoder->base.dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_sdvo *intel_sdvo = to_intel_sdvo(&encoder->base);
 	struct intel_sdvo_dtd dtd;
-	u32 flags = 0;
+	int encoder_pixel_multiplier = 0;
+	u32 flags = 0, sdvox;
+	u8 val;
 	bool ret;
 
 	ret = intel_sdvo_get_input_timing(intel_sdvo, &dtd);
@@ -1335,6 +1339,30 @@ static void intel_sdvo_get_config(struct intel_encoder *encoder,
 		flags |= DRM_MODE_FLAG_NVSYNC;
 
 	pipe_config->adjusted_mode.flags |= flags;
+
+	if (IS_I915G(dev) || IS_I915GM(dev)) {
+		sdvox = I915_READ(intel_sdvo->sdvo_reg);
+		pipe_config->pixel_multiplier =
+			((sdvox & SDVO_PORT_MULTIPLY_MASK)
+			 >> SDVO_PORT_MULTIPLY_SHIFT) + 1;
+	}
+
+	/* Cross check the port pixel multiplier with the sdvo encoder state. */
+	intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_CLOCK_RATE_MULT, &val, 1);
+	switch (val) {
+	case SDVO_CLOCK_RATE_MULT_1X:
+		encoder_pixel_multiplier = 1;
+		break;
+	case SDVO_CLOCK_RATE_MULT_2X:
+		encoder_pixel_multiplier = 2;
+		break;
+	case SDVO_CLOCK_RATE_MULT_4X:
+		encoder_pixel_multiplier = 4;
+		break;
+	}
+	WARN(encoder_pixel_multiplier != pipe_config->pixel_multiplier,
+	     "SDVO pixel multiplier mismatch, port: %i, encoder: %i\n",
+	     pipe_config->pixel_multiplier, encoder_pixel_multiplier);
 }
 
 static void intel_disable_sdvo(struct intel_encoder *encoder)
-- 
1.7.11.7

Re: [PATCH] drm/i915: hw state readout support for pixel_multiplier

[Imre Deak]

On Thu, 2013-06-06 at 12:45 +0200, Daniel Vetter wrote:
> Incomplete since ilk+ support needs proper pch dpll tracking first.
> SDVO get_config parts based on a patch from Jesse Barnes, but fixed up
> to actually work.
> 
> v2: Make sure that we call encoder->get_config _after_ we
> get_pipe_config to be consistent in both setup_hw_state and the
> modeset state checker. Otherwise the clever trick with handling the
> pixel mutliplier on i915G/GM where the encoder overrides the default
> value of 1 from the crtc get_pipe_config function doesn't work.
> Spotted by Imre Deak.
> 
> v3: Actually cross-check the pixel mutliplier (but not on pch split
> platforms for now). Now actually also tested on a i915G with a sdvo
> encoder plugged in.
> 
> Cc: <imre.deak@intel.com>
> Cc: Jesse Barnes <jbarnes@virtuousgeek.org>
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

Looks ok,
Reviewed-by: Imre Deak <imre.deak@intel.com>

Re: [PATCH] drm/i915: hw state readout support for pixel_multiplier

[Daniel Vetter]

On Thu, Jun 06, 2013 at 02:50:15PM +0300, Imre Deak wrote:
> On Thu, 2013-06-06 at 12:45 +0200, Daniel Vetter wrote:
> > Incomplete since ilk+ support needs proper pch dpll tracking first.
> > SDVO get_config parts based on a patch from Jesse Barnes, but fixed up
> > to actually work.
> > 
> > v2: Make sure that we call encoder->get_config _after_ we
> > get_pipe_config to be consistent in both setup_hw_state and the
> > modeset state checker. Otherwise the clever trick with handling the
> > pixel mutliplier on i915G/GM where the encoder overrides the default
> > value of 1 from the crtc get_pipe_config function doesn't work.
> > Spotted by Imre Deak.
> > 
> > v3: Actually cross-check the pixel mutliplier (but not on pch split
> > platforms for now). Now actually also tested on a i915G with a sdvo
> > encoder plugged in.
> > 
> > Cc: <imre.deak@intel.com>
> > Cc: Jesse Barnes <jbarnes@virtuousgeek.org>
> > Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> 
> Looks ok,
> Reviewed-by: Imre Deak <imre.deak@intel.com>

Queued for -next, thanks for the review.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch