From: Tom Musta <tommusta@gmail.com>
To: qemu-devel@nongnu.org, tommusta@gmail.com
Cc: qemu-ppc@nongnu.org
Subject: [Qemu-devel] [PATCH V3 15/19] Add VSX xmax/xmin Instructions
Date: Fri, 1 Nov 2013 08:35:51 -0500 [thread overview]
Message-ID: <1383312955-2607-16-git-send-email-tommusta@gmail.com> (raw)
In-Reply-To: <1383312955-2607-1-git-send-email-tommusta@gmail.com>
This patch adds the VSX floating point maximum and minimum
instructions:
- xsmaxdp, xvmaxdp, xvmaxsp
- xsmindp, xvmindp, xvminsp
Because of the Power ISA definitions of maximum and minimum
on various boundary cases, the standard softfloat comparison
routines (e.g. float64_lt) do not work as well as one might
think. Therefore specific routines for comparing 64 and 32
bit floating point numbers are implemented in the PowerPC
helper code.
V2: consolidated into a single macro, using the softfloat
float*_max/float*_min routines.
Signed-off-by: Tom Musta <tommusta@gmail.com>
---
target-ppc/fpu_helper.c | 50 +++++++++++++++++++++++++++++++++++++++++++++++
target-ppc/helper.h | 6 +++++
target-ppc/translate.c | 12 +++++++++++
3 files changed, 68 insertions(+), 0 deletions(-)
diff --git a/target-ppc/fpu_helper.c b/target-ppc/fpu_helper.c
index eb5d878..b90541c 100644
--- a/target-ppc/fpu_helper.c
+++ b/target-ppc/fpu_helper.c
@@ -2288,3 +2288,53 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \
VSX_SCALAR_CMP(xscmpodp, 1)
VSX_SCALAR_CMP(xscmpudp, 0)
+
+#define float64_snan_to_qnan(x) ((x) | 0x0008000000000000ul)
+#define float32_snan_to_qnan(x) ((x) | 0x00400000)
+
+/* VSX_MAX_MIN - VSX floating point maximum/minimum
+ * name - instruction mnemonic
+ * op - operation (max or min)
+ * nels - number of elements (1, 2 or 4)
+ * tp - type (float32 or float64)
+ * fld - vsr_t field (f32 or f64)
+ */
+#define VSX_MAX_MIN(name, op, nels, tp, fld) \
+void helper_##name(CPUPPCState *env, uint32_t opcode) \
+{ \
+ ppc_vsr_t xt, xa, xb; \
+ int i; \
+ \
+ getVSR(xA(opcode), &xa, env); \
+ getVSR(xB(opcode), &xb, env); \
+ getVSR(xT(opcode), &xt, env); \
+ \
+ for (i = 0; i < nels; i++) { \
+ if (unlikely(tp##_is_any_nan(xa.fld[i]) || \
+ tp##_is_any_nan(xb.fld[i]))) { \
+ if (tp##_is_signaling_nan(xa.fld[i])) { \
+ xt.fld[i] = tp##_snan_to_qnan(xa.fld[i]); \
+ fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0); \
+ } else if (tp##_is_signaling_nan(xb.fld[i])) { \
+ xt.fld[i] = tp##_snan_to_qnan(xb.fld[i]); \
+ fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0); \
+ } else if (tp##_is_quiet_nan(xb.fld[i])) { \
+ xt.fld[i] = xa.fld[i]; \
+ } else { /* XA is QNaN */ \
+ xt.fld[i] = xb.fld[i]; \
+ } \
+ } else { \
+ xt.fld[i] = tp##_##op(xa.fld[i], xb.fld[i], &env->fp_status); \
+ } \
+ } \
+ \
+ putVSR(xT(opcode), &xt, env); \
+ helper_float_check_status(env); \
+}
+
+VSX_MAX_MIN(xsmaxdp, max, 1, float64, f64)
+VSX_MAX_MIN(xvmaxdp, max, 2, float64, f64)
+VSX_MAX_MIN(xvmaxsp, max, 4, float32, f32)
+VSX_MAX_MIN(xsmindp, min, 1, float64, f64)
+VSX_MAX_MIN(xvmindp, min, 2, float64, f64)
+VSX_MAX_MIN(xvminsp, min, 4, float32, f32)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index cd72388..4a65d39 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -270,6 +270,8 @@ DEF_HELPER_2(xsnmsubadp, void, env, i32)
DEF_HELPER_2(xsnmsubmdp, void, env, i32)
DEF_HELPER_2(xscmpodp, void, env, i32)
DEF_HELPER_2(xscmpudp, void, env, i32)
+DEF_HELPER_2(xsmaxdp, void, env, i32)
+DEF_HELPER_2(xsmindp, void, env, i32)
DEF_HELPER_2(xvadddp, void, env, i32)
DEF_HELPER_2(xvsubdp, void, env, i32)
@@ -288,6 +290,8 @@ DEF_HELPER_2(xvnmaddadp, void, env, i32)
DEF_HELPER_2(xvnmaddmdp, void, env, i32)
DEF_HELPER_2(xvnmsubadp, void, env, i32)
DEF_HELPER_2(xvnmsubmdp, void, env, i32)
+DEF_HELPER_2(xvmaxdp, void, env, i32)
+DEF_HELPER_2(xvmindp, void, env, i32)
DEF_HELPER_2(xvaddsp, void, env, i32)
DEF_HELPER_2(xvsubsp, void, env, i32)
@@ -306,6 +310,8 @@ DEF_HELPER_2(xvnmaddasp, void, env, i32)
DEF_HELPER_2(xvnmaddmsp, void, env, i32)
DEF_HELPER_2(xvnmsubasp, void, env, i32)
DEF_HELPER_2(xvnmsubmsp, void, env, i32)
+DEF_HELPER_2(xvmaxsp, void, env, i32)
+DEF_HELPER_2(xvminsp, void, env, i32)
DEF_HELPER_2(efscfsi, i32, env, i32)
DEF_HELPER_2(efscfui, i32, env, i32)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index a2a4e2d..10c238a 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -7314,6 +7314,8 @@ GEN_VSX_HELPER_2(xsnmsubadp, 0x04, 0x16, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xsnmsubmdp, 0x04, 0x17, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xscmpodp, 0x0C, 0x05, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xscmpudp, 0x0C, 0x04, 0, PPC2_VSX)
+GEN_VSX_HELPER_2(xsmaxdp, 0x00, 0x14, 0, PPC2_VSX)
+GEN_VSX_HELPER_2(xsmindp, 0x00, 0x15, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xvadddp, 0x00, 0x0C, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xvsubdp, 0x00, 0x0D, 0, PPC2_VSX)
@@ -7332,6 +7334,8 @@ GEN_VSX_HELPER_2(xvnmaddadp, 0x04, 0x1C, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xvnmaddmdp, 0x04, 0x1D, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xvnmsubadp, 0x04, 0x1E, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xvnmsubmdp, 0x04, 0x1F, 0, PPC2_VSX)
+GEN_VSX_HELPER_2(xvmaxdp, 0x00, 0x1C, 0, PPC2_VSX)
+GEN_VSX_HELPER_2(xvmindp, 0x00, 0x1D, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xvaddsp, 0x00, 0x08, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xvsubsp, 0x00, 0x09, 0, PPC2_VSX)
@@ -7350,6 +7354,8 @@ GEN_VSX_HELPER_2(xvnmaddasp, 0x04, 0x18, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xvnmaddmsp, 0x04, 0x19, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xvnmsubasp, 0x04, 0x1A, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xvnmsubmsp, 0x04, 0x1B, 0, PPC2_VSX)
+GEN_VSX_HELPER_2(xvmaxsp, 0x00, 0x18, 0, PPC2_VSX)
+GEN_VSX_HELPER_2(xvminsp, 0x00, 0x19, 0, PPC2_VSX)
#define VSX_LOGICAL(name, tcg_op) \
static void glue(gen_, name)(DisasContext * ctx) \
@@ -10052,6 +10058,8 @@ GEN_XX3FORM(xsnmsubadp, 0x04, 0x16, PPC2_VSX),
GEN_XX3FORM(xsnmsubmdp, 0x04, 0x17, PPC2_VSX),
GEN_XX2FORM(xscmpodp, 0x0C, 0x05, PPC2_VSX),
GEN_XX2FORM(xscmpudp, 0x0C, 0x04, PPC2_VSX),
+GEN_XX3FORM(xsmaxdp, 0x00, 0x14, PPC2_VSX),
+GEN_XX3FORM(xsmindp, 0x00, 0x15, PPC2_VSX),
GEN_XX3FORM(xvadddp, 0x00, 0x0C, PPC2_VSX),
GEN_XX3FORM(xvsubdp, 0x00, 0x0D, PPC2_VSX),
@@ -10070,6 +10078,8 @@ GEN_XX3FORM(xvnmaddadp, 0x04, 0x1C, PPC2_VSX),
GEN_XX3FORM(xvnmaddmdp, 0x04, 0x1D, PPC2_VSX),
GEN_XX3FORM(xvnmsubadp, 0x04, 0x1E, PPC2_VSX),
GEN_XX3FORM(xvnmsubmdp, 0x04, 0x1F, PPC2_VSX),
+GEN_XX3FORM(xvmaxdp, 0x00, 0x1C, PPC2_VSX),
+GEN_XX3FORM(xvmindp, 0x00, 0x1D, PPC2_VSX),
GEN_XX3FORM(xvaddsp, 0x00, 0x08, PPC2_VSX),
GEN_XX3FORM(xvsubsp, 0x00, 0x09, PPC2_VSX),
@@ -10088,6 +10098,8 @@ GEN_XX3FORM(xvnmaddasp, 0x04, 0x18, PPC2_VSX),
GEN_XX3FORM(xvnmaddmsp, 0x04, 0x19, PPC2_VSX),
GEN_XX3FORM(xvnmsubasp, 0x04, 0x1A, PPC2_VSX),
GEN_XX3FORM(xvnmsubmsp, 0x04, 0x1B, PPC2_VSX),
+GEN_XX3FORM(xvmaxsp, 0x00, 0x18, PPC2_VSX),
+GEN_XX3FORM(xvminsp, 0x00, 0x19, PPC2_VSX),
#undef VSX_LOGICAL
#define VSX_LOGICAL(name, opc2, opc3, fl2) \
--
1.7.1
next prev parent reply other threads:[~2013-11-01 13:36 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-11-01 13:35 [Qemu-devel] [PATCH V3 00/19] PowerPC VSX Stage 3 Tom Musta
2013-11-01 13:35 ` [Qemu-devel] [PATCH V3 01/19] Fix float64_to_uint64 Tom Musta
2013-12-17 13:42 ` [Qemu-devel] [Qemu-ppc] " Alexander Graf
2013-12-17 13:52 ` Peter Maydell
2013-12-17 14:03 ` Alexander Graf
2013-12-18 14:21 ` Tom Musta
2013-12-18 14:35 ` Peter Maydell
2013-12-18 15:31 ` Tom Musta
2013-12-18 15:52 ` Peter Maydell
2013-12-18 20:43 ` Tom Musta
2013-12-18 20:44 ` Tom Musta
2013-11-01 13:35 ` [Qemu-devel] [PATCH V3 02/19] Add float32_to_uint64() Tom Musta
2013-11-01 13:35 ` [Qemu-devel] [PATCH V3 03/19] Add set_fprf Argument to fload_invalid_op_excp() Tom Musta
2013-11-01 13:35 ` [Qemu-devel] [PATCH V3 04/19] General Support for VSX Helpers Tom Musta
2013-11-01 13:35 ` [Qemu-devel] [PATCH V3 05/19] Add VSX ISA2.06 xadd/xsub Instructions Tom Musta
2013-11-01 13:35 ` [Qemu-devel] [PATCH V3 06/19] Add VSX ISA2.06 xmul Instructions Tom Musta
2013-11-01 13:35 ` [Qemu-devel] [PATCH V3 07/19] Add VSX ISA2.06 xdiv Instructions Tom Musta
2013-11-01 13:35 ` [Qemu-devel] [PATCH V3 08/19] Add VSX ISA2.06 xre Instructions Tom Musta
2013-11-01 13:35 ` [Qemu-devel] [PATCH V3 09/19] Add VSX ISA2.06 xsqrt Instructions Tom Musta
2013-11-01 13:35 ` [Qemu-devel] [PATCH V3 10/19] Add VSX ISA2.06 xrsqrte Instructions Tom Musta
2013-11-01 13:35 ` [Qemu-devel] [PATCH V3 11/19] Add VSX ISA2.06 xtdiv Instructions Tom Musta
2013-11-01 13:35 ` [Qemu-devel] [PATCH V3 12/19] Add VSX ISA2.06 xtsqrt Instructions Tom Musta
2013-11-01 13:35 ` [Qemu-devel] [PATCH V3 13/19] Add VSX ISA2.06 Multiply Add Instructions Tom Musta
2013-11-01 13:35 ` [Qemu-devel] [PATCH V3 14/19] Add VSX xscmp*dp Instructions Tom Musta
2013-11-01 13:35 ` Tom Musta [this message]
2013-11-01 13:35 ` [Qemu-devel] [PATCH V3 16/19] Add VSX Vector Compare Instructions Tom Musta
2013-11-01 13:35 ` [Qemu-devel] [PATCH V3 17/19] Add VSX Floating Point to Floating Point Conversion Instructions Tom Musta
2013-11-01 13:35 ` [Qemu-devel] [PATCH V3 18/19] Add VSX ISA2.06 Integer " Tom Musta
2013-11-01 13:35 ` [Qemu-devel] [PATCH V3 19/19] Add VSX Rounding Instructions Tom Musta
2013-12-03 16:16 ` [Qemu-devel] [PATCH V3 00/19] PowerPC VSX Stage 3 Tom Musta
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