From: Tom Musta <tommusta@gmail.com>
To: qemu-devel@nongnu.org, tommusta@gmail.com
Cc: qemu-ppc@nongnu.org
Subject: [Qemu-devel] [PATCH V3 16/19] Add VSX Vector Compare Instructions
Date: Fri, 1 Nov 2013 08:35:52 -0500 [thread overview]
Message-ID: <1383312955-2607-17-git-send-email-tommusta@gmail.com> (raw)
In-Reply-To: <1383312955-2607-1-git-send-email-tommusta@gmail.com>
This patch adds the VSX floating point compare vector instructions:
- xvcmpeqdp[.], xvcmpgedp[.], xvcmpgtdp[.]
- xvcmpeqsp[.], xvcmpgesp[.], xvcmpgtsp[.]
Signed-off-by: Tom Musta <tommusta@gmail.com>
---
target-ppc/fpu_helper.c | 57 +++++++++++++++++++++++++++++++++++++++++++++++
target-ppc/helper.h | 6 +++++
target-ppc/translate.c | 23 +++++++++++++++++++
3 files changed, 86 insertions(+), 0 deletions(-)
diff --git a/target-ppc/fpu_helper.c b/target-ppc/fpu_helper.c
index b90541c..ec1df4f 100644
--- a/target-ppc/fpu_helper.c
+++ b/target-ppc/fpu_helper.c
@@ -2338,3 +2338,60 @@ VSX_MAX_MIN(xvmaxsp, max, 4, float32, f32)
VSX_MAX_MIN(xsmindp, min, 1, float64, f64)
VSX_MAX_MIN(xvmindp, min, 2, float64, f64)
VSX_MAX_MIN(xvminsp, min, 4, float32, f32)
+
+/* VSX_CMP - VSX floating point compare
+ * op - instruction mnemonic
+ * nels - number of elements (1, 2 or 4)
+ * tp - type (float32 or float64)
+ * fld - vsr_t field (f32 or f64)
+ * cmp - comparison operation
+ * svxvc - set VXVC bit
+ */
+#define VSX_CMP(op, nels, tp, fld, cmp, svxvc) \
+void helper_##op(CPUPPCState *env, uint32_t opcode) \
+{ \
+ ppc_vsr_t xt, xa, xb; \
+ int i; \
+ int all_true = 1; \
+ int all_false = 1; \
+ \
+ getVSR(xA(opcode), &xa, env); \
+ getVSR(xB(opcode), &xb, env); \
+ getVSR(xT(opcode), &xt, env); \
+ \
+ for (i = 0; i < nels; i++) { \
+ if (unlikely(tp##_is_any_nan(xa.fld[i]) || \
+ tp##_is_any_nan(xb.fld[i]))) { \
+ if (tp##_is_signaling_nan(xa.fld[i]) || \
+ tp##_is_signaling_nan(xb.fld[i])) { \
+ fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0); \
+ } \
+ if (svxvc) { \
+ fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXVC, 0); \
+ } \
+ xt.fld[i] = 0; \
+ all_true = 0; \
+ } else { \
+ if (tp##_##cmp(xb.fld[i], xa.fld[i], &env->fp_status) == 1) { \
+ xt.fld[i] = -1; \
+ all_false = 0; \
+ } else { \
+ xt.fld[i] = 0; \
+ all_true = 0; \
+ } \
+ } \
+ } \
+ \
+ putVSR(xT(opcode), &xt, env); \
+ if ((opcode >> (31-21)) & 1) { \
+ env->crf[6] = (all_true ? 0x8 : 0) | (all_false ? 0x2 : 0); \
+ } \
+ helper_float_check_status(env); \
+ }
+
+VSX_CMP(xvcmpeqdp, 2, float64, f64, eq, 0)
+VSX_CMP(xvcmpgedp, 2, float64, f64, le, 1)
+VSX_CMP(xvcmpgtdp, 2, float64, f64, lt, 1)
+VSX_CMP(xvcmpeqsp, 4, float32, f32, eq, 0)
+VSX_CMP(xvcmpgesp, 4, float32, f32, le, 1)
+VSX_CMP(xvcmpgtsp, 4, float32, f32, lt, 1)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 4a65d39..35389c5 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -292,6 +292,9 @@ DEF_HELPER_2(xvnmsubadp, void, env, i32)
DEF_HELPER_2(xvnmsubmdp, void, env, i32)
DEF_HELPER_2(xvmaxdp, void, env, i32)
DEF_HELPER_2(xvmindp, void, env, i32)
+DEF_HELPER_2(xvcmpeqdp, void, env, i32)
+DEF_HELPER_2(xvcmpgedp, void, env, i32)
+DEF_HELPER_2(xvcmpgtdp, void, env, i32)
DEF_HELPER_2(xvaddsp, void, env, i32)
DEF_HELPER_2(xvsubsp, void, env, i32)
@@ -312,6 +315,9 @@ DEF_HELPER_2(xvnmsubasp, void, env, i32)
DEF_HELPER_2(xvnmsubmsp, void, env, i32)
DEF_HELPER_2(xvmaxsp, void, env, i32)
DEF_HELPER_2(xvminsp, void, env, i32)
+DEF_HELPER_2(xvcmpeqsp, void, env, i32)
+DEF_HELPER_2(xvcmpgesp, void, env, i32)
+DEF_HELPER_2(xvcmpgtsp, void, env, i32)
DEF_HELPER_2(efscfsi, i32, env, i32)
DEF_HELPER_2(efscfui, i32, env, i32)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 10c238a..377a482 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -7336,6 +7336,9 @@ GEN_VSX_HELPER_2(xvnmsubadp, 0x04, 0x1E, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xvnmsubmdp, 0x04, 0x1F, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xvmaxdp, 0x00, 0x1C, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xvmindp, 0x00, 0x1D, 0, PPC2_VSX)
+GEN_VSX_HELPER_2(xvcmpeqdp, 0x0C, 0x0C, 0, PPC2_VSX)
+GEN_VSX_HELPER_2(xvcmpgtdp, 0x0C, 0x0D, 0, PPC2_VSX)
+GEN_VSX_HELPER_2(xvcmpgedp, 0x0C, 0x0E, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xvaddsp, 0x00, 0x08, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xvsubsp, 0x00, 0x09, 0, PPC2_VSX)
@@ -7356,6 +7359,9 @@ GEN_VSX_HELPER_2(xvnmsubasp, 0x04, 0x1A, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xvnmsubmsp, 0x04, 0x1B, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xvmaxsp, 0x00, 0x18, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xvminsp, 0x00, 0x19, 0, PPC2_VSX)
+GEN_VSX_HELPER_2(xvcmpeqsp, 0x0C, 0x08, 0, PPC2_VSX)
+GEN_VSX_HELPER_2(xvcmpgtsp, 0x0C, 0x09, 0, PPC2_VSX)
+GEN_VSX_HELPER_2(xvcmpgesp, 0x0C, 0x0A, 0, PPC2_VSX)
#define VSX_LOGICAL(name, tcg_op) \
static void glue(gen_, name)(DisasContext * ctx) \
@@ -10006,6 +10012,17 @@ GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2), \
GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 2, opc3, 0, PPC_NONE, fl2), \
GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 3, opc3, 0, PPC_NONE, fl2)
+#undef GEN_XX3_RC_FORM
+#define GEN_XX3_RC_FORM(name, opc2, opc3, fl2) \
+GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x00, opc3 | 0x00, 0, PPC_NONE, fl2), \
+GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x01, opc3 | 0x00, 0, PPC_NONE, fl2), \
+GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x02, opc3 | 0x00, 0, PPC_NONE, fl2), \
+GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x03, opc3 | 0x00, 0, PPC_NONE, fl2), \
+GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x00, opc3 | 0x10, 0, PPC_NONE, fl2), \
+GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x01, opc3 | 0x10, 0, PPC_NONE, fl2), \
+GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x02, opc3 | 0x10, 0, PPC_NONE, fl2), \
+GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x03, opc3 | 0x10, 0, PPC_NONE, fl2)
+
#undef GEN_XX3FORM_DM
#define GEN_XX3FORM_DM(name, opc2, opc3) \
GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
@@ -10080,6 +10097,9 @@ GEN_XX3FORM(xvnmsubadp, 0x04, 0x1E, PPC2_VSX),
GEN_XX3FORM(xvnmsubmdp, 0x04, 0x1F, PPC2_VSX),
GEN_XX3FORM(xvmaxdp, 0x00, 0x1C, PPC2_VSX),
GEN_XX3FORM(xvmindp, 0x00, 0x1D, PPC2_VSX),
+GEN_XX3_RC_FORM(xvcmpeqdp, 0x0C, 0x0C, PPC2_VSX),
+GEN_XX3_RC_FORM(xvcmpgtdp, 0x0C, 0x0D, PPC2_VSX),
+GEN_XX3_RC_FORM(xvcmpgedp, 0x0C, 0x0E, PPC2_VSX),
GEN_XX3FORM(xvaddsp, 0x00, 0x08, PPC2_VSX),
GEN_XX3FORM(xvsubsp, 0x00, 0x09, PPC2_VSX),
@@ -10100,6 +10120,9 @@ GEN_XX3FORM(xvnmsubasp, 0x04, 0x1A, PPC2_VSX),
GEN_XX3FORM(xvnmsubmsp, 0x04, 0x1B, PPC2_VSX),
GEN_XX3FORM(xvmaxsp, 0x00, 0x18, PPC2_VSX),
GEN_XX3FORM(xvminsp, 0x00, 0x19, PPC2_VSX),
+GEN_XX3_RC_FORM(xvcmpeqsp, 0x0C, 0x08, PPC2_VSX),
+GEN_XX3_RC_FORM(xvcmpgtsp, 0x0C, 0x09, PPC2_VSX),
+GEN_XX3_RC_FORM(xvcmpgesp, 0x0C, 0x0A, PPC2_VSX),
#undef VSX_LOGICAL
#define VSX_LOGICAL(name, opc2, opc3, fl2) \
--
1.7.1
next prev parent reply other threads:[~2013-11-01 13:36 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-11-01 13:35 [Qemu-devel] [PATCH V3 00/19] PowerPC VSX Stage 3 Tom Musta
2013-11-01 13:35 ` [Qemu-devel] [PATCH V3 01/19] Fix float64_to_uint64 Tom Musta
2013-12-17 13:42 ` [Qemu-devel] [Qemu-ppc] " Alexander Graf
2013-12-17 13:52 ` Peter Maydell
2013-12-17 14:03 ` Alexander Graf
2013-12-18 14:21 ` Tom Musta
2013-12-18 14:35 ` Peter Maydell
2013-12-18 15:31 ` Tom Musta
2013-12-18 15:52 ` Peter Maydell
2013-12-18 20:43 ` Tom Musta
2013-12-18 20:44 ` Tom Musta
2013-11-01 13:35 ` [Qemu-devel] [PATCH V3 02/19] Add float32_to_uint64() Tom Musta
2013-11-01 13:35 ` [Qemu-devel] [PATCH V3 03/19] Add set_fprf Argument to fload_invalid_op_excp() Tom Musta
2013-11-01 13:35 ` [Qemu-devel] [PATCH V3 04/19] General Support for VSX Helpers Tom Musta
2013-11-01 13:35 ` [Qemu-devel] [PATCH V3 05/19] Add VSX ISA2.06 xadd/xsub Instructions Tom Musta
2013-11-01 13:35 ` [Qemu-devel] [PATCH V3 06/19] Add VSX ISA2.06 xmul Instructions Tom Musta
2013-11-01 13:35 ` [Qemu-devel] [PATCH V3 07/19] Add VSX ISA2.06 xdiv Instructions Tom Musta
2013-11-01 13:35 ` [Qemu-devel] [PATCH V3 08/19] Add VSX ISA2.06 xre Instructions Tom Musta
2013-11-01 13:35 ` [Qemu-devel] [PATCH V3 09/19] Add VSX ISA2.06 xsqrt Instructions Tom Musta
2013-11-01 13:35 ` [Qemu-devel] [PATCH V3 10/19] Add VSX ISA2.06 xrsqrte Instructions Tom Musta
2013-11-01 13:35 ` [Qemu-devel] [PATCH V3 11/19] Add VSX ISA2.06 xtdiv Instructions Tom Musta
2013-11-01 13:35 ` [Qemu-devel] [PATCH V3 12/19] Add VSX ISA2.06 xtsqrt Instructions Tom Musta
2013-11-01 13:35 ` [Qemu-devel] [PATCH V3 13/19] Add VSX ISA2.06 Multiply Add Instructions Tom Musta
2013-11-01 13:35 ` [Qemu-devel] [PATCH V3 14/19] Add VSX xscmp*dp Instructions Tom Musta
2013-11-01 13:35 ` [Qemu-devel] [PATCH V3 15/19] Add VSX xmax/xmin Instructions Tom Musta
2013-11-01 13:35 ` Tom Musta [this message]
2013-11-01 13:35 ` [Qemu-devel] [PATCH V3 17/19] Add VSX Floating Point to Floating Point Conversion Instructions Tom Musta
2013-11-01 13:35 ` [Qemu-devel] [PATCH V3 18/19] Add VSX ISA2.06 Integer " Tom Musta
2013-11-01 13:35 ` [Qemu-devel] [PATCH V3 19/19] Add VSX Rounding Instructions Tom Musta
2013-12-03 16:16 ` [Qemu-devel] [PATCH V3 00/19] PowerPC VSX Stage 3 Tom Musta
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