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From: Paul Bolle <pebolle@tiscali.nl>
To: Bjorn Helgaas <bhelgaas@google.com>
Cc: Steven Newbury <steve@snewbury.org.uk>,
	Daniel Vetter <daniel.vetter@ffwll.ch>,
	David Airlie <airlied@linux.ie>,
	intel-gfx <intel-gfx@lists.freedesktop.org>,
	Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
	Yinghai Lu <yinghai@kernel.org>,
	linux-pci@vger.kernel.org
Subject: Re: [Intel-gfx] agp/intel: can't ioremap flush page - no chipset flushing
Date: Tue, 11 Mar 2014 00:45:21 +0100	[thread overview]
Message-ID: <1394495121.1975.6.camel@x41> (raw)
In-Reply-To: <20140310182431.GA11424@google.com>

Bjorn Helgaas schreef op ma 10-03-2014 om 12:24 [-0600]:
> Thanks.  Can you try the patch below?  I think it should fix the problem.
> 
> 
> PCI: Don't check resource_size() in pci_bus_alloc_resource()
> 
> From: Bjorn Helgaas <bhelgaas@google.com>
> 
> When resource_size_t is 32 bits wide, e.g., when CONFIG_PHYS_ADDR_T_64BIT
> is not defined, resource_size() on [mem 0x00000000-0xffffffff] returns 0
> because (r->end - r->start + 1) overflows.
> 
> Therefore, we can't use "resource_size() == 0" to decide that allocation
> from this resource will fail.  allocate_resource() should fail anyway if it
> can't satisfy the address constraints, so we should just depend on that.
> 
> A [mem 0x00000000-0xffffffff] bus resource is obviously not really valid,
> but we do fall back to it as a default when we don't have information about
> host bridge apertures.
> 
> Link: https://bugzilla.kernel.org/show_bug.cgi?id=71611
> Fixes: f75b99d5a77d PCI: Enforce bus address limits in resource allocation
> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
> ---
>  drivers/pci/bus.c |    2 --
>  1 file changed, 2 deletions(-)
> 
> diff --git a/drivers/pci/bus.c b/drivers/pci/bus.c
> index 00660cc502c5..38901665c770 100644
> --- a/drivers/pci/bus.c
> +++ b/drivers/pci/bus.c
> @@ -162,8 +162,6 @@ static int pci_bus_alloc_from_region(struct pci_bus *bus, struct resource *res,
>  
>  		avail = *r;
>  		pci_clip_resource_to_region(bus, &avail, region);
> -		if (!resource_size(&avail))
> -			continue;
>  
>  		/*
>  		 * "min" is typically PCIBIOS_MIN_IO or PCIBIOS_MIN_MEM to

I've applied your patch on top of v3.14-rc6. The boot warning is gone.
And /proc/iomem once again has the lines:
    [...]
    80000000-801fffff : PCI Bus 0000:02
    80200000-8027ffff : 0000:00:02.1
    80280000-80280fff : Intel Flush Page
    [...]

Which is what we want, don't we?

A bit of doubt is caused by two new boot time messages:
    pnp 00:00: unknown resource type 10 in _CRS
    pnp 00:00: can't evaluate _CRS: 1

But I haven't yet tried v3.14-rc6 without your patch, so these might be
unrelated. They're unclear to me, anyway.

Thanks,


Paul Bolle


WARNING: multiple messages have this Message-ID (diff)
From: Paul Bolle <pebolle@tiscali.nl>
To: Bjorn Helgaas <bhelgaas@google.com>
Cc: David Airlie <airlied@linux.ie>,
	Daniel Vetter <daniel.vetter@ffwll.ch>,
	intel-gfx <intel-gfx@lists.freedesktop.org>,
	Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
	linux-pci@vger.kernel.org, Yinghai Lu <yinghai@kernel.org>
Subject: Re: agp/intel: can't ioremap flush page - no chipset flushing
Date: Tue, 11 Mar 2014 00:45:21 +0100	[thread overview]
Message-ID: <1394495121.1975.6.camel@x41> (raw)
In-Reply-To: <20140310182431.GA11424@google.com>

Bjorn Helgaas schreef op ma 10-03-2014 om 12:24 [-0600]:
> Thanks.  Can you try the patch below?  I think it should fix the problem.
> 
> 
> PCI: Don't check resource_size() in pci_bus_alloc_resource()
> 
> From: Bjorn Helgaas <bhelgaas@google.com>
> 
> When resource_size_t is 32 bits wide, e.g., when CONFIG_PHYS_ADDR_T_64BIT
> is not defined, resource_size() on [mem 0x00000000-0xffffffff] returns 0
> because (r->end - r->start + 1) overflows.
> 
> Therefore, we can't use "resource_size() == 0" to decide that allocation
> from this resource will fail.  allocate_resource() should fail anyway if it
> can't satisfy the address constraints, so we should just depend on that.
> 
> A [mem 0x00000000-0xffffffff] bus resource is obviously not really valid,
> but we do fall back to it as a default when we don't have information about
> host bridge apertures.
> 
> Link: https://bugzilla.kernel.org/show_bug.cgi?id=71611
> Fixes: f75b99d5a77d PCI: Enforce bus address limits in resource allocation
> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
> ---
>  drivers/pci/bus.c |    2 --
>  1 file changed, 2 deletions(-)
> 
> diff --git a/drivers/pci/bus.c b/drivers/pci/bus.c
> index 00660cc502c5..38901665c770 100644
> --- a/drivers/pci/bus.c
> +++ b/drivers/pci/bus.c
> @@ -162,8 +162,6 @@ static int pci_bus_alloc_from_region(struct pci_bus *bus, struct resource *res,
>  
>  		avail = *r;
>  		pci_clip_resource_to_region(bus, &avail, region);
> -		if (!resource_size(&avail))
> -			continue;
>  
>  		/*
>  		 * "min" is typically PCIBIOS_MIN_IO or PCIBIOS_MIN_MEM to

I've applied your patch on top of v3.14-rc6. The boot warning is gone.
And /proc/iomem once again has the lines:
    [...]
    80000000-801fffff : PCI Bus 0000:02
    80200000-8027ffff : 0000:00:02.1
    80280000-80280fff : Intel Flush Page
    [...]

Which is what we want, don't we?

A bit of doubt is caused by two new boot time messages:
    pnp 00:00: unknown resource type 10 in _CRS
    pnp 00:00: can't evaluate _CRS: 1

But I haven't yet tried v3.14-rc6 without your patch, so these might be
unrelated. They're unclear to me, anyway.

Thanks,


Paul Bolle

  reply	other threads:[~2014-03-10 23:45 UTC|newest]

Thread overview: 46+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-02-08 19:06 agp/intel: can't ioremap flush page - no chipset flushing Paul Bolle
2014-02-08 19:59 ` Daniel Vetter
2014-02-08 19:59   ` Daniel Vetter
2014-02-08 20:22   ` Paul Bolle
2014-02-09  0:02     ` Daniel Vetter
2014-02-09  0:02       ` Daniel Vetter
2014-02-09 13:15       ` Steven Newbury
2014-02-09 13:15         ` [Intel-gfx] " Steven Newbury
2014-02-09 13:25         ` Paul Bolle
2014-02-09 13:25           ` [Intel-gfx] " Paul Bolle
2014-02-09 13:32           ` Steven Newbury
2014-02-09 13:32             ` [Intel-gfx] " Steven Newbury
2014-02-10 21:33           ` Bjorn Helgaas
2014-02-10 21:33             ` [Intel-gfx] " Bjorn Helgaas
2014-03-06 20:25             ` Paul Bolle
2014-03-06 20:25               ` [Intel-gfx] " Paul Bolle
2014-03-06 21:38               ` Bjorn Helgaas
2014-03-06 21:38                 ` [Intel-gfx] " Bjorn Helgaas
2014-03-07 20:33               ` Bjorn Helgaas
2014-03-07 20:33                 ` [Intel-gfx] " Bjorn Helgaas
2014-03-07  9:48             ` Paul Bolle
2014-03-07  9:48               ` [Intel-gfx] " Paul Bolle
2014-03-07 16:55               ` Bjorn Helgaas
2014-03-07 16:55                 ` [Intel-gfx] " Bjorn Helgaas
2014-03-07 17:16                 ` Paul Bolle
2014-03-07 17:16                   ` [Intel-gfx] " Paul Bolle
2014-03-07 20:40                   ` Bjorn Helgaas
2014-03-07 20:40                     ` [Intel-gfx] " Bjorn Helgaas
2014-03-07 21:03                     ` Paul Bolle
2014-03-07 21:03                       ` [Intel-gfx] " Paul Bolle
2014-03-07 22:07                       ` Bjorn Helgaas
2014-03-07 22:07                         ` [Intel-gfx] " Bjorn Helgaas
2014-03-08 14:12                     ` Bjorn Helgaas
2014-03-08 14:12                       ` [Intel-gfx] " Bjorn Helgaas
2014-03-08 14:44                       ` Paul Bolle
2014-03-08 14:44                         ` [Intel-gfx] " Paul Bolle
2014-03-10 18:24                         ` Bjorn Helgaas
2014-03-10 18:24                           ` Bjorn Helgaas
2014-03-10 23:45                           ` Paul Bolle [this message]
2014-03-10 23:45                             ` Paul Bolle
2014-03-11  0:07                             ` [Intel-gfx] " Bjorn Helgaas
2014-03-11  0:07                               ` Bjorn Helgaas
2014-03-11  0:15                               ` [Intel-gfx] " Paul Bolle
2014-03-11  2:07                                 ` Bjorn Helgaas
2014-03-11  9:20                                   ` Paul Bolle
2014-03-11  9:20                                     ` Paul Bolle

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