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From: <Eugen.Hristev@microchip.com>
To: <clement.leger@bootlin.com>
Cc: <Ludovic.Desroches@microchip.com>, <u-boot@lists.denx.de>,
	<Nicolas.Ferre@microchip.com>, <thomas.petazzoni@bootlin.com>,
	<Claudiu.Beznea@microchip.com>
Subject: Re: [PATCH v7 4/4] configs: sama5d2: enable option CONFIG_ATMEL_TCB_TIMER
Date: Thu, 31 Mar 2022 05:59:02 +0000	[thread overview]
Message-ID: <13daf34f-2524-40c0-8e92-3988ab34b2be@microchip.com> (raw)
In-Reply-To: <20220330174956.04f10e5d@fixe.home>

On 3/30/22 6:49 PM, Clément Léger wrote:
> Le Tue, 22 Mar 2022 13:35:08 +0100,
> Clément Léger <clement.leger@bootlin.com> a écrit :
> 
>> Le Tue, 22 Mar 2022 11:18:39 +0000,
>> <Eugen.Hristev@microchip.com> a écrit :
>>
> 
> [...]
> 
>>>
>>> Could not initialize timer (err -22)
>>>
>>> ...
>>>
>>>
>>>
>>> Could you investigate this please ?
>>
>> Hi Eugen,
>>
>> Ok, I'll try to debug that !
> 
> Hi Eugen, while debugging it, I found that there was actually one major
> flaw. The clock that I used was the GLCK. If only this clock is
> enabled, the TCB can not work, the tcb0_clk must also be enabled for the
> TCB to start counting. It worked on my side because I forgot that I had
> a quirk in OP-TEE that was enabling the clocks before starting U-Boot.
> Without that, it actually could not work.
> 
> Since the tcb0_clk is needed, I switched the driver to use this one
> only and it works well on a "bare" setup (ie without OP-TEE). I even
> think it could not work with the tcb0_gclk since this one does not
> correctly handles the case when the parent clock is the slow_clk (which
> might be the case after booting) and in this case, will return 0 as
> rate (this is by the way supported in your CCF branch).
> 
> Anyway, I fixed the driver to use the tcb0_clk and thus it should work
> much better. I will send a V8 and it should work with U-Boot and the
> SPL.
> 
> By the way, do you have any documentation which explains how to use
> U-Boot SPL on sama5d2_xplained (or other) board ?

Hi Clement,

I don't have any documentation at hand, but what I can say in a few 
words is that once you build the SPL, you should have a file 
spl/boot.bin and this binary should replace our stage2 at91 bootloader 
at91bootstrap.

Unlike at91bootstrap, the SPL has all the drivers inside and can boot 
from all supported media, however, SPL will read a dedicated CPU 
register where the stage1 has written some bits representing the index 
of the NVM *used to copy the boot.bin from* . The SPL will then attempt 
to read the u-boot.bin from the same media. (you can alter the file name 
in defconfig ).

What is required for your series is that the SPL still works as it 
worked before your series. (e.g. no regressions with your patches).

Eugen

> 
> Regards,
> 
> Clément.
> 
> --
> Clément Léger,
> Embedded Linux and Kernel engineer at Bootlin
> https://bootlin.com
> 


  reply	other threads:[~2022-03-31  5:59 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-03-11  9:35 [PATCH v7 0/4] add TCB driver for sama5d2 Clément Léger
2022-03-11  9:35 ` [PATCH v7 1/4] timer: atmel_tcb_timer: add atmel_tcb driver Clément Léger
2022-03-11  9:35 ` [PATCH v7 2/4] ARM: dts: at91: sama5d2: add AIC node Clément Léger
2022-03-11  9:35 ` [PATCH v7 3/4] ARM: dts: at91: sama5d2: add TCB node Clément Léger
2022-03-11  9:35 ` [PATCH v7 4/4] configs: sama5d2: enable option CONFIG_ATMEL_TCB_TIMER Clément Léger
2022-03-22 11:18   ` Eugen.Hristev
2022-03-22 12:35     ` Clément Léger
2022-03-30 15:49       ` Clément Léger
2022-03-31  5:59         ` Eugen.Hristev [this message]
2022-03-31  7:40           ` Clément Léger
2022-03-31  7:53             ` Eugen.Hristev

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