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From: geoff@infradead.org (Geoff Levand)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 9/9] arm64: Add new cpu-return-addr device tree binding
Date: Fri, 29 Aug 2014 14:45:04 -0700	[thread overview]
Message-ID: <1409348704.21254.95.camel@smoke> (raw)
In-Reply-To: <20140827083022.GE6968@arm.com>

Hi Catalin,

On Wed, 2014-08-27 at 09:30 +0100, Catalin Marinas wrote:
> On Fri, Aug 22, 2014 at 08:49:17PM +0100, Geoff Levand wrote:
> > Add a new arm64 device tree binding cpu-return-addr.  This binding is recomended
> > for all ARM v8 CPUs that have an "enable-method" property value of "spin-table".
> > The value is a 64 bit physical address that secondary CPU execution will transfer
> > to upon CPU shutdown.
> > 
> > Signed-off-by: Geoff Levand <geoff@infradead.org>
> > ---
> >  Documentation/devicetree/bindings/arm/cpus.txt | 25 +++++++++++++++++++++++++
> >  1 file changed, 25 insertions(+)
> > 
> > diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
> > index 1fe72a0..42d5d5f 100644
> > --- a/Documentation/devicetree/bindings/arm/cpus.txt
> > +++ b/Documentation/devicetree/bindings/arm/cpus.txt
> > @@ -201,6 +201,15 @@ nodes to be present and contain the properties described below.
> >  			  property identifying a 64-bit zero-initialised
> >  			  memory location.
> >  
> > +	- cpu-return-addr
> > +		Usage: recomended for all ARM v8 CPUs that have an
> > +		       "enable-method" property value of "spin-table".
> > +		Value type: <prop-encoded-array>
> > +		Definition:
> > +			# On ARM v8 64-bit systems must be a two cell property.
> > +			The value is a 64 bit physical address that secondary
> > +			CPU execution will transfer to upon CPU shutdown.
> 
> As I've been away for most of the past four weeks, I haven't read all
> the threads around this topic. But I don't think we ended up with a
> clearly agreed recommendation for cpu-return-addr. If we do, we also
> need to be clear on what state the CPU should be in when returned to
> such address (ELx, MMU, caches).

Regarding the system state, I think what Mark proposed [1] is what we
should work towards.  I'll add that to the binding's Definition text.

I have not tried to implement it yet though, but once I get it working
and tested we'll be able to say that this is what works and should be
the interface.

[1] http://lists.infradead.org/pipermail/linux-arm-kernel/2014-August/278910.html

> In general, if we need returning to firmware I would strongly recommend
> PSCI but I know there is the Applied board which does not have EL3, so
> something like this may work. But we need to get them into discussion as
> well since I assume cpu-return-addr would be a firmware provided
> address.

Yes, cpu-return-addr will be (optionally) provided by the firmware.

The current kexec_prepare system call implementation I have checks
the return of cpu_ops.cpu_disable() for all CPUs.  I have setup the
spin-table cpu_disable() to check if the device tree defines a
cpu-return-addr for that CPU.  So if there is no cpu-return-addr
kexec_prepare will fail and the user will get an error on a kernel
load from kexec-tools.

Feng Kan of APM has already said that address O will work correctly
for the APM board [2], and Arun Chandran has tested this.

[2] http://lists.infradead.org/pipermail/linux-arm-kernel/2014-July/273084.html

-Geoff

WARNING: multiple messages have this Message-ID (diff)
From: Geoff Levand <geoff-wEGCiKHe2LqWVfeAwA7xHQ@public.gmane.org>
To: Catalin Marinas <catalin.marinas-5wv7dgnIgG8@public.gmane.org>,
	Feng Kan <fkan-qTEPVZfXA3Y@public.gmane.org>,
	Arun Chandran <achandran-Igf4POYTYCDQT0dZR+AlfA@public.gmane.org>
Cc: Will Deacon <Will.Deacon-5wv7dgnIgG8@public.gmane.org>,
	"linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org"
	<linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org>,
	"grant.likely-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org"
	<grant.likely-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>,
	Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>,
	"devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org"
	<devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>,
	Mark Rutland <Mark.Rutland-5wv7dgnIgG8@public.gmane.org>
Subject: Re: [PATCH 9/9] arm64: Add new cpu-return-addr device tree binding
Date: Fri, 29 Aug 2014 14:45:04 -0700	[thread overview]
Message-ID: <1409348704.21254.95.camel@smoke> (raw)
In-Reply-To: <20140827083022.GE6968-5wv7dgnIgG8@public.gmane.org>

Hi Catalin,

On Wed, 2014-08-27 at 09:30 +0100, Catalin Marinas wrote:
> On Fri, Aug 22, 2014 at 08:49:17PM +0100, Geoff Levand wrote:
> > Add a new arm64 device tree binding cpu-return-addr.  This binding is recomended
> > for all ARM v8 CPUs that have an "enable-method" property value of "spin-table".
> > The value is a 64 bit physical address that secondary CPU execution will transfer
> > to upon CPU shutdown.
> > 
> > Signed-off-by: Geoff Levand <geoff-wEGCiKHe2LqWVfeAwA7xHQ@public.gmane.org>
> > ---
> >  Documentation/devicetree/bindings/arm/cpus.txt | 25 +++++++++++++++++++++++++
> >  1 file changed, 25 insertions(+)
> > 
> > diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
> > index 1fe72a0..42d5d5f 100644
> > --- a/Documentation/devicetree/bindings/arm/cpus.txt
> > +++ b/Documentation/devicetree/bindings/arm/cpus.txt
> > @@ -201,6 +201,15 @@ nodes to be present and contain the properties described below.
> >  			  property identifying a 64-bit zero-initialised
> >  			  memory location.
> >  
> > +	- cpu-return-addr
> > +		Usage: recomended for all ARM v8 CPUs that have an
> > +		       "enable-method" property value of "spin-table".
> > +		Value type: <prop-encoded-array>
> > +		Definition:
> > +			# On ARM v8 64-bit systems must be a two cell property.
> > +			The value is a 64 bit physical address that secondary
> > +			CPU execution will transfer to upon CPU shutdown.
> 
> As I've been away for most of the past four weeks, I haven't read all
> the threads around this topic. But I don't think we ended up with a
> clearly agreed recommendation for cpu-return-addr. If we do, we also
> need to be clear on what state the CPU should be in when returned to
> such address (ELx, MMU, caches).

Regarding the system state, I think what Mark proposed [1] is what we
should work towards.  I'll add that to the binding's Definition text.

I have not tried to implement it yet though, but once I get it working
and tested we'll be able to say that this is what works and should be
the interface.

[1] http://lists.infradead.org/pipermail/linux-arm-kernel/2014-August/278910.html

> In general, if we need returning to firmware I would strongly recommend
> PSCI but I know there is the Applied board which does not have EL3, so
> something like this may work. But we need to get them into discussion as
> well since I assume cpu-return-addr would be a firmware provided
> address.

Yes, cpu-return-addr will be (optionally) provided by the firmware.

The current kexec_prepare system call implementation I have checks
the return of cpu_ops.cpu_disable() for all CPUs.  I have setup the
spin-table cpu_disable() to check if the device tree defines a
cpu-return-addr for that CPU.  So if there is no cpu-return-addr
kexec_prepare will fail and the user will get an error on a kernel
load from kexec-tools.

Feng Kan of APM has already said that address O will work correctly
for the APM board [2], and Arun Chandran has tested this.

[2] http://lists.infradead.org/pipermail/linux-arm-kernel/2014-July/273084.html

-Geoff




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  reply	other threads:[~2014-08-29 21:45 UTC|newest]

Thread overview: 37+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-08-22 19:49 [PATCH 0/9] arm64: minor fixups and enhancements Geoff Levand
2014-08-22 19:49 ` [PATCH 1/9] arm64: Fix efi kernel entry Geoff Levand
2014-08-26 15:55   ` Catalin Marinas
2014-08-26 16:19     ` Ard Biesheuvel
2014-08-26 18:42       ` Geoff Levand
2014-08-22 19:49 ` [PATCH 7/9] arm64: Add atomic macros to assembler.h Geoff Levand
2014-08-26 16:05   ` Catalin Marinas
2014-08-26 19:40     ` Geoff Levand
2014-08-27  8:25       ` Catalin Marinas
2014-08-22 19:49 ` [PATCH 2/9] arm64: Fix INVALID_HWID definition Geoff Levand
2014-08-26 15:57   ` Catalin Marinas
2014-08-26 18:18     ` Geoff Levand
2014-08-27  8:21       ` Catalin Marinas
2014-08-26 16:31   ` Mark Rutland
2014-08-26 17:38     ` Geoff Levand
2014-08-22 19:49 ` [PATCH 6/9] arm64: Add new routine local_disable Geoff Levand
2014-08-26 16:04   ` Catalin Marinas
2014-08-26 16:23     ` Mark Rutland
2014-08-22 19:49 ` [PATCH 3/9] arm64: Remove unneeded extern keyword Geoff Levand
2014-08-26 16:11   ` Mark Rutland
2014-08-22 19:49 ` [PATCH 4/9] arm64: Remove unused variable in head.S Geoff Levand
2014-08-27  8:40   ` Will Deacon
2014-08-22 19:49 ` [PATCH 5/9] arm64: Fix include header order in vmlinux.lds.S Geoff Levand
2014-08-26 16:27   ` Mark Rutland
2014-08-26 19:27     ` Geoff Levand
2014-08-27  8:24       ` Catalin Marinas
2014-08-29 21:53         ` Geoff Levand
2014-08-22 19:49 ` [PATCH 8/9] arm64: Add missing AT() macros to vmlinux.lds.S Geoff Levand
2014-08-26 16:08   ` Catalin Marinas
2014-08-26 19:33     ` Geoff Levand
2014-08-27  6:53       ` AKASHI Takahiro
2014-08-22 19:49 ` [PATCH 9/9] arm64: Add new cpu-return-addr device tree binding Geoff Levand
2014-08-22 19:49   ` Geoff Levand
2014-08-27  8:30   ` Catalin Marinas
2014-08-27  8:30     ` Catalin Marinas
2014-08-29 21:45     ` Geoff Levand [this message]
2014-08-29 21:45       ` Geoff Levand

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