UBI on dual NAND chips

UBI on dual NAND chips

[Nathan Williams]

Hi,

We are planning to use two 32GiB MLC NAND flash chips in a product using
a SoC FPGA with two NAND interfaces. The motivation for wanting to use
multiple NAND chips is to improve reliability, not capacity.

>From what I've read, it's possible to use UBI on a concatenated MTD.
If I have two identical chips, will these be concatenated automatically?

Is creating a single UBI volume over the two NAND chips (and using UBIFS
on it) the best way to make use of a redundant NAND chip? Would
mirroring data on a second UBI volume offer additional improvements to
data reliability?

Also, what's the current status of the "unstable bits issue"?

Thanks,
Nathan

Re: UBI on dual NAND chips

[Richard Weinberger]

Nathan,

On Thu, Sep 24, 2015 at 4:44 AM, Nathan Williams
<nathan.williams@flightdata.com.au> wrote:
> We are planning to use two 32GiB MLC NAND flash chips in a product using
> a SoC FPGA with two NAND interfaces. The motivation for wanting to use
> multiple NAND chips is to improve reliability, not capacity.

Using UBI on MLC is not supported yet.
IOW, you have been warned. ;-)

> From what I've read, it's possible to use UBI on a concatenated MTD.
> If I have two identical chips, will these be concatenated automatically?

You mean using the mtd_concat driver?

> Is creating a single UBI volume over the two NAND chips (and using UBIFS
> on it) the best way to make use of a redundant NAND chip? Would
> mirroring data on a second UBI volume offer additional improvements to
> data reliability?

Depends on how you define "data reliability".
You're looking for something like an MTD RAID1 to deal with a dead chip?

> Also, what's the current status of the "unstable bits issue"?

It is a known issue but nobody cared hard enough so far.
Mostly due to the fact that nobody actually can trigger it.

Can you trigger it? If so, I'd like to get access to that hardware
and have a look.

-- 
Thanks,
//richard

Re: UBI on dual NAND chips

[Nathan Williams]

On Thu, 2015-09-24 at 11:02 +0200, Richard Weinberger wrote:
> Using UBI on MLC is not supported yet.
> IOW, you have been warned. ;-)

Thanks. I wasn't sure, despite my background reading.

> > From what I've read, it's possible to use UBI on a concatenated MTD.
> > If I have two identical chips, will these be concatenated automatically?
> 
> You mean using the mtd_concat driver?

Yes.

> > Is creating a single UBI volume over the two NAND chips (and using UBIFS
> > on it) the best way to make use of a redundant NAND chip? Would
> > mirroring data on a second UBI volume offer additional improvements to
> > data reliability?
> 
> Depends on how you define "data reliability".
> You're looking for something like an MTD RAID1 to deal with a dead chip?

Yes that would be ideal. The NAND flash will be used for data logging.
We'd like to use multiple chips to improve our chances of recovering
recorded data in the event that either a chip dies or there are too many
errors.

> > Also, what's the current status of the "unstable bits issue"?
> 
> It is a known issue but nobody cared hard enough so far.
> Mostly due to the fact that nobody actually can trigger it.
> 
> Can you trigger it? If so, I'd like to get access to that hardware
> and have a look.

No I haven't seen it. Our hardware is still in the planning phase.

Re: UBI on dual NAND chips

[Nathan Williams]

On Fri, 2015-09-25 at 01:16 +0000, Bean Huo 霍斌斌 (beanhuo) wrote:
> Hi, 
> Do you already enable mtd_concat driver on your MLC NAND?
> For MLC NAND, I think, it is not suitable. 

I don't have any hardware yet. I'm still only investigating the
possibilities. At the moment it looks like we'll design hardware with
two NAND interfaces and see what we can get working. Perhaps we will
start with one chip and only use half of it until the paired pages issue
is resolved.

RE: UBI on dual NAND chips

[Bean Huo 霍斌斌 (beanhuo)]

> On Fri, 2015-09-25 at 01:16 +0000, Bean Huo 霍斌斌 (beanhuo) wrote:
> > Hi,
> > Do you already enable mtd_concat driver on your MLC NAND?
> > For MLC NAND, I think, it is not suitable.
> 
> I don't have any hardware yet. I'm still only investigating the possibilities. At
> the moment it looks like we'll design hardware with two NAND interfaces and
> see what we can get working. Perhaps we will start with one chip and only use
> half of it until the paired pages issue is resolved.

Means you regard MLC NAND as SLC NAND, only program lower page?
For paired pages issue, we just now have two methods solution based on UBI,
This week I will send out first one, we can talk about it together, if you interested in it.