Re: [PATCH v3 7/9] xen/arm: vgic: Optimize the way to store the target vCPU in the rank

[Ian Campbell <ian.campbell@citrix.com>]

On Wed, 2015-10-07 at 19:16 +0100, Julien Grall wrote:

> Furthermore, based on the spec (4.3.12 in IHI 0048B.b): "A register
> field corresponding to an unimplemented interrupt is RAZ/WI."
> 
> If the user knows that an interrupt is not implemented, he may decide to
> write 0 in the corresponding byte. With the current solution, the whole
> write access is ignored.
> 
> The solution suggested in this patch is less restrictive and will just
> ignore the corresponding byte if it's 0.

I think this (a 32-bit register covering both implemented and non
-implemented interrupts) is a compelling reason to only ignore the specific
zero bytes and not the whole word.

> On another side, nothing in the spec specified what happen if the target
> field is 0 for a valid interrupt. But I think this is OK to just ignore
> it and carry on. It's simpler to implement.


On a (not very) related notes, these registers are res0 when affinity
routing is enabled on gic-v3 (which I think is our hardcoded configuration)
and I noticed that vgic_v3_distr_mmio_read doesn't look to implement that
explicitly, hence it uses the default case which logs. Probably we should
add a proper handler which silently does RAZ/WI?