From: Kai Huang <kai.huang@linux.intel.com>
To: jbeulich@suse.com, andrew.cooper3@citrix.com,
george.dunlap@eu.citrix.com, kevin.tian@intel.com,
jun.nakajima@intel.com, xen-devel@lists.xen.org
Cc: Kai Huang <kai.huang@linux.intel.com>
Subject: [PATCH 2/2] x86/vmx: fix coding style of PML functions
Date: Tue, 20 Oct 2015 10:34:46 +0800 [thread overview]
Message-ID: <1445308486-25132-3-git-send-email-kai.huang@linux.intel.com> (raw)
In-Reply-To: <1445308486-25132-1-git-send-email-kai.huang@linux.intel.com>
According to Jan's comments, also fix the coding style of for_each_vcpu in
existing PML functions.
Signed-off-by: Kai Huang <kai.huang@linux.intel.com>
---
xen/arch/x86/hvm/vmx/vmcs.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/xen/arch/x86/hvm/vmx/vmcs.c b/xen/arch/x86/hvm/vmx/vmcs.c
index c11f3ec..4ea1ad1 100644
--- a/xen/arch/x86/hvm/vmx/vmcs.c
+++ b/xen/arch/x86/hvm/vmx/vmcs.c
@@ -1500,7 +1500,7 @@ int vmx_domain_enable_pml(struct domain *d)
if ( vmx_domain_pml_enabled(d) )
return 0;
- for_each_vcpu( d, v )
+ for_each_vcpu ( d, v )
if ( (rc = vmx_vcpu_enable_pml(v)) != 0 )
goto error;
@@ -1509,7 +1509,7 @@ int vmx_domain_enable_pml(struct domain *d)
return 0;
error:
- for_each_vcpu( d, v )
+ for_each_vcpu ( d, v )
if ( vmx_vcpu_pml_enabled(v) )
vmx_vcpu_disable_pml(v);
return rc;
@@ -1530,7 +1530,7 @@ void vmx_domain_disable_pml(struct domain *d)
if ( !vmx_domain_pml_enabled(d) )
return;
- for_each_vcpu( d, v )
+ for_each_vcpu ( d, v )
vmx_vcpu_disable_pml(v);
d->arch.hvm_domain.vmx.status &= ~VMX_DOMAIN_PML_ENABLED;
@@ -1549,7 +1549,7 @@ void vmx_domain_flush_pml_buffers(struct domain *d)
if ( !vmx_domain_pml_enabled(d) )
return;
- for_each_vcpu( d, v )
+ for_each_vcpu ( d, v )
vmx_vcpu_flush_pml_buffer(v);
}
--
2.1.4
next prev parent reply other threads:[~2015-10-20 2:34 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-10-20 2:34 [PATCH 0/2] Deter enabling of EPT A/D bit plus coding style fix Kai Huang
2015-10-20 2:34 ` [PATCH 1/2] x86/ept: defer enabling of EPT A/D bit until PML get enabled Kai Huang
2015-10-20 9:46 ` Jan Beulich
2015-10-20 10:01 ` Andrew Cooper
2015-10-21 3:00 ` Tian, Kevin
2015-10-20 2:34 ` Kai Huang [this message]
2015-10-20 10:01 ` [PATCH 2/2] x86/vmx: fix coding style of PML functions Andrew Cooper
2015-10-21 3:00 ` Tian, Kevin
2015-10-20 10:44 ` [PATCH 0/2] Deter enabling of EPT A/D bit plus coding style fix Kai Huang
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