From: Andrew Cooper <andrew.cooper3@citrix.com>
To: Kai Huang <kai.huang@linux.intel.com>,
jbeulich@suse.com, george.dunlap@eu.citrix.com,
kevin.tian@intel.com, jun.nakajima@intel.com,
xen-devel@lists.xen.org
Subject: Re: [PATCH 1/2] x86/ept: defer enabling of EPT A/D bit until PML get enabled.
Date: Tue, 20 Oct 2015 11:01:20 +0100 [thread overview]
Message-ID: <562610F0.4020308@citrix.com> (raw)
In-Reply-To: <1445308486-25132-2-git-send-email-kai.huang@linux.intel.com>
On 20/10/15 03:34, Kai Huang wrote:
> Existing PML implementation turns on EPT A/D bit unconditionally if PML is
> supported by hardware. This works but enabling of EPT A/D bit can be deferred
> until PML get enabled. There's no point in enabling the extra feature for every
> domain when we're not meaning to use it (yet).
>
> Also added ASSERT of domain having been paused to ept_flush_pml_buffers to make
> it consistent with ept_enable{disable}_pml.
>
> Sanity live migration and GUI display were tested on Broadwell Machine.
>
> Signed-off-by: Kai Huang <kai.huang@linux.intel.com>
> Suggested-by: Jan Beulich <jbeulich@suse.com>
Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>
next prev parent reply other threads:[~2015-10-20 10:01 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-10-20 2:34 [PATCH 0/2] Deter enabling of EPT A/D bit plus coding style fix Kai Huang
2015-10-20 2:34 ` [PATCH 1/2] x86/ept: defer enabling of EPT A/D bit until PML get enabled Kai Huang
2015-10-20 9:46 ` Jan Beulich
2015-10-20 10:01 ` Andrew Cooper [this message]
2015-10-21 3:00 ` Tian, Kevin
2015-10-20 2:34 ` [PATCH 2/2] x86/vmx: fix coding style of PML functions Kai Huang
2015-10-20 10:01 ` Andrew Cooper
2015-10-21 3:00 ` Tian, Kevin
2015-10-20 10:44 ` [PATCH 0/2] Deter enabling of EPT A/D bit plus coding style fix Kai Huang
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