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From: Archit Taneja <architt@codeaurora.org>
To: sboyd@codeaurora.org
Cc: linux-arm-msm@vger.kernel.org,
	Archit Taneja <architt@codeaurora.org>,
	John Stultz <john.stultz@linaro.org>,
	Vinay Simha <vinaysimha@inforcecomputing.com>
Subject: [PATCH] clk: qcom: Fix pre-divider usage for pixel RCG
Date: Fri, 26 Feb 2016 11:00:55 +0530	[thread overview]
Message-ID: <1456464655-3684-1-git-send-email-architt@codeaurora.org> (raw)

The clk_rcg_pixel_set_rate clk_op sets up the pre-divider by reading
its current value from the NS register.

Using the pre-divider wasn't really intended when creating these ops.
The pixel RCG was only intended to achieve fractional multiplication
provided in the pixel_table array. Leaving the pre-divider to the
existing register value results in a wrong pixel clock when the
bootloader sets up the display. This was left unidentified because
the IFC6410 Plus board on which this was verified didn't have a
bootloader that configured the display.

Don't set the RCG pre-divider in freq_tbl to the existing NS register
value. Instead, set it based on the fractional multiplication we want.
Prevent using M/N counter when we can just manage with using the
pre-divider.

Cc: John Stultz <john.stultz@linaro.org>
Cc: Vinay Simha <vinaysimha@inforcecomputing.com>
Signed-off-by: Archit Taneja <architt@codeaurora.org>
---
John, Vinay, could you please test this on N7 and confirm if it works?

 drivers/clk/qcom/clk-rcg.c | 10 +++++++---
 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/drivers/clk/qcom/clk-rcg.c b/drivers/clk/qcom/clk-rcg.c
index bfbb28f..2c033f2 100644
--- a/drivers/clk/qcom/clk-rcg.c
+++ b/drivers/clk/qcom/clk-rcg.c
@@ -638,7 +638,6 @@ static int clk_rcg_pixel_set_rate(struct clk_hw *hw, unsigned long rate,
 		return ret;
 
 	src = ns_to_src(&rcg->s, ns);
-	f.pre_div = ns_to_pre_div(&rcg->p, ns) + 1;
 
 	for (i = 0; i < num_parents; i++) {
 		if (src == rcg->s.parent_map[i].cfg) {
@@ -655,8 +654,13 @@ static int clk_rcg_pixel_set_rate(struct clk_hw *hw, unsigned long rate,
 			(parent_rate > (request + delta)))
 			continue;
 
-		f.m = frac->num;
-		f.n = frac->den;
+		/* try to use only the pre-divider if we can */
+		if (frac->num == 1) {
+			f.pre_div = frac->den;
+		} else {
+			f.m = frac->num;
+			f.n = frac->den;
+		}
 
 		return __clk_rcg_set_rate(rcg, &f);
 	}
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation

             reply	other threads:[~2016-02-26  5:31 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-02-26  5:30 Archit Taneja [this message]
2016-02-26 17:44 ` [PATCH] clk: qcom: Fix pre-divider usage for pixel RCG Stephen Boyd
2016-02-28  9:42   ` Archit Taneja
2016-02-26 20:40 ` John Stultz
2016-02-28 10:06   ` Archit Taneja
2016-02-28 10:07 ` [PATCH v2] " Archit Taneja
2016-02-29 19:31   ` John Stultz
2016-02-29 20:57   ` Stephen Boyd

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