From: Stephen Boyd <sboyd@codeaurora.org>
To: Archit Taneja <architt@codeaurora.org>
Cc: linux-arm-msm@vger.kernel.org,
John Stultz <john.stultz@linaro.org>,
Vinay Simha <vinaysimha@inforcecomputing.com>
Subject: Re: [PATCH v2] clk: qcom: Fix pre-divider usage for pixel RCG
Date: Mon, 29 Feb 2016 12:57:15 -0800 [thread overview]
Message-ID: <20160229205715.GF28849@codeaurora.org> (raw)
In-Reply-To: <1456654037-15787-1-git-send-email-architt@codeaurora.org>
On 02/28, Archit Taneja wrote:
> The clk_rcg_pixel_set_rate clk_op sets up the pre-divider by reading
> its current value from the NS register.
>
> Using the pre-divider wasn't really intended when creating these ops.
> The pixel RCG was only intended to achieve fractional multiplication
> provided in the pixel_table array. Leaving the pre-divider to the
> existing register value results in a wrong pixel clock when the
> bootloader sets up the display. This was left unidentified because
> the IFC6410 Plus board on which this was verified didn't have a
> bootloader that configured the display.
>
> Don't set the RCG pre-divider in freq_tbl to the existing NS register
> value. Force it to 1 and only use the M/N counter to achieve the desired
> fractional multiplication.
>
> Cc: John Stultz <john.stultz@linaro.org>
> Cc: Vinay Simha <vinaysimha@inforcecomputing.com>
> Signed-off-by: Archit Taneja <architt@codeaurora.org>
> ---
Applied to clk-next
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
prev parent reply other threads:[~2016-02-29 20:57 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-02-26 5:30 [PATCH] clk: qcom: Fix pre-divider usage for pixel RCG Archit Taneja
2016-02-26 17:44 ` Stephen Boyd
2016-02-28 9:42 ` Archit Taneja
2016-02-26 20:40 ` John Stultz
2016-02-28 10:06 ` Archit Taneja
2016-02-28 10:07 ` [PATCH v2] " Archit Taneja
2016-02-29 19:31 ` John Stultz
2016-02-29 20:57 ` Stephen Boyd [this message]
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