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From: Raphael Poggi <poggi.raph@gmail.com>
To: barebox@lists.infradead.org
Cc: Raphael Poggi <poggi.raph@gmail.com>
Subject: [PATCH v2 08/12] arm: include: system_info: add armv8 identification
Date: Tue, 14 Jun 2016 09:06:42 +0200	[thread overview]
Message-ID: <1465888006-39463-9-git-send-email-poggi.raph@gmail.com> (raw)
In-Reply-To: <1465888006-39463-1-git-send-email-poggi.raph@gmail.com>

Signed-off-by: Raphael Poggi <poggi.raph@gmail.com>
---
 arch/arm/include/asm/system_info.h | 38 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 38 insertions(+)

diff --git a/arch/arm/include/asm/system_info.h b/arch/arm/include/asm/system_info.h
index 0761848..25fffd2 100644
--- a/arch/arm/include/asm/system_info.h
+++ b/arch/arm/include/asm/system_info.h
@@ -13,6 +13,7 @@
 #define CPU_ARCH_ARMv5TEJ	7
 #define CPU_ARCH_ARMv6		8
 #define CPU_ARCH_ARMv7		9
+#define CPU_ARCH_ARMv8		10
 
 #define CPU_IS_ARM720		0x41007200
 #define CPU_IS_ARM720_MASK	0xff00fff0
@@ -41,6 +42,12 @@
 #define CPU_IS_CORTEX_A15	0x410fc0f0
 #define CPU_IS_CORTEX_A15_MASK	0xff0ffff0
 
+#define CPU_IS_CORTEX_A53	0x410fd034
+#define CPU_IS_CORTEX_A53_MASK	0xff0ffff0
+
+#define CPU_IS_CORTEX_A57	0x411fd070
+#define CPU_IS_CORTEX_A57_MASK	0xff0ffff0
+
 #define CPU_IS_PXA250		0x69052100
 #define CPU_IS_PXA250_MASK	0xfffff7f0
 
@@ -112,6 +119,19 @@
 #define cpu_is_cortex_a15() (0)
 #endif
 
+#ifdef CONFIG_CPU_64v8
+#ifdef ARM_ARCH
+#define ARM_MULTIARCH
+#else
+#define ARM_ARCH CPU_ARCH_ARMv8
+#endif
+#define cpu_is_cortex_a53() cpu_is_arm(CORTEX_A53)
+#define cpu_is_cortex_a57() cpu_is_arm(CORTEX_A57)
+#else
+#define cpu_is_cortex_a53() (0)
+#define cpu_is_cortex_a57() (0)
+#endif
+
 #ifndef __ASSEMBLY__
 
 #ifdef ARM_MULTIARCH
@@ -133,6 +153,23 @@ static inline int arm_early_get_cpu_architecture(void)
 		if (cpu_arch)
 			cpu_arch += CPU_ARCH_ARMv3;
 	} else if ((read_cpuid_id() & 0x000f0000) == 0x000f0000) {
+#ifdef CONFIG_CPU_64v8
+		unsigned int isar2;
+
+		__asm__ __volatile__(
+			"mrs	%0, id_isar2_el1\n"
+			: "=r" (isar2)
+			:
+			: "memory");
+
+
+		/* Check Load/Store acquire to check if ARMv8 or not */
+
+		if (isar2 & 0x2)
+			cpu_arch = CPU_ARCH_ARMv8;
+		else
+			cpu_arch = CPU_ARCH_UNKNOWN;
+#else
 		unsigned int mmfr0;
 
 		/* Revised CPUID format. Read the Memory Model Feature
@@ -149,6 +186,7 @@ static inline int arm_early_get_cpu_architecture(void)
 			cpu_arch = CPU_ARCH_UNKNOWN;
 	} else
 		cpu_arch = CPU_ARCH_UNKNOWN;
+#endif
 
 	return cpu_arch;
 }
-- 
2.1.0


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  parent reply	other threads:[~2016-06-14  7:07 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-06-14  7:06 Raphael Poggi
2016-06-14  7:06 ` [PATCH v2 01/12] arm: add armv8 Kconfig entries Raphael Poggi
2016-06-15  6:33   ` Sascha Hauer
2016-06-23 14:43     ` Raphaël Poggi
2016-06-14  7:06 ` [PATCH v2 02/12] arm: Makefile: rework makefile to handle armv8 Raphael Poggi
2016-06-14  7:06 ` [PATCH v2 03/12] arm: introduce lib64 for arm64 related stuff Raphael Poggi
2016-06-15  6:15   ` Sascha Hauer
2016-06-23 14:43     ` Raphaël Poggi
2016-06-14  7:06 ` [PATCH v2 04/12] arm: cpu: add arm64 specific code Raphael Poggi
2016-06-14  7:06 ` [PATCH v2 05/12] arm: include: system: add arm64 helper functions Raphael Poggi
2016-06-14  7:06 ` [PATCH v2 06/12] arm: cpu: start: arm64 does not support relocation Raphael Poggi
2016-06-14  7:06 ` [PATCH v2 07/12] arm: include: bitops: arm64 use generic __fls Raphael Poggi
2016-06-14  7:06 ` Raphael Poggi [this message]
2016-06-14  7:06 ` [PATCH v2 09/12] arm: cpu: cpuinfo: add armv8 support Raphael Poggi
2016-06-14  7:06 ` [PATCH v2 10/12] arm: cpu: disable code portion in armv8 case Raphael Poggi
2016-06-14  7:06 ` [PATCH v2 11/12] arm: cpu: add basic arm64 mmu support Raphael Poggi
2016-06-14  7:06 ` [PATCH v2 12/12] arm: boards: add mach-qemu and virt64 board Raphael Poggi
2016-06-24  8:17 ` Raphaël Poggi
2016-06-24 11:49   ` Re: Sascha Hauer

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