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From: Bibby Hsieh <bibby.hsieh@mediatek.com>
To: Philipp Zabel <p.zabel@pengutronix.de>
Cc: Junzhi Zhao <junzhi.zhao@mediatek.com>,
	linux-kernel@vger.kernel.org,
	Daniel Vetter <daniel.vetter@ffwll.ch>,
	Cawa Cheng <cawa.cheng@mediatek.com>,
	dri-devel@lists.freedesktop.org,
	Mao Huang <littlecvr@chromium.org>,
	linux-mediatek@lists.infradead.org,
	Sascha Hauer <kernel@pengutronix.de>,
	Matthias Brugger <matthias.bgg@gmail.com>,
	Yingjoe Chen <yingjoe.chen@mediatek.com>,
	linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v3 3/3] drm/mediatek: fix the wrong pixel clock when resolution is 4K
Date: Mon, 15 Aug 2016 14:51:16 +0800	[thread overview]
Message-ID: <1471243876.2906.9.camel@mtksdaap41> (raw)
In-Reply-To: <1470899712.2493.16.camel@pengutronix.de>

Hi, Philipp,

On Thu, 2016-08-11 at 09:15 +0200, Philipp Zabel wrote:
> Am Donnerstag, den 04.08.2016, 10:38 +0800 schrieb Bibby Hsieh:
> > From: Junzhi Zhao <junzhi.zhao@mediatek.com>
> > 
> > Pixel clock should be 297MHz when resolution is 4K.
> > 
> > Signed-off-by: Junzhi Zhao <junzhi.zhao@mediatek.com>
> > Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com>
> > ---
> >  drivers/gpu/drm/mediatek/mtk_dpi.c |    8 ++++++--
> >  1 file changed, 6 insertions(+), 2 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c
> > index d05ca79..a90af59 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_dpi.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
> > @@ -438,10 +438,14 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi,
> >  	}
> >  
> >  	pix_rate = 1000UL * mode->clock;
> > -	if (mode->clock <= 74000)
> > +	if (mode->clock <= 27000)
> > +		factor = 16 * 3;
> > +	else if (mode->clock <= 74250)
> >  		factor = 8 * 3;
> > -	else
> > +	else if (mode->clock <= 167000)
> >  		factor = 4 * 3;
> > +	else
> > +		factor = 2 * 3;
> >  	pll_rate = pix_rate * factor;
> >  
> >  	dev_dbg(dpi->dev, "Want PLL %lu Hz, pixel clock %lu Hz\n",
> 
> Could you add a comment why this also changes the 74 MHz limit to 74.25
> MHz and that adds a factor 16*3 for clocks <= 27 MHz ?
> 
Because the valid range of tvdpll is from 1GHz to 2GHz, so, we have to
make the clock to fit that.

> regards
> Philipp
> 

-- 
Bibby

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dri-devel mailing list
dri-devel@lists.freedesktop.org
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WARNING: multiple messages have this Message-ID (diff)
From: bibby.hsieh@mediatek.com (Bibby Hsieh)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v3 3/3] drm/mediatek: fix the wrong pixel clock when resolution is 4K
Date: Mon, 15 Aug 2016 14:51:16 +0800	[thread overview]
Message-ID: <1471243876.2906.9.camel@mtksdaap41> (raw)
In-Reply-To: <1470899712.2493.16.camel@pengutronix.de>

Hi, Philipp,

On Thu, 2016-08-11 at 09:15 +0200, Philipp Zabel wrote:
> Am Donnerstag, den 04.08.2016, 10:38 +0800 schrieb Bibby Hsieh:
> > From: Junzhi Zhao <junzhi.zhao@mediatek.com>
> > 
> > Pixel clock should be 297MHz when resolution is 4K.
> > 
> > Signed-off-by: Junzhi Zhao <junzhi.zhao@mediatek.com>
> > Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com>
> > ---
> >  drivers/gpu/drm/mediatek/mtk_dpi.c |    8 ++++++--
> >  1 file changed, 6 insertions(+), 2 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c
> > index d05ca79..a90af59 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_dpi.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
> > @@ -438,10 +438,14 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi,
> >  	}
> >  
> >  	pix_rate = 1000UL * mode->clock;
> > -	if (mode->clock <= 74000)
> > +	if (mode->clock <= 27000)
> > +		factor = 16 * 3;
> > +	else if (mode->clock <= 74250)
> >  		factor = 8 * 3;
> > -	else
> > +	else if (mode->clock <= 167000)
> >  		factor = 4 * 3;
> > +	else
> > +		factor = 2 * 3;
> >  	pll_rate = pix_rate * factor;
> >  
> >  	dev_dbg(dpi->dev, "Want PLL %lu Hz, pixel clock %lu Hz\n",
> 
> Could you add a comment why this also changes the 74 MHz limit to 74.25
> MHz and that adds a factor 16*3 for clocks <= 27 MHz ?
> 
Because the valid range of tvdpll is from 1GHz to 2GHz, so, we have to
make the clock to fit that.

> regards
> Philipp
> 

-- 
Bibby

WARNING: multiple messages have this Message-ID (diff)
From: Bibby Hsieh <bibby.hsieh@mediatek.com>
To: Philipp Zabel <p.zabel@pengutronix.de>
Cc: David Airlie <airlied@linux.ie>,
	Matthias Brugger <matthias.bgg@gmail.com>,
	Daniel Vetter <daniel.vetter@ffwll.ch>,
	<dri-devel@lists.freedesktop.org>,
	<linux-mediatek@lists.infradead.org>,
	Yingjoe Chen <yingjoe.chen@mediatek.com>,
	Cawa Cheng <cawa.cheng@mediatek.com>,
	Daniel Kurtz <djkurtz@chromium.org>,
	YT Shen <yt.shen@mediatek.com>,
	Thierry Reding <thierry.reding@gmail.com>,
	CK Hu <ck.hu@mediatek.com>, Mao Huang <littlecvr@chromium.org>,
	<linux-arm-kernel@lists.infradead.org>,
	<linux-kernel@vger.kernel.org>,
	"Sascha Hauer" <kernel@pengutronix.de>,
	Junzhi Zhao <junzhi.zhao@mediatek.com>
Subject: Re: [PATCH v3 3/3] drm/mediatek: fix the wrong pixel clock when resolution is 4K
Date: Mon, 15 Aug 2016 14:51:16 +0800	[thread overview]
Message-ID: <1471243876.2906.9.camel@mtksdaap41> (raw)
In-Reply-To: <1470899712.2493.16.camel@pengutronix.de>

Hi, Philipp,

On Thu, 2016-08-11 at 09:15 +0200, Philipp Zabel wrote:
> Am Donnerstag, den 04.08.2016, 10:38 +0800 schrieb Bibby Hsieh:
> > From: Junzhi Zhao <junzhi.zhao@mediatek.com>
> > 
> > Pixel clock should be 297MHz when resolution is 4K.
> > 
> > Signed-off-by: Junzhi Zhao <junzhi.zhao@mediatek.com>
> > Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com>
> > ---
> >  drivers/gpu/drm/mediatek/mtk_dpi.c |    8 ++++++--
> >  1 file changed, 6 insertions(+), 2 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c
> > index d05ca79..a90af59 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_dpi.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
> > @@ -438,10 +438,14 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi,
> >  	}
> >  
> >  	pix_rate = 1000UL * mode->clock;
> > -	if (mode->clock <= 74000)
> > +	if (mode->clock <= 27000)
> > +		factor = 16 * 3;
> > +	else if (mode->clock <= 74250)
> >  		factor = 8 * 3;
> > -	else
> > +	else if (mode->clock <= 167000)
> >  		factor = 4 * 3;
> > +	else
> > +		factor = 2 * 3;
> >  	pll_rate = pix_rate * factor;
> >  
> >  	dev_dbg(dpi->dev, "Want PLL %lu Hz, pixel clock %lu Hz\n",
> 
> Could you add a comment why this also changes the 74 MHz limit to 74.25
> MHz and that adds a factor 16*3 for clocks <= 27 MHz ?
> 
Because the valid range of tvdpll is from 1GHz to 2GHz, so, we have to
make the clock to fit that.

> regards
> Philipp
> 

-- 
Bibby

  reply	other threads:[~2016-08-15  6:51 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-08-04  2:38 [PATCH v3 0/3] MT8173 HDMI 4K support Bibby Hsieh
2016-08-04  2:38 ` Bibby Hsieh
2016-08-04  2:38 ` Bibby Hsieh
2016-08-04  2:38 ` [PATCH v3 1/3] drm/mediatek: do mtk_hdmi_send_infoframe after HDMI clock enable Bibby Hsieh
2016-08-04  2:38   ` Bibby Hsieh
2016-08-04  2:38   ` Bibby Hsieh
2016-08-04  2:38 ` [PATCH v3 2/3] drm/mediatek: enhance the HDMI driving current Bibby Hsieh
2016-08-04  2:38   ` Bibby Hsieh
2016-08-04  2:38   ` Bibby Hsieh
2016-08-04  2:38 ` [PATCH v3 3/3] drm/mediatek: fix the wrong pixel clock when resolution is 4K Bibby Hsieh
2016-08-04  2:38   ` Bibby Hsieh
2016-08-04  2:38   ` Bibby Hsieh
2016-08-11  7:15   ` Philipp Zabel
2016-08-11  7:15     ` Philipp Zabel
2016-08-11  7:15     ` Philipp Zabel
2016-08-15  6:51     ` Bibby Hsieh [this message]
2016-08-15  6:51       ` Bibby Hsieh
2016-08-15  6:51       ` Bibby Hsieh

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