From: Ritesh Harjani <riteshh@codeaurora.org>
To: adrian.hunter@intel.com
Cc: ulf.hansson@linaro.org, linux-mmc@vger.kernel.org,
shawn.lin@rock-chips.com, linux-arm-msm@vger.kernel.org,
georgi.djakov@linaro.org, alex.lemberg@sandisk.com,
mateusz.nowak@intel.com, Yuliy.Izrailov@sandisk.com,
asutoshd@codeaurora.org, david.griego@linaro.org,
stummala@codeaurora.org, venkatg@codeaurora.org,
pramod.gurav@linaro.org, bjorn.andersson@linaro.org,
Ritesh Harjani <riteshh@codeaurora.org>
Subject: [PATCH v4 6/9] mmc: sdhci-msm: Enable few quirks
Date: Wed, 24 Aug 2016 15:33:41 +0530 [thread overview]
Message-ID: <1472033024-14890-7-git-send-email-riteshh@codeaurora.org> (raw)
In-Reply-To: <1472033024-14890-1-git-send-email-riteshh@codeaurora.org>
sdhc-msm controller needs this SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN
& SDHCI_QUIRK2_PRESET_VALUE_BROKEN to be set. Hence setting it.
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
Signed-off-by: Ritesh Harjani <riteshh@codeaurora.org>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
---
drivers/mmc/host/sdhci-msm.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c
index 244e67a..a6280aa 100644
--- a/drivers/mmc/host/sdhci-msm.c
+++ b/drivers/mmc/host/sdhci-msm.c
@@ -603,7 +603,9 @@ static const struct sdhci_ops sdhci_msm_ops = {
static const struct sdhci_pltfm_data sdhci_msm_pdata = {
.quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION |
SDHCI_QUIRK_NO_CARD_NO_RESET |
- SDHCI_QUIRK_SINGLE_POWER_WRITE,
+ SDHCI_QUIRK_SINGLE_POWER_WRITE |
+ SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
+ .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
.ops = &sdhci_msm_ops,
};
--
The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project.
next prev parent reply other threads:[~2016-08-24 10:03 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-08-24 10:03 [PATCH v4 0/9] mmc: sdhci-msm: Add clk-rates and DDR support Ritesh Harjani
2016-08-24 10:03 ` [PATCH v4 1/9] mmc: sdhci-msm: Change poor style writel/readl of registers Ritesh Harjani
2016-08-24 10:03 ` [PATCH v4 2/9] mmc: sdhci-msm: Update DLL reset sequence Ritesh Harjani
2016-08-24 10:03 ` [PATCH v4 3/9] mmc: sdhci-msm: add pltfm_data support to get clk-rates from DT Ritesh Harjani
2016-08-25 22:27 ` Stephen Boyd
2016-08-30 14:12 ` Ritesh Harjani
[not found] ` <1a44bb54-d88c-737d-7fb1-e7c3597ac03b-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2016-09-07 16:14 ` Stephen Boyd
2016-09-12 6:17 ` Ritesh Harjani
2016-10-04 9:33 ` Ritesh Harjani
2016-09-12 7:33 ` Arnd Bergmann
2016-09-27 5:06 ` Ritesh Harjani
2016-08-24 10:03 ` [PATCH v4 4/9] ARM: dts: qcom: Add clk-rates to sdhc1 & sdhc2 Ritesh Harjani
2016-08-24 10:03 ` [PATCH v4 5/9] mmc: sdhci-msm: Add get_min_clock() and get_max_clock() callback Ritesh Harjani
2016-08-24 10:03 ` Ritesh Harjani [this message]
2016-08-24 10:03 ` [PATCH v4 7/9] mmc: sdhci-msm: Implement set_clock callback for sdhci-msm Ritesh Harjani
2016-08-24 10:03 ` [PATCH v4 8/9] mmc: sdhci-msm: Add clock changes for DDR mode Ritesh Harjani
2016-08-29 13:17 ` Adrian Hunter
2016-08-30 14:16 ` Ritesh Harjani
2016-08-24 10:03 ` [PATCH v4 9/9] arm64: dts: qcom: msm8916: Add ddr support to sdhc1 Ritesh Harjani
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