Re: [Qemu-devel] [PATCH RFC 4/4] target-ppc: flush tlb from all the cpu

[Benjamin Herrenschmidt <benh@kernel.crashing.org>]

On Sun, 2016-09-04 at 18:00 +0100, Alex Bennée wrote:
> > 
> > > We must provide a guarantee that no other processor can see the old
> > > translation when the tlb invalidation sequence completes. With the
> > > current lazy TLB flush, we already delay the invalidation until
> > > we hit that synchronization point so we need to be synchronous.
> 
> When is the synchronisation point? On ARM we end the basic block on
> system instructions that mess with the cache. As a result the flush is
> done as soon as we exit the run loop on the next instruction.

Look for gen_check_tlb_flush() in translated code and check_tlb_flush
elsewhere in target-ppc.

Basically, when we hit tlbie or slbie (TLB or segment invalidation
instruction), we just set a flag indicating that the TLB "needs
flushing".

When we hit an execution synchronizing instruction (isync) or a
ptesync, or if we hit an exception, we do the actual flush.

This isn't 100% architecturally correct but work with every OS out there
and saves quite a bit of churn, especially on context switch when we
invalidate/replae multiple segments or when invalidating range of pages.

In any case, ptesync especially needs to be the hard sync point, past that
point all translation must have been gone and all accesses using the previous
transltion completed or retried on all processors.

Another approach would be to shoot asynchronous event on the actual tlbie/
slbie instructions and synchronize at the end, but I suspect it won't be
any better, especially since the current code structure can't do fine grained
invalidation of the qemu TLB anyway, we can only blow it all up.

So better safe than sorry here.

That being said, your statement about basic block confuses me a bit. You
mean MT TCG will sync all the threads when exiting a basic block on any CPU ?
 
Cheers,
Ben.

> > 
> > 
> > 
> > > 
> > > > 
> > > > diff --git a/target-ppc/mmu-hash64.c b/target-ppc/mmu-hash64.c
> > > > index 8118143..d852c21 100644
> > > > --- a/target-ppc/mmu-hash64.c
> > > > +++ b/target-ppc/mmu-hash64.c
> > > > @@ -912,7 +912,7 @@ void ppc_hash64_tlb_flush_hpte(PowerPCCPU *cpu,
> > > > * invalidate, and we still don't have a tlb_flush_mask(env, n,
> > > > * mask) in QEMU, we just invalidate all TLBs
> > > > */
> > > > -tlb_flush(CPU(cpu), 1);
> > > > +tlb_flush_all(CPU(cpu), 1);
> > > > }
> > > > 
> > > > void ppc_hash64_update_rmls(CPUPPCState *env)
> > 
> > Regards,
> > Nikunj
> 
> 
> --
> Alex Bennée