From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
To: "Nikunj A Dadhania" <nikunj@linux.vnet.ibm.com>,
"Alex Bennée" <alex.bennee@linaro.org>
Cc: qemu-ppc@nongnu.org, david@gibson.dropbear.id.au,
rth@twiddle.net, qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] [PATCH RFC 4/4] target-ppc: flush tlb from all the cpu
Date: Tue, 06 Sep 2016 13:05:07 +1000 [thread overview]
Message-ID: <1473131107.2313.53.camel@kernel.crashing.org> (raw)
In-Reply-To: <878tv5lrkl.fsf@abhimanyu.i-did-not-set--mail-host-address--so-tickle-me>
On Tue, 2016-09-06 at 07:25 +0530, Nikunj A Dadhania wrote:
> > Benjamin Herrenschmidt <benh@kernel.crashing.org> writes:
>
> >
> > On Sun, 2016-09-04 at 18:00 +0100, Alex Bennée wrote:
> >
> > >
> > > When is the synchronisation point? On ARM we end the basic block on
> > > system instructions that mess with the cache. As a result the flush
> > > is done as soon as we exit the run loop on the next instruction.
> >
> > Talking o this... Nikunj, I notice, all our TLB flushing is only ever
> > done on the "current" CPU. I mean today, without MT-TCG. That looks
> > broken already isn't it ?
>
> Without MT-TCG, there was only one cpu, so I think we never hit that
> issue.
No there isn't. You can start qemu with --smp 4 and have 4 CPUs. It
will alternate between them, but they *will* have differrent TLBs.
next prev parent reply other threads:[~2016-09-06 3:05 UTC|newest]
Thread overview: 45+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-09-02 6:32 [Qemu-devel] [PATCH RFC 0/4] Enable MTTCG on PowerPC Nikunj A Dadhania
2016-09-02 6:32 ` [Qemu-devel] [PATCH RFC 1/4] spapr-hcall: take iothread lock during handler call Nikunj A Dadhania
2016-09-02 8:53 ` Greg Kurz
2016-09-02 9:28 ` Nikunj A Dadhania
2016-09-02 9:57 ` Greg Kurz
2016-09-03 16:31 ` Nikunj A Dadhania
2016-09-02 10:06 ` Thomas Huth
2016-09-03 16:33 ` Nikunj A Dadhania
2016-09-02 6:32 ` [Qemu-devel] [PATCH RFC 2/4] target-ppc: with MTTCG report more threads Nikunj A Dadhania
2016-09-02 9:28 ` Greg Kurz
2016-09-02 9:34 ` Nikunj A Dadhania
2016-09-02 10:45 ` Greg Kurz
2016-09-03 16:34 ` Nikunj A Dadhania
2016-09-07 3:51 ` David Gibson
2016-09-07 4:41 ` Nikunj A Dadhania
2016-09-02 6:32 ` [Qemu-devel] [PATCH RFC 3/4] target-ppc: use atomic_cmpxchg for ld/st reservation Nikunj A Dadhania
2016-09-07 4:02 ` David Gibson
2016-09-07 4:47 ` Nikunj A Dadhania
2016-09-07 5:24 ` Benjamin Herrenschmidt
2016-09-07 8:42 ` Nikunj A Dadhania
2016-09-07 5:34 ` David Gibson
2016-09-07 7:13 ` Alex Bennée
2016-09-12 1:19 ` David Gibson
2016-09-12 8:39 ` Alex Bennée
2016-09-12 9:15 ` Benjamin Herrenschmidt
2016-09-02 6:32 ` [Qemu-devel] [PATCH RFC 4/4] target-ppc: flush tlb from all the cpu Nikunj A Dadhania
2016-09-02 7:22 ` Benjamin Herrenschmidt
2016-09-02 7:34 ` Nikunj A Dadhania
2016-09-04 17:00 ` Alex Bennée
2016-09-04 22:17 ` Benjamin Herrenschmidt
2016-09-05 0:10 ` Benjamin Herrenschmidt
2016-09-06 1:55 ` Nikunj A Dadhania
2016-09-06 3:05 ` Benjamin Herrenschmidt [this message]
2016-09-06 4:53 ` Nikunj A Dadhania
2016-09-06 5:30 ` Benjamin Herrenschmidt
2016-09-06 6:57 ` Nikunj A Dadhania
2016-09-02 6:43 ` [Qemu-devel] [PATCH RFC 0/4] Enable MTTCG on PowerPC Cédric Le Goater
2016-09-02 6:46 ` Nikunj A Dadhania
2016-09-02 7:57 ` Thomas Huth
2016-09-02 11:44 ` Cédric Le Goater
2016-09-02 7:19 ` Benjamin Herrenschmidt
2016-09-02 7:39 ` Nikunj A Dadhania
2016-09-02 12:13 ` Benjamin Herrenschmidt
2016-09-07 4:08 ` David Gibson
2016-09-07 4:48 ` Nikunj A Dadhania
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