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From: Paulo Zanoni <paulo.r.zanoni@intel.com>
To: Matt Roper <matthew.d.roper@intel.com>
Cc: intel-gfx@lists.freedesktop.org, stable@vger.kernel.org
Subject: Re: [PATCH] drm/i915/gen9: fix the WM memory bandwidth WA for Y tiling cases
Date: Mon, 14 Nov 2016 18:03:58 -0200	[thread overview]
Message-ID: <1479153838.2400.12.camel@intel.com> (raw)
In-Reply-To: <20161109013809.GG6536@intel.com>

Em Ter, 2016-11-08 às 17:38 -0800, Matt Roper escreveu:
> On Tue, Nov 08, 2016 at 06:22:11PM -0200, Paulo Zanoni wrote:
> > 
> > The previous spec version said "double Ytile planes minimum lines",
> > and I interpreted this as referring to what the spec calls "Y tile
> > minimum", but in fact it was referring to what the spec calls
> > "Minimum
> > Scanlines for Y tile". I noticed that Mahesh Kumar had a different
> > interpretation, so I sent and email to the spec authors and got
> > clarification on the correct meaning. Also, BSpec was updated and
> > should be clear now.
> > 
> > Fixes: ee3d532fcb64 ("drm/i915/gen9: unconditionally apply the
> > memory bandwidth WA")
> > Cc: stable@vger.kernel.org
> > Cc: Mahesh Kumar <mahesh1.kumar@intel.com>
> > Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> 
> This seems to match my reading of the spec update from Nov 4th, so:
> 
> Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

Patch merged today. Thanks for the review!

> 
> 
> > 
> > ---
> >  drivers/gpu/drm/i915/intel_pm.c | 5 +++--
> >  1 file changed, 3 insertions(+), 2 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c
> > b/drivers/gpu/drm/i915/intel_pm.c
> > index cc9e0c0..653525f 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -3624,6 +3624,9 @@ static int skl_compute_plane_wm(const struct
> > drm_i915_private *dev_priv,
> >  		y_min_scanlines = 4;
> >  	}
> >  
> > +	if (apply_memory_bw_wa)
> > +		y_min_scanlines *= 2;
> > +
> >  	plane_bytes_per_line = width * cpp;
> >  	if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
> >  	    fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) {
> > @@ -3644,8 +3647,6 @@ static int skl_compute_plane_wm(const struct
> > drm_i915_private *dev_priv,
> >  				 plane_blocks_per_line);
> >  
> >  	y_tile_minimum = plane_blocks_per_line * y_min_scanlines;
> > -	if (apply_memory_bw_wa)
> > -		y_tile_minimum *= 2;
> >  
> >  	if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
> >  	    fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) {
> > -- 
> > 2.7.4
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

WARNING: multiple messages have this Message-ID (diff)
From: Paulo Zanoni <paulo.r.zanoni@intel.com>
To: Matt Roper <matthew.d.roper@intel.com>
Cc: intel-gfx@lists.freedesktop.org, stable@vger.kernel.org
Subject: Re: [Intel-gfx] [PATCH] drm/i915/gen9: fix the WM memory bandwidth WA for Y tiling cases
Date: Mon, 14 Nov 2016 18:03:58 -0200	[thread overview]
Message-ID: <1479153838.2400.12.camel@intel.com> (raw)
In-Reply-To: <20161109013809.GG6536@intel.com>

Em Ter, 2016-11-08 às 17:38 -0800, Matt Roper escreveu:
> On Tue, Nov 08, 2016 at 06:22:11PM -0200, Paulo Zanoni wrote:
> > 
> > The previous spec version said "double Ytile planes minimum lines",
> > and I interpreted this as referring to what the spec calls "Y tile
> > minimum", but in fact it was referring to what the spec calls
> > "Minimum
> > Scanlines for Y tile". I noticed that Mahesh Kumar had a different
> > interpretation, so I sent and email to the spec authors and got
> > clarification on the correct meaning. Also, BSpec was updated and
> > should be clear now.
> > 
> > Fixes: ee3d532fcb64 ("drm/i915/gen9: unconditionally apply the
> > memory bandwidth WA")
> > Cc: stable@vger.kernel.org
> > Cc: Mahesh Kumar <mahesh1.kumar@intel.com>
> > Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> 
> This seems to match my reading of the spec update from Nov 4th, so:
> 
> Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

Patch merged today. Thanks for the review!

> 
> 
> > 
> > ---
> >  drivers/gpu/drm/i915/intel_pm.c | 5 +++--
> >  1 file changed, 3 insertions(+), 2 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c
> > b/drivers/gpu/drm/i915/intel_pm.c
> > index cc9e0c0..653525f 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -3624,6 +3624,9 @@ static int skl_compute_plane_wm(const struct
> > drm_i915_private *dev_priv,
> >  		y_min_scanlines = 4;
> >  	}
> >  
> > +	if (apply_memory_bw_wa)
> > +		y_min_scanlines *= 2;
> > +
> >  	plane_bytes_per_line = width * cpp;
> >  	if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
> >  	    fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) {
> > @@ -3644,8 +3647,6 @@ static int skl_compute_plane_wm(const struct
> > drm_i915_private *dev_priv,
> >  				 plane_blocks_per_line);
> >  
> >  	y_tile_minimum = plane_blocks_per_line * y_min_scanlines;
> > -	if (apply_memory_bw_wa)
> > -		y_tile_minimum *= 2;
> >  
> >  	if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
> >  	    fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) {
> > -- 
> > 2.7.4
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 

  reply	other threads:[~2016-11-14 20:04 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-11-08 20:22 [PATCH] drm/i915/gen9: fix the WM memory bandwidth WA for Y tiling cases Paulo Zanoni
2016-11-08 20:22 ` Paulo Zanoni
2016-11-08 20:46 ` ✓ Fi.CI.BAT: success for " Patchwork
2016-11-09  1:38 ` [Intel-gfx] [PATCH] " Matt Roper
2016-11-14 20:03   ` Paulo Zanoni [this message]
2016-11-14 20:03     ` Paulo Zanoni

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