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From: Stafford Horne <shorne@gmail.com>
To: openrisc@lists.librecores.org
Subject: [OpenRISC] [PATCH 15/18] sim: or1k: Implement register store/fetch
Date: Thu, 24 Nov 2016 07:14:29 +0900	[thread overview]
Message-ID: <1479939272-1754-16-git-send-email-shorne@gmail.com> (raw)
In-Reply-To: <1479939272-1754-1-git-send-email-shorne@gmail.com>

There was a comment questioning the use of these. But as soon
as I run any basic test gdb complains that these are not implemented.

More tests and basic run and execute work now.
---
 sim/or1k/or1k-sim.h |  2 +-
 sim/or1k/or1k.c     | 31 ++++++++++++++++++++++++++++---
 2 files changed, 29 insertions(+), 4 deletions(-)

diff --git a/sim/or1k/or1k-sim.h b/sim/or1k/or1k-sim.h
index 9e1754f..7213caa 100644
--- a/sim/or1k/or1k-sim.h
+++ b/sim/or1k/or1k-sim.h
@@ -4,7 +4,7 @@
 #include "symcat.h"
 
 /* GDB register numbers. */
-#define PC_REGNUM	16
+#define PC_REGNUM	33
 
 /* Misc. profile data.  */
 typedef struct {
diff --git a/sim/or1k/or1k.c b/sim/or1k/or1k.c
index 98225ab..565a018 100644
--- a/sim/or1k/or1k.c
+++ b/sim/or1k/or1k.c
@@ -9,27 +9,52 @@
 #include "sim-main.h"
 #include "symcat.h"
 #include "cgen-ops.h"
+#include "cgen-mem.h"
+#include "cpuall.h"
 
 #include <string.h>
 
-/* not sure what the point of these is */
 int XCONCAT2(WANT_CPU,_fetch_register) (sim_cpu *current_cpu, int rn, unsigned char *buf, int len)
 {
-  return -1;
+   if (rn < 32)
+    SETTWI (buf, XCONCAT2(WANT_CPU,_h_gpr_get) (current_cpu, rn));
+  else
+    switch (rn)
+      {
+      case PC_REGNUM :
+        SETTWI (buf, XCONCAT2(WANT_CPU,_h_pc_get) (current_cpu));
+        break;
+      default :
+         return 0;
+      }
+  return sizeof(WI); /* WI from arch.h */
 }
 
 int XCONCAT2(WANT_CPU,_store_register) (sim_cpu *current_cpu, int rn, unsigned char *buf, int len)
 {
-  return -1;
+  if (rn < 32)
+    XCONCAT2(WANT_CPU,_h_gpr_set) (current_cpu, rn, GETTWI (buf));
+  else
+    switch (rn)
+      {
+      case PC_REGNUM :
+        XCONCAT2(WANT_CPU,_h_pc_set) (current_cpu, GETTWI (buf));
+        break;
+      default :
+         return 0;
+      }
+  return sizeof(WI); /* WI from arch.h */
 }
 
 #ifdef WANT_CPU_OR1K32BF
 int or1k32bf_model_or1200_u_exec (sim_cpu * UNUSED current_cpu, const IDESC * UNUSED idesc, int unit_num, int referenced)
 {
+  return -1;
 }
 
 int or1k32bf_model_or1200nd_u_exec (sim_cpu * UNUSED current_cpu, const IDESC * UNUSED idesc, int unit_num, int referenced)
 {
+  return -1;
 }
 
 void or1k32bf_model_insn_before (sim_cpu * UNUSED current_cpu, int UNUSED first_p)
-- 
2.7.4



  parent reply	other threads:[~2016-11-23 22:14 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-11-23 22:14 [OpenRISC] [PATCH 00/18] sim: port for OpenRISC Stafford Horne
2016-11-23 22:14 ` [OpenRISC] [PATCH 01/18] sim: cgen: add rem (remainder) function (needed for OR1K lf.rem.[sd]) Stafford Horne
2016-11-23 22:14 ` [OpenRISC] [PATCH 02/18] sim: cgen: add mul-o1flag, mul-o2flag RTL functions to CGEN Stafford Horne
2016-11-23 22:14 ` [OpenRISC] [PATCH 03/18] sim: cgen: allow suffix on generated arch.[ch] and cpuall.h Stafford Horne
2016-11-23 22:14 ` [OpenRISC] [PATCH 04/18] sim: or1k: add or1k target to sim Stafford Horne
2016-11-23 22:14 ` [OpenRISC] [PATCH 05/18] sim: or1k: add NOP_EXIT_SILENT; make simulator print exit code for NOP_EXIT; Stafford Horne
2016-11-23 22:14 ` [OpenRISC] [PATCH 06/18] sim: or1k: fix branching and exceptions in sim Stafford Horne
2016-11-23 22:14 ` [OpenRISC] [PATCH 07/18] sim: or1k: remove erroneous warning message in sim/or1k/or1k.c Stafford Horne
2016-11-23 22:14 ` [OpenRISC] [PATCH 08/18] sim: or1k: fix fl1 in sim Stafford Horne
2016-11-23 22:14 ` [OpenRISC] [PATCH 09/18] sim: or1k: regenerate sim files Stafford Horne
2016-11-23 22:14 ` [OpenRISC] [PATCH 10/18] sim: testsuite: add testsuite for or1k sim Stafford Horne
2016-11-23 22:14 ` [OpenRISC] [PATCH 11/18] sim: or1k: fix segfault when run without arguments Stafford Horne
2016-11-23 22:14 ` [OpenRISC] [PATCH 12/18] sim: or1k: Get or1k sim building with latest sim common Stafford Horne
2016-11-23 22:14 ` [OpenRISC] [PATCH 13/18] sim: or1k: Regenerate cgen files Stafford Horne
2016-11-23 22:14 ` [OpenRISC] [PATCH 14/18] sim: or1k: Regenerate autotool files Stafford Horne
2016-11-23 22:14 ` Stafford Horne [this message]
2016-11-23 22:14 ` [OpenRISC] [PATCH 16/18] sim: or1k: Do trap breakpoint handling Stafford Horne
2016-11-23 22:14 ` [OpenRISC] [PATCH 17/18] sim: or1k: Implement fetch/store for ppc and sr Stafford Horne
2016-11-23 22:14 ` [OpenRISC] [PATCH 18/18] sim: or1k: add additional stubs for linux build Stafford Horne
2016-11-23 23:04 ` [OpenRISC] [PATCH 00/18] sim: port for OpenRISC Stafford Horne
2016-11-25 16:19 ` Mike Frysinger
2016-11-25 22:46   ` Stafford Horne
2016-12-05  8:40     ` Stafford Horne
2016-12-16 20:34       ` Mike Frysinger
2016-12-17  4:18         ` Stafford Horne
2016-12-18  4:33           ` Mike Frysinger

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