From: York Sun <york.sun@nxp.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 03/24] powerpc: mpc85xx: Move CONFIG_SYS_PPC_E500_DEBUG_TLB to Kconfig
Date: Wed, 28 Dec 2016 08:43:29 -0800 [thread overview]
Message-ID: <1482943430-10231-4-git-send-email-york.sun@nxp.com> (raw)
In-Reply-To: <1482943430-10231-1-git-send-email-york.sun@nxp.com>
Use Kconfig SYS_PPC_E500_DEBUG_TLB and clean up existing macros.
Signed-off-by: York Sun <york.sun@nxp.com>
---
README | 9 -------
arch/powerpc/cpu/mpc85xx/Kconfig | 40 +++++++++++++++++++++++++++++++
arch/powerpc/include/asm/config_mpc85xx.h | 14 -----------
scripts/config_whitelist.txt | 1 -
4 files changed, 40 insertions(+), 24 deletions(-)
diff --git a/README b/README
index 25cad2f..f6d3781 100644
--- a/README
+++ b/README
@@ -376,15 +376,6 @@ The following options need to be configured:
Defines the string to utilize when trying to match PCIe device
tree nodes for the given platform.
- CONFIG_SYS_PPC_E500_DEBUG_TLB
-
- Enables a temporary TLB entry to be used during boot to work
- around limitations in e500v1 and e500v2 external debugger
- support. This reduces the portions of the boot code where
- breakpoints and single stepping do not work. The value of this
- symbol should be set to the TLB1 entry to be used for this
- purpose.
-
CONFIG_SYS_FSL_ERRATUM_A004510
Enables a workaround for erratum A004510. If set,
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index 2b1d0f6..7f04a09 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -338,14 +338,17 @@ config ARCH_BSC9131
config ARCH_BSC9132
bool
select FSL_LAW
+ select SYS_PPC_E500_USE_DEBUG_TLB
config ARCH_C29X
bool
select FSL_LAW
+ select SYS_PPC_E500_USE_DEBUG_TLB
config ARCH_MPC8536
bool
select FSL_LAW
+ select SYS_PPC_E500_USE_DEBUG_TLB
config ARCH_MPC8540
bool
@@ -358,10 +361,12 @@ config ARCH_MPC8541
config ARCH_MPC8544
bool
select FSL_LAW
+ select SYS_PPC_E500_USE_DEBUG_TLB
config ARCH_MPC8548
bool
select FSL_LAW
+ select SYS_PPC_E500_USE_DEBUG_TLB
config ARCH_MPC8555
bool
@@ -386,22 +391,27 @@ config ARCH_MPC8572
config ARCH_P1010
bool
select FSL_LAW
+ select SYS_PPC_E500_USE_DEBUG_TLB
config ARCH_P1011
bool
select FSL_LAW
+ select SYS_PPC_E500_USE_DEBUG_TLB
config ARCH_P1020
bool
select FSL_LAW
+ select SYS_PPC_E500_USE_DEBUG_TLB
config ARCH_P1021
bool
select FSL_LAW
+ select SYS_PPC_E500_USE_DEBUG_TLB
config ARCH_P1022
bool
select FSL_LAW
+ select SYS_PPC_E500_USE_DEBUG_TLB
config ARCH_P1023
bool
@@ -410,14 +420,17 @@ config ARCH_P1023
config ARCH_P1024
bool
select FSL_LAW
+ select SYS_PPC_E500_USE_DEBUG_TLB
config ARCH_P1025
bool
select FSL_LAW
+ select SYS_PPC_E500_USE_DEBUG_TLB
config ARCH_P2020
bool
select FSL_LAW
+ select SYS_PPC_E500_USE_DEBUG_TLB
config ARCH_P2041
bool
@@ -655,6 +668,33 @@ config SYS_NUM_TLBCAMS
Number of TLB CAM entries for Book-E chips. 64 for E500MC,
16 for other E500 SoCs.
+config SYS_PPC_E500_USE_DEBUG_TLB
+ bool
+
+config SYS_PPC_E500_DEBUG_TLB
+ int "Temporary TLB entry for external debugger"
+ depends on SYS_PPC_E500_USE_DEBUG_TLB
+ default 0 if ARCH_MPC8544 || ARCH_MPC8548
+ default 1 if ARCH_MPC8536
+ default 2 if ARCH_MPC8572 || \
+ ARCH_P1011 || \
+ ARCH_P1020 || \
+ ARCH_P1021 || \
+ ARCH_P1022 || \
+ ARCH_P1024 || \
+ ARCH_P1025 || \
+ ARCH_P2020
+ default 3 if ARCH_P1010 || \
+ ARCH_BSC9132 || \
+ ARCH_C29X
+ help
+ Select a temporary TLB entry to be used during boot to work
+ around limitations in e500v1 and e500v2 external debugger
+ support. This reduces the portions of the boot code where
+ breakpoints and single stepping do not work. The value of this
+ symbol should be set to the TLB1 entry to be used for this
+ purpose. If unsure, do not change.
+
source "board/freescale/b4860qds/Kconfig"
source "board/freescale/bsc9131rdb/Kconfig"
source "board/freescale/bsc9132qds/Kconfig"
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index 5761218..cbaba36 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -25,7 +25,6 @@
#define CONFIG_SYS_FSL_SEC_MON_BE
#if defined(CONFIG_ARCH_MPC8536)
-#define CONFIG_SYS_PPC_E500_DEBUG_TLB 1
#define CONFIG_SYS_FSL_SEC_COMPAT 2
#define CONFIG_SYS_FSL_ERRATUM_A004508
#define CONFIG_SYS_FSL_ERRATUM_A005125
@@ -39,13 +38,11 @@
#elif defined(CONFIG_ARCH_MPC8544)
#define CONFIG_SYS_FSL_DDRC_GEN2
-#define CONFIG_SYS_PPC_E500_DEBUG_TLB 0
#define CONFIG_SYS_FSL_SEC_COMPAT 2
#define CONFIG_SYS_FSL_ERRATUM_A005125
#elif defined(CONFIG_ARCH_MPC8548)
#define CONFIG_SYS_FSL_DDRC_GEN2
-#define CONFIG_SYS_PPC_E500_DEBUG_TLB 0
#define CONFIG_SYS_FSL_SEC_COMPAT 2
#define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
#define CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
@@ -92,7 +89,6 @@
#define CONFIG_SYS_FSL_ERRATUM_A005125
#elif defined(CONFIG_ARCH_MPC8572)
-#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
#define CONFIG_SYS_FSL_SEC_COMPAT 2
#define CONFIG_SYS_FSL_ERRATUM_DDR_115
#define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
@@ -101,7 +97,6 @@
#elif defined(CONFIG_ARCH_P1010)
#define CONFIG_FSL_SDHC_V2_3
-#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
#define CONFIG_TSECV2
#define CONFIG_SYS_FSL_SEC_COMPAT 4
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
@@ -126,7 +121,6 @@
/* P1011 is single core version of P1020 */
#elif defined(CONFIG_ARCH_P1011)
-#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
#define CONFIG_TSECV2
#define CONFIG_FSL_PCIE_DISABLE_ASPM
#define CONFIG_SYS_FSL_SEC_COMPAT 2
@@ -137,7 +131,6 @@
#define CONFIG_SYS_FSL_ERRATUM_A005125
#elif defined(CONFIG_ARCH_P1020)
-#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
#define CONFIG_TSECV2
#define CONFIG_FSL_PCIE_DISABLE_ASPM
#define CONFIG_SYS_FSL_SEC_COMPAT 2
@@ -150,7 +143,6 @@
#endif
#elif defined(CONFIG_ARCH_P1021)
-#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
#define CONFIG_TSECV2
#define CONFIG_FSL_PCIE_DISABLE_ASPM
#define CONFIG_SYS_FSL_SEC_COMPAT 2
@@ -164,7 +156,6 @@
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#elif defined(CONFIG_ARCH_P1022)
-#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
#define CONFIG_TSECV2
#define CONFIG_SYS_FSL_SEC_COMPAT 2
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
@@ -192,7 +183,6 @@
/* P1024 is lower end variant of P1020 */
#elif defined(CONFIG_ARCH_P1024)
-#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
#define CONFIG_TSECV2
#define CONFIG_FSL_PCIE_DISABLE_ASPM
#define CONFIG_SYS_FSL_SEC_COMPAT 2
@@ -205,7 +195,6 @@
/* P1025 is lower end variant of P1021 */
#elif defined(CONFIG_ARCH_P1025)
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
-#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
#define CONFIG_TSECV2
#define CONFIG_FSL_PCIE_DISABLE_ASPM
#define CONFIG_SYS_FSL_SEC_COMPAT 2
@@ -218,7 +207,6 @@
#define CONFIG_SYS_FSL_ERRATUM_A005125
#elif defined(CONFIG_ARCH_P2020)
-#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
#define CONFIG_SYS_FSL_SEC_COMPAT 2
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
@@ -433,7 +421,6 @@
#define CONFIG_ESDHC_HC_BLK_ADDR
#elif defined(CONFIG_ARCH_BSC9132)
-#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
#define CONFIG_FSL_SDHC_V2_3
#define CONFIG_TSECV2
#define CONFIG_SYS_FSL_SEC_COMPAT 4
@@ -721,7 +708,6 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
#elif defined(CONFIG_ARCH_C29X)
#define CONFIG_FSL_SDHC_V2_3
-#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
#define CONFIG_TSECV2_1
#define CONFIG_SYS_FSL_SEC_COMPAT 6
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index da10149..2f33c2e 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -7211,7 +7211,6 @@ CONFIG_SYS_POWER_MANAGER
CONFIG_SYS_PPC4XX_USB_ADDR
CONFIG_SYS_PPC64
CONFIG_SYS_PPC_DDR_WIMGE
-CONFIG_SYS_PPC_E500_DEBUG_TLB
CONFIG_SYS_PQSPAR
CONFIG_SYS_PRELIM_OR_AM
CONFIG_SYS_PROMPT_HUSH_PS2
--
2.7.4
next prev parent reply other threads:[~2016-12-28 16:43 UTC|newest]
Thread overview: 52+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-12-28 16:43 [U-Boot] [PATCH 00/24] Lift mpc85xx config options to Kconfig York Sun
2016-12-28 16:43 ` [U-Boot] [PATCH 01/24] powerpc: E500: Move CONFIG_E500 and CONFIG_E500MC " York Sun
2017-01-05 13:28 ` [U-Boot] [U-Boot, " Tom Rini
2016-12-28 16:43 ` [U-Boot] [PATCH 02/24] powerpc: mpc85xx: Move CONFIG_SYS_NUM_TLBCAMS " York Sun
2017-01-05 13:28 ` [U-Boot] [U-Boot, " Tom Rini
2016-12-28 16:43 ` York Sun [this message]
2017-01-05 13:28 ` [U-Boot] [U-Boot, 03/24] powerpc: mpc85xx: Move CONFIG_SYS_PPC_E500_DEBUG_TLB " Tom Rini
2016-12-28 16:43 ` [U-Boot] [PATCH 04/24] crypto: Move SYS_FSL_SEC_COMPAT into driver Kconfig York Sun
2017-01-05 13:28 ` [U-Boot] [U-Boot, " Tom Rini
2016-12-28 16:43 ` [U-Boot] [PATCH 05/24] crypto: Move CONFIG_SYS_FSL_SEC_LE and _BE to Kconfig York Sun
2017-01-05 13:28 ` [U-Boot] [U-Boot, " Tom Rini
2016-12-28 16:43 ` [U-Boot] [PATCH 06/24] powerpc: mpc85xx: Remove variant SoCs T1020/T1022/T1013/T1014 York Sun
2017-01-05 13:28 ` [U-Boot] [U-Boot, " Tom Rini
2016-12-28 16:43 ` [U-Boot] [PATCH 07/24] powerpc: T1023RDB: Remove macro CONFIG_T1023RDB York Sun
2017-01-05 13:28 ` [U-Boot] [U-Boot, " Tom Rini
2016-12-28 16:43 ` [U-Boot] [PATCH 08/24] powerpc: T1024RDB: Remove macro CONFIG_T1024RDB York Sun
2017-01-05 13:29 ` [U-Boot] [U-Boot, " Tom Rini
2016-12-28 16:43 ` [U-Boot] [PATCH 09/24] powerpc: T1040QDS: Remove macro CONFIG_T1040QDS York Sun
2017-01-05 13:29 ` [U-Boot] [U-Boot, " Tom Rini
2016-12-28 16:43 ` [U-Boot] [PATCH 10/24] powerpc: T2080QDS: Remove macro T2080QDS York Sun
2017-01-05 13:29 ` [U-Boot] [U-Boot, " Tom Rini
2016-12-28 16:43 ` [U-Boot] [PATCH 11/24] powerpc: T2080RDB: Remove macro CONFIG_T2080RDB York Sun
2017-01-05 13:29 ` [U-Boot] [U-Boot, " Tom Rini
2016-12-28 16:43 ` [U-Boot] [PATCH 12/24] powerpc: T2081QDS: Remove macro T2081QDS York Sun
2017-01-05 13:29 ` [U-Boot] [U-Boot, " Tom Rini
2016-12-28 16:43 ` [U-Boot] [PATCH 13/24] powerpc: T104xQDS: Remove macro CONFIG_T104xD4QDS York Sun
2017-01-05 13:29 ` [U-Boot] [U-Boot, " Tom Rini
2016-12-28 16:43 ` [U-Boot] [PATCH 14/24] fsl_ddr: Move DDR config options to driver Kconfig York Sun
2017-01-05 13:29 ` [U-Boot] [U-Boot, " Tom Rini
2016-12-28 16:43 ` [U-Boot] [PATCH 15/24] arm: layerscape: Move CONFIG_SYS_FSL_ERRATUM_* to Kconfig York Sun
2017-01-05 13:29 ` [U-Boot] [U-Boot, " Tom Rini
2016-12-28 16:43 ` [U-Boot] [PATCH 16/24] mmc: move CONFIG_SYS_FSL_ERRATUM_ESDHC* " York Sun
2017-01-05 13:29 ` [U-Boot] [U-Boot, " Tom Rini
2016-12-28 16:43 ` [U-Boot] [PATCH 17/24] powerpc: mpc85xx: Move CONFIG_SYS_FSL_ERRATUM_* " York Sun
2017-01-05 13:29 ` [U-Boot] [U-Boot, " Tom Rini
2016-12-28 16:43 ` [U-Boot] [PATCH 18/24] ddr: fsl: Move macro CONFIG_NUM_DDR_CONTROLLERS " York Sun
2017-01-05 13:29 ` [U-Boot] [U-Boot, " Tom Rini
2016-12-28 16:43 ` [U-Boot] [PATCH 19/24] ddr: fsl: Merge macro CONFIG_NUM_DDR_CONTROLLERS and CONFIG_SYS_NUM_DDR_CTRLS York Sun
2017-01-05 13:29 ` [U-Boot] [U-Boot, " Tom Rini
2016-12-28 16:43 ` [U-Boot] [PATCH 20/24] ddr: fsl: Move CONFIG_SYS_FSL_DDR_VER to Kconfig York Sun
2017-01-05 13:29 ` [U-Boot] [U-Boot, " Tom Rini
2016-12-28 16:43 ` [U-Boot] [PATCH 21/24] powerpc: mpc85xx: Remove unused ifdef in config header York Sun
2017-01-05 13:30 ` [U-Boot] [U-Boot, " Tom Rini
2016-12-28 16:43 ` [U-Boot] [PATCH 22/24] powerpc: E6500: Move macro CONFIG_E6500 to Kconfig York Sun
2017-01-05 13:30 ` [U-Boot] [U-Boot, " Tom Rini
2016-12-28 16:43 ` [U-Boot] [PATCH 23/24] powerpc: mpc85xx: Move CONFIG_SYS_FSL_QORIQ_CHASSIS* " York Sun
2017-01-05 13:30 ` [U-Boot] [U-Boot, " Tom Rini
2016-12-28 16:43 ` [U-Boot] [PATCH 24/24] powerpc: mpc85xx: Move macro CONFIG_SYS_PPC64 " York Sun
2017-01-05 13:30 ` [U-Boot] [U-Boot, " Tom Rini
2017-01-05 13:28 ` [U-Boot] [PATCH 00/24] Lift mpc85xx config options " Tom Rini
2017-01-05 16:28 ` york sun
2017-01-05 17:34 ` york sun
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