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From: Mike Galbraith <efault@gmx.de>
To: Ingo Molnar <mingo@kernel.org>
Cc: Matt Fleming <matt@codeblueprint.co.uk>,
	lkml <linux-kernel@vger.kernel.org>,
	Peter Zijlstra <peterz@infradead.org>,
	Ingo Molnar <mingo@elte.hu>, Marc Zyngier <marc.zyngier@arm.com>
Subject: Re: WARNING: CPU: 1 PID: 15 at kernel/sched/sched.h:804 assert_clock_updated.isra.62.part.63+0x25/0x27
Date: Tue, 31 Jan 2017 12:17:54 +0100	[thread overview]
Message-ID: <1485861474.4419.3.camel@gmx.de> (raw)
In-Reply-To: <20170131085455.GB27019@gmail.com>

On Tue, 2017-01-31 at 09:54 +0100, Ingo Molnar wrote:

> > Fast ain't gonna happen, 5bf728f02218 bricked.
> 
> :-/
> 
> Next point would be f9a42e0d58cf I suspect, to establish that Linus's latest 
> kernel is fine. That means it's in one of the ~200 -tip commits - should be 
> bisectable in 8-10 steps from that point on.

It bisected cleanly to the below, confirmed via quilt push/pop revert. 
 According to the symptoms my box exhibits, patchlet needs to be
twiddled to ensure that interrupts are enabled at _least_ once ;-)

08d85f3ea99f1eeafc4e8507936190e86a16ee8c is the first bad commit
commit 08d85f3ea99f1eeafc4e8507936190e86a16ee8c
Author: Marc Zyngier <marc.zyngier@arm.com>
Date:   Tue Jan 17 16:00:48 2017 +0000

    irqdomain: Avoid activating interrupts more than once
    
    Since commit f3b0946d629c ("genirq/msi: Make sure PCI MSIs are
    activated early"), we can end-up activating a PCI/MSI twice (once
    at allocation time, and once at startup time).
    
    This is normally of no consequences, except that there is some
    HW out there that may misbehave if activate is used more than once
    (the GICv3 ITS, for example, uses the activate callback
    to issue the MAPVI command, and the architecture spec says that
    "If there is an existing mapping for the EventID-DeviceID
    combination, behavior is UNPREDICTABLE").
    
    While this could be worked around in each individual driver, it may
    make more sense to tackle the issue at the core level. In order to
    avoid getting in that situation, let's have a per-interrupt flag
    to remember if we have already activated that interrupt or not.
    
    Fixes: f3b0946d629c ("genirq/msi: Make sure PCI MSIs are activated early")
    Reported-and-tested-by: Andre Przywara <andre.przywara@arm.com>
    Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
    Cc: stable@vger.kernel.org
    Link: http://lkml.kernel.org/r/1484668848-24361-1-git-send-email-marc.zyngier@arm.com
    Signed-off-by: Thomas Gleixner <tglx@linutronix.de>

:040000 040000 eed859b1f22b822f4400e7c050929d8b4c4a146d 39097c0315a12c0a3809bb82687fa56b1c9e5633 M	include
:040000 040000 7dfe2ca8e1de55e890d0e6a761bab9c07c6f5f8a e28a3a54a68866273b474e2053b16155987e06f2 M	kernel

  reply	other threads:[~2017-01-31 11:18 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-01-28  7:21 WARNING: CPU: 1 PID: 15 at kernel/sched/sched.h:804 assert_clock_updated.isra.62.part.63+0x25/0x27 Mike Galbraith
2017-01-30 11:59 ` Matt Fleming
2017-01-31  6:19   ` Mike Galbraith
2017-01-31  7:28     ` Ingo Molnar
2017-01-31  7:35       ` Mike Galbraith
2017-01-31  7:45         ` Ingo Molnar
2017-01-31  8:07           ` Mike Galbraith
2017-01-31  8:51       ` Mike Galbraith
2017-01-31  8:54         ` Ingo Molnar
2017-01-31 11:17           ` Mike Galbraith [this message]
2017-01-31 16:25             ` Ingo Molnar

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