From: Gerd Hoffmann <kraxel@redhat.com>
To: Icenowy Zheng <icenowy@aosc.xyz>
Cc: Beniamino Galvani <b.galvani@gmail.com>,
Peter Maydell <peter.maydell@linaro.org>,
qemu-arm@nongnu.org
Subject: Re: [Qemu-arm] [PATCH 1/2] usb/ehci: Add SysBus EHCI device for Allwinner SoCs
Date: Tue, 07 Feb 2017 08:42:40 +0100 [thread overview]
Message-ID: <1486453360.24589.14.camel@redhat.com> (raw)
In-Reply-To: <20170207000824.8L0ShHJx@smtp1m.mail.yandex.net>
On Mo, 2017-01-30 at 21:59 +0800, Icenowy Zheng wrote:
> 2017年1月30日 16:19于 Gerd Hoffmann <kraxel@redhat.com>写道：
> >
> > On So, 2017-01-29 at 09:00 +0800, Icenowy Zheng wrote:
> > > It uses a register map like the one in Exynos SoCs.
> > >
> > > Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
> >
> > I guess this goes through the arm queue?
>
> I don't know about the QEMU development process, sorry.
The question was for Peter who maintains the arm queue.
And as patch 2/2 (which clearly belongs to arm) depends on 1/2 it is
easier to just take both through the same queue even though 2/2 is a usb
patch.
cheers,
Gerd
next prev parent reply other threads:[~2017-02-07 7:42 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-01-30 13:59 [Qemu-arm] [PATCH 1/2] usb/ehci: Add SysBus EHCI device for Allwinner SoCs Icenowy Zheng
2017-02-07 7:42 ` Gerd Hoffmann [this message]
-- strict thread matches above, loose matches on Subject: below --
2017-01-29 1:00 Icenowy Zheng
2017-01-30 8:19 ` Gerd Hoffmann
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