From: Scott Wood <oss@buserror.net>
To: yuantian.tang@nxp.com, mturquette@baylibre.com
Cc: sboyd@codeaurora.org, robh+dt@kernel.org, mark.rutland@arm.com,
linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH 2/2] clk: qoriq: Separate root input clock for core PLLs on ls1012a
Date: Wed, 15 Feb 2017 12:36:30 -0600 [thread overview]
Message-ID: <1487183790.5636.13.camel@buserror.net> (raw)
In-Reply-To: <1487137656-4006-2-git-send-email-yuantian.tang@nxp.com>
On Wed, 2017-02-15 at 13:47 +0800, yuantian.tang@nxp.com wrote:
> From: Tang Yuantian <Yuantian.Tang@nxp.com>
>
> ls1012a has separate input root clocks for core PLLs versus the
> platform PLL, with the latter described as sysclk in the hw docs.
> If a second input clock, named "coreclk", is present, this clock will be
> used for the core PLLs.
>
> Signed-off-by: Scott Wood <oss@buserror.net>
> Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com>
> ---
> drivers/clk/clk-qoriq.c | 91 +++++++++++++++++++++++++++++++++++++++++-----
Why did you reset the author on these patches? Have you changed anything?
Why aren't they marked either v2 or resend?
-Scott
WARNING: multiple messages have this Message-ID (diff)
From: oss@buserror.net (Scott Wood)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 2/2] clk: qoriq: Separate root input clock for core PLLs on ls1012a
Date: Wed, 15 Feb 2017 12:36:30 -0600 [thread overview]
Message-ID: <1487183790.5636.13.camel@buserror.net> (raw)
In-Reply-To: <1487137656-4006-2-git-send-email-yuantian.tang@nxp.com>
On Wed, 2017-02-15 at 13:47 +0800, yuantian.tang at nxp.com wrote:
> From: Tang Yuantian <Yuantian.Tang@nxp.com>
>
> ls1012a has separate input root clocks for core PLLs versus the
> platform PLL, with the latter described as sysclk in the hw docs.
> If a second input clock, named "coreclk", is present, this clock will be
> used for the core PLLs.
>
> Signed-off-by: Scott Wood <oss@buserror.net>
> Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com>
> ---
> ?drivers/clk/clk-qoriq.c | 91 +++++++++++++++++++++++++++++++++++++++++-----
Why did you reset the author on these patches? ?Have you changed anything?
?Why aren't they marked either v2 or resend?
-Scott
WARNING: multiple messages have this Message-ID (diff)
From: Scott Wood <oss-fOR+EgIDQEHk1uMJSBkQmQ@public.gmane.org>
To: yuantian.tang-3arQi8VN3Tc@public.gmane.org,
mturquette-rdvid1DuHRBWk0Htik3J/w@public.gmane.org
Cc: sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org,
mark.rutland-5wv7dgnIgG8@public.gmane.org,
linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
Subject: Re: [PATCH 2/2] clk: qoriq: Separate root input clock for core PLLs on ls1012a
Date: Wed, 15 Feb 2017 12:36:30 -0600 [thread overview]
Message-ID: <1487183790.5636.13.camel@buserror.net> (raw)
In-Reply-To: <1487137656-4006-2-git-send-email-yuantian.tang-3arQi8VN3Tc@public.gmane.org>
On Wed, 2017-02-15 at 13:47 +0800, yuantian.tang-3arQi8VN3Tc@public.gmane.org wrote:
> From: Tang Yuantian <Yuantian.Tang-3arQi8VN3Tc@public.gmane.org>
>
> ls1012a has separate input root clocks for core PLLs versus the
> platform PLL, with the latter described as sysclk in the hw docs.
> If a second input clock, named "coreclk", is present, this clock will be
> used for the core PLLs.
>
> Signed-off-by: Scott Wood <oss-fOR+EgIDQEHk1uMJSBkQmQ@public.gmane.org>
> Signed-off-by: Tang Yuantian <yuantian.tang-3arQi8VN3Tc@public.gmane.org>
> ---
> drivers/clk/clk-qoriq.c | 91 +++++++++++++++++++++++++++++++++++++++++-----
Why did you reset the author on these patches? Have you changed anything?
Why aren't they marked either v2 or resend?
-Scott
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next prev parent reply other threads:[~2017-02-15 18:36 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-02-15 5:47 [PATCH 1/2] dt-bindings: qoriq-clock: Add coreclk yuantian.tang
2017-02-15 5:47 ` yuantian.tang
2017-02-15 5:47 ` yuantian.tang at nxp.com
2017-02-15 5:47 ` [PATCH 2/2] clk: qoriq: Separate root input clock for core PLLs on ls1012a yuantian.tang
2017-02-15 5:47 ` yuantian.tang
2017-02-15 5:47 ` yuantian.tang at nxp.com
2017-02-15 18:36 ` Scott Wood [this message]
2017-02-15 18:36 ` Scott Wood
2017-02-15 18:36 ` Scott Wood
2017-02-16 2:21 ` Y.T. Tang
2017-02-16 2:21 ` Y.T. Tang
2017-02-16 2:21 ` Y.T. Tang
2017-02-27 2:19 ` [PATCH 1/2] dt-bindings: qoriq-clock: Add coreclk Y.T. Tang
2017-02-27 2:19 ` Y.T. Tang
2017-02-27 2:19 ` Y.T. Tang
2017-02-27 2:19 ` Y.T. Tang
2017-02-27 17:18 ` Rob Herring
2017-02-27 17:18 ` Rob Herring
2017-02-27 17:18 ` Rob Herring
2017-03-01 1:45 ` Y.T. Tang
2017-03-01 1:45 ` Y.T. Tang
2017-03-01 1:45 ` Y.T. Tang
2017-03-01 1:45 ` Y.T. Tang
2017-03-01 23:17 ` Rob Herring
2017-03-01 23:17 ` Rob Herring
2017-03-09 8:46 ` Y.T. Tang
2017-03-09 8:46 ` Y.T. Tang
2017-03-09 8:46 ` Y.T. Tang
2017-03-09 8:46 ` Y.T. Tang
2017-07-21 22:03 ` sboyd
2017-07-21 22:03 ` sboyd-sgV2jX0FEOL9JmXXK+q4OQ
2017-07-21 22:03 ` sboyd at codeaurora.org
2017-07-24 1:20 ` Andy Tang
2017-07-24 1:20 ` Andy Tang
2017-07-24 1:20 ` Andy Tang
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