From: daniel.lezcano@linaro.org (Daniel Lezcano)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 03/29] arm64: Define Cortex-A73 MIDR
Date: Sun, 16 Apr 2017 22:26:53 +0200 [thread overview]
Message-ID: <1492374441-23336-3-git-send-email-daniel.lezcano@linaro.org> (raw)
In-Reply-To: <1492374441-23336-1-git-send-email-daniel.lezcano@linaro.org>
From: Marc Zyngier <marc.zyngier@arm.com>
As we're about to introduce a new workaround that is specific to
Cortex-A73, let's define the coresponding MIDR.
Acked-by: Thomas Gleixner <tglx@linutronix.de>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
---
arch/arm64/include/asm/cputype.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h
index fc50271..0984d1b 100644
--- a/arch/arm64/include/asm/cputype.h
+++ b/arch/arm64/include/asm/cputype.h
@@ -80,6 +80,7 @@
#define ARM_CPU_PART_FOUNDATION 0xD00
#define ARM_CPU_PART_CORTEX_A57 0xD07
#define ARM_CPU_PART_CORTEX_A53 0xD03
+#define ARM_CPU_PART_CORTEX_A73 0xD09
#define APM_CPU_PART_POTENZA 0x000
@@ -92,6 +93,7 @@
#define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53)
#define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57)
+#define MIDR_CORTEX_A73 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A73)
#define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)
#define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)
#define MIDR_QCOM_FALKOR_V1 MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_FALKOR_V1)
--
2.7.4
WARNING: multiple messages have this Message-ID (diff)
From: Daniel Lezcano <daniel.lezcano@linaro.org>
To: tglx@linutronix.de
Cc: linux-kernel@vger.kernel.org, Marc Zyngier <marc.zyngier@arm.com>,
Mark Rutland <mark.rutland@arm.com>,
Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will.deacon@arm.com>,
Christopher Covington <cov@codeaurora.org>,
Shanker Donthineni <shankerd@codeaurora.org>,
Ganapatrao Kulkarni <gkulkarni@caviumnetworks.com>,
Robert Richter <rrichter@cavium.com>,
linux-arm-kernel@lists.infradead.org (moderated list:ARM64 PORT
(AARCH64 ARCHITECTURE))
Subject: [PATCH 03/29] arm64: Define Cortex-A73 MIDR
Date: Sun, 16 Apr 2017 22:26:53 +0200 [thread overview]
Message-ID: <1492374441-23336-3-git-send-email-daniel.lezcano@linaro.org> (raw)
In-Reply-To: <1492374441-23336-1-git-send-email-daniel.lezcano@linaro.org>
From: Marc Zyngier <marc.zyngier@arm.com>
As we're about to introduce a new workaround that is specific to
Cortex-A73, let's define the coresponding MIDR.
Acked-by: Thomas Gleixner <tglx@linutronix.de>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
---
arch/arm64/include/asm/cputype.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h
index fc50271..0984d1b 100644
--- a/arch/arm64/include/asm/cputype.h
+++ b/arch/arm64/include/asm/cputype.h
@@ -80,6 +80,7 @@
#define ARM_CPU_PART_FOUNDATION 0xD00
#define ARM_CPU_PART_CORTEX_A57 0xD07
#define ARM_CPU_PART_CORTEX_A53 0xD03
+#define ARM_CPU_PART_CORTEX_A73 0xD09
#define APM_CPU_PART_POTENZA 0x000
@@ -92,6 +93,7 @@
#define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53)
#define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57)
+#define MIDR_CORTEX_A73 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A73)
#define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)
#define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)
#define MIDR_QCOM_FALKOR_V1 MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_FALKOR_V1)
--
2.7.4
next prev parent reply other threads:[~2017-04-16 20:26 UTC|newest]
Thread overview: 71+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-04-16 20:25 [GIT PULL] timers changes for 4.12 Daniel Lezcano
2017-04-16 20:26 ` [PATCH 01/29] arm64: Allow checking of a CPU-local erratum Daniel Lezcano
2017-04-16 20:26 ` Daniel Lezcano
2017-04-16 20:26 ` [PATCH 02/29] arm64: Add CNTVCT_EL0 trap handler Daniel Lezcano
2017-04-16 20:26 ` Daniel Lezcano
2017-04-16 20:26 ` Daniel Lezcano [this message]
2017-04-16 20:26 ` [PATCH 03/29] arm64: Define Cortex-A73 MIDR Daniel Lezcano
2017-04-16 20:26 ` [PATCH 04/29] arm64: cpu_errata: Allow an erratum to be match for all revisions of a core Daniel Lezcano
2017-04-16 20:26 ` Daniel Lezcano
2017-04-16 20:26 ` [PATCH 05/29] arm64: cpu_errata: Add capability to advertise Cortex-A73 erratum 858921 Daniel Lezcano
2017-04-16 20:26 ` Daniel Lezcano
2017-04-16 20:26 ` [PATCH 06/29] arm64: arch_timer: Add infrastructure for multiple erratum detection methods Daniel Lezcano
2017-04-16 20:26 ` Daniel Lezcano
2017-04-16 20:26 ` [PATCH 07/29] arm64: arch_timer: Add erratum handler for CPU-specific capability Daniel Lezcano
2017-04-16 20:26 ` Daniel Lezcano
2017-04-16 20:26 ` [PATCH 08/29] arm64: arch_timer: Move arch_timer_reg_read/write around Daniel Lezcano
2017-04-16 20:26 ` Daniel Lezcano
2017-04-16 20:26 ` [PATCH 09/29] arm64: arch_timer: Get rid of erratum_workaround_set_sne Daniel Lezcano
2017-04-16 20:26 ` Daniel Lezcano
2017-04-16 20:27 ` [PATCH 10/29] arm64: arch_timer: Rework the set_next_event workarounds Daniel Lezcano
2017-04-16 20:27 ` Daniel Lezcano
2017-04-16 20:27 ` [PATCH 11/29] arm64: arch_timer: Make workaround methods optional Daniel Lezcano
2017-04-16 20:27 ` Daniel Lezcano
2017-04-16 20:27 ` [PATCH 12/29] arm64: arch_timer: Allows a CPU-specific erratum to only affect a subset of CPUs Daniel Lezcano
2017-04-16 20:27 ` Daniel Lezcano
2017-04-16 20:27 ` [PATCH 13/29] arm64: arch_timer: Move clocksource_counter and co around Daniel Lezcano
2017-04-16 20:27 ` Daniel Lezcano
2017-04-16 20:27 ` [PATCH 14/29] arm64: arch_timer: Save cntkctl_el1 as a per-cpu variable Daniel Lezcano
2017-04-16 20:27 ` Daniel Lezcano
2017-04-16 20:27 ` [PATCH 15/29] arm64: arch_timer: Enable CNTVCT_EL0 trap if workaround is enabled Daniel Lezcano
2017-04-16 20:27 ` Daniel Lezcano
2017-04-16 20:27 ` [PATCH 16/29] arm64: arch_timer: Workaround for Cortex-A73 erratum 858921 Daniel Lezcano
2017-04-16 20:27 ` Daniel Lezcano
2017-04-16 20:27 ` [PATCH 17/29] arm64: arch_timer: Allow erratum matching with ACPI OEM information Daniel Lezcano
2017-04-16 20:27 ` Daniel Lezcano
2017-04-16 20:27 ` [PATCH 18/29] arm64: arch_timer: Add HISILICON_ERRATUM_161010101 ACPI matching data Daniel Lezcano
2017-04-16 20:27 ` Daniel Lezcano
2017-04-16 20:27 ` [PATCH 19/29] clocksource/drivers/orion: Read clock rate once Daniel Lezcano
2017-04-16 20:27 ` [PATCH 20/29] clocksource/drivers/orion: Add delay_timer implementation Daniel Lezcano
2017-04-16 20:27 ` [PATCH 21/29] clocksource: Add missing line break to error messages Daniel Lezcano
2017-04-16 20:27 ` Daniel Lezcano
2017-04-16 20:27 ` Daniel Lezcano
2017-04-16 20:27 ` Daniel Lezcano
2017-04-16 20:27 ` Daniel Lezcano
2017-04-24 7:45 ` Uwe Kleine-König
2017-04-24 7:45 ` Uwe Kleine-König
2017-04-24 7:45 ` Uwe Kleine-König
2017-04-24 7:45 ` Uwe Kleine-König
2017-04-24 7:45 ` Uwe Kleine-König
2017-04-16 20:27 ` [PATCH 22/29] dt-bindings: Clarify compatible property for rockchip timers Daniel Lezcano
2017-04-16 20:27 ` Daniel Lezcano
2017-04-16 20:27 ` Daniel Lezcano
[not found] ` <1492374441-23336-22-git-send-email-daniel.lezcano-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
2017-04-20 14:12 ` Rob Herring
2017-04-20 14:12 ` Rob Herring
2017-04-20 14:12 ` Rob Herring
2017-04-16 20:27 ` [PATCH 23/29] ARM: dts: rockchip: Update compatible property for rk322x timer Daniel Lezcano
2017-04-16 20:27 ` Daniel Lezcano
2017-04-16 20:27 ` Daniel Lezcano
2017-04-16 20:27 ` [PATCH 24/29] clocksource/drivers/rockchip_timer: Implement clocksource timer Daniel Lezcano
2017-04-16 20:27 ` Daniel Lezcano
2017-04-16 20:27 ` Daniel Lezcano
2017-04-16 20:27 ` [PATCH 25/29] ARM: dts: rockchip: Add timer entries to rk3188 SoC Daniel Lezcano
2017-04-16 20:27 ` Daniel Lezcano
2017-04-16 20:27 ` Daniel Lezcano
2017-04-16 20:27 ` [PATCH 26/29] ARM: dts: rockchip: disable arm-global-timer for rk3188 Daniel Lezcano
2017-04-16 20:27 ` Daniel Lezcano
2017-04-16 20:27 ` Daniel Lezcano
2017-04-16 20:27 ` [PATCH 27/29] clocksource: Augment bindings for Faraday timer Daniel Lezcano
2017-04-16 20:27 ` Daniel Lezcano
2017-04-16 20:27 ` [PATCH 28/29] clocksource/drivers/gemini: Rename Gemini timer to Faraday Daniel Lezcano
2017-04-16 20:27 ` [PATCH 29/29] clocksource/drivers/fttmr010: Refactor to handle clock Daniel Lezcano
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1492374441-23336-3-git-send-email-daniel.lezcano@linaro.org \
--to=daniel.lezcano@linaro.org \
--cc=linux-arm-kernel@lists.infradead.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.