* [U-Boot] [PATCH 0/2] *** SUBJECT HERE ***
@ 2017-06-22 6:38 make at marvell.com
2017-06-22 6:38 ` [U-Boot] [PATCH 1/2] pinctrl: a3700: Fix uart2 group selection register mask make at marvell.com
2017-06-22 6:38 ` [U-Boot] [PATCH 2/2] pinctrl: a3700: Fix the issue that gpio controller is registered with wrong node id make at marvell.com
0 siblings, 2 replies; 6+ messages in thread
From: make at marvell.com @ 2017-06-22 6:38 UTC (permalink / raw)
To: u-boot
From: Ken Ma <make@marvell.com>
*** BLURB HERE ***
Fix 2 armada37x0 pinctrl issues.
Ken Ma (2):
pinctrl: a3700: Fix uart2 group selection register mask
pinctrl: a3700: Fix the issue that gpio controller is registered with
wrong node id
drivers/pinctrl/mvebu/pinctrl-armada-37xx.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
--
1.9.1
^ permalink raw reply [flat|nested] 6+ messages in thread* [U-Boot] [PATCH 1/2] pinctrl: a3700: Fix uart2 group selection register mask 2017-06-22 6:38 [U-Boot] [PATCH 0/2] *** SUBJECT HERE *** make at marvell.com @ 2017-06-22 6:38 ` make at marvell.com 2017-06-22 6:38 ` [U-Boot] [PATCH 2/2] pinctrl: a3700: Fix the issue that gpio controller is registered with wrong node id make at marvell.com 1 sibling, 0 replies; 6+ messages in thread From: make at marvell.com @ 2017-06-22 6:38 UTC (permalink / raw) To: u-boot From: Ken Ma <make@marvell.com> If north bridge selection register bit1 is clear, pins [10:8] are for SDIO0 Resetn, Wakeup, and PDN while if bit1 is set, pins [10:8]are for GPIO; when bit1 is clear, pin 9 and pin 10 can be used for uart2 RTSn and CTSn, so bit1 should be added to uart2 group and it must be set for both "gpio" and "uart" functions of uart2 group. Signed-off-by: Ken Ma <make@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Kostya Porotchkin <kostap@marvell.com> --- drivers/pinctrl/mvebu/pinctrl-armada-37xx.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c index 3bb4c43..2ac66ec 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c @@ -159,8 +159,9 @@ static struct armada_37xx_pin_group armada_37xx_nb_groups[] = { PIN_GRP_GPIO("onewire", 4, 1, BIT(16), "onewire"), PIN_GRP_GPIO("uart1", 25, 2, BIT(17), "uart"), PIN_GRP_GPIO("spi_quad", 15, 2, BIT(18), "spi"), - PIN_GRP_EXTRA("uart2", 9, 2, BIT(13) | BIT(14) | BIT(19), - BIT(13) | BIT(14), BIT(19), 18, 2, "gpio", "uart"), + PIN_GRP_EXTRA("uart2", 9, 2, BIT(1) | BIT(13) | BIT(14) | BIT(19), + BIT(1) | BIT(13) | BIT(14), BIT(1) | BIT(19), + 18, 2, "gpio", "uart"), PIN_GRP_GPIO("led0_od", 11, 1, BIT(20), "led"), PIN_GRP_GPIO("led1_od", 12, 1, BIT(21), "led"), PIN_GRP_GPIO("led2_od", 13, 1, BIT(22), "led"), -- 1.9.1 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* [U-Boot] [PATCH 2/2] pinctrl: a3700: Fix the issue that gpio controller is registered with wrong node id 2017-06-22 6:38 [U-Boot] [PATCH 0/2] *** SUBJECT HERE *** make at marvell.com 2017-06-22 6:38 ` [U-Boot] [PATCH 1/2] pinctrl: a3700: Fix uart2 group selection register mask make at marvell.com @ 2017-06-22 6:38 ` make at marvell.com 1 sibling, 0 replies; 6+ messages in thread From: make at marvell.com @ 2017-06-22 6:38 UTC (permalink / raw) To: u-boot From: Ken Ma <make@marvell.com> In armada_37xx_gpiochip_register, the return value of fdtdec_get_bool should be true when gpio-controller is found; current codes makes a wrong inverse return value judgement, this patch fixes it. Signed-off-by: Ken Ma <make@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Kostya Porotchkin <kostap@marvell.com> --- drivers/pinctrl/mvebu/pinctrl-armada-37xx.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c index 2ac66ec..27165b0 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c @@ -539,7 +539,7 @@ static int armada_37xx_gpiochip_register(struct udevice *parent, } fdt_for_each_subnode(subnode, blob, node) { - if (!fdtdec_get_bool(blob, subnode, "gpio-controller")) { + if (fdtdec_get_bool(blob, subnode, "gpio-controller")) { ret = 0; break; } -- 1.9.1 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* [U-Boot] [PATCH 0/2] *** SUBJECT HERE ***
@ 2017-06-22 9:13 make at marvell.com
2017-06-22 9:13 ` [U-Boot] [PATCH 1/2] pinctrl: a3700: Fix uart2 group selection register mask make at marvell.com
0 siblings, 1 reply; 6+ messages in thread
From: make at marvell.com @ 2017-06-22 9:13 UTC (permalink / raw)
To: u-boot
From: Ken Ma <make@marvell.com>
*** BLURB HERE ***
Fix 2 armada-37xx pinctrl issues.
Ken Ma (2):
pinctrl: a3700: Fix uart2 group selection register mask
pinctrl: a3700: Fix the issue that gpio controller is registered with
wrong node id
drivers/pinctrl/mvebu/pinctrl-armada-37xx.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
--
1.9.1
^ permalink raw reply [flat|nested] 6+ messages in thread* [U-Boot] [PATCH 1/2] pinctrl: a3700: Fix uart2 group selection register mask 2017-06-22 9:13 [U-Boot] [PATCH 0/2] *** SUBJECT HERE *** make at marvell.com @ 2017-06-22 9:13 ` make at marvell.com 2017-06-22 9:20 ` Stefan Roese 2017-06-23 8:40 ` Stefan Roese 0 siblings, 2 replies; 6+ messages in thread From: make at marvell.com @ 2017-06-22 9:13 UTC (permalink / raw) To: u-boot From: Ken Ma <make@marvell.com> If north bridge selection register bit1 is clear, pins [10:8] are for SDIO0 Resetn, Wakeup, and PDN while if bit1 is set, pins [10:8]are for GPIO; when bit1 is clear, pin 9 and pin 10 can be used for uart2 RTSn and CTSn, so bit1 should be added to uart2 group and it must be set for both "gpio" and "uart" functions of uart2 group. Signed-off-by: Ken Ma <make@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Gregory CLEMENT <gregory.clement@free-electrons.com> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Wilson Ding <dingwei@marvell.com> --- drivers/pinctrl/mvebu/pinctrl-armada-37xx.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c index 3bb4c43..2ac66ec 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c @@ -159,8 +159,9 @@ static struct armada_37xx_pin_group armada_37xx_nb_groups[] = { PIN_GRP_GPIO("onewire", 4, 1, BIT(16), "onewire"), PIN_GRP_GPIO("uart1", 25, 2, BIT(17), "uart"), PIN_GRP_GPIO("spi_quad", 15, 2, BIT(18), "spi"), - PIN_GRP_EXTRA("uart2", 9, 2, BIT(13) | BIT(14) | BIT(19), - BIT(13) | BIT(14), BIT(19), 18, 2, "gpio", "uart"), + PIN_GRP_EXTRA("uart2", 9, 2, BIT(1) | BIT(13) | BIT(14) | BIT(19), + BIT(1) | BIT(13) | BIT(14), BIT(1) | BIT(19), + 18, 2, "gpio", "uart"), PIN_GRP_GPIO("led0_od", 11, 1, BIT(20), "led"), PIN_GRP_GPIO("led1_od", 12, 1, BIT(21), "led"), PIN_GRP_GPIO("led2_od", 13, 1, BIT(22), "led"), -- 1.9.1 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* [U-Boot] [PATCH 1/2] pinctrl: a3700: Fix uart2 group selection register mask 2017-06-22 9:13 ` [U-Boot] [PATCH 1/2] pinctrl: a3700: Fix uart2 group selection register mask make at marvell.com @ 2017-06-22 9:20 ` Stefan Roese 2017-06-23 8:40 ` Stefan Roese 1 sibling, 0 replies; 6+ messages in thread From: Stefan Roese @ 2017-06-22 9:20 UTC (permalink / raw) To: u-boot Hi Ken, On 22.06.2017 11:13, make at marvell.com wrote: > From: Ken Ma <make@marvell.com> > > If north bridge selection register bit1 is clear, pins [10:8] are for > SDIO0 Resetn, Wakeup, and PDN while if bit1 is set, pins [10:8]are for > GPIO; when bit1 is clear, pin 9 and pin 10 can be used for uart2 RTSn > and CTSn, so bit1 should be added to uart2 group and it must be set > for both "gpio" and "uart" functions of uart2 group. > > Signed-off-by: Ken Ma <make@marvell.com> > Cc: Stefan Roese <sr@denx.de> > Cc: Kostya Porotchkin <kostap@marvell.com> > Cc: Gregory CLEMENT <gregory.clement@free-electrons.com> > Cc: Nadav Haklai <nadavh@marvell.com> > Cc: Wilson Ding <dingwei@marvell.com> Thanks for the the patches. One remark though about the patch submission process: You should mark version of your patches and list the changes (patch history) in the patch as described here: http://www.denx.de/wiki/view/U-Boot/Patches#Sending_updated_patch_versions This makes the review process much easier, as the reviewer does not need to review the whole patch again, but only need to look for the new changes in new version. You don't need to do it for these patches, but please do it the next time. For this patch: Reviewed-by: Stefan Roese <sr@denx.de> Thanks, Stefan ^ permalink raw reply [flat|nested] 6+ messages in thread
* [U-Boot] [PATCH 1/2] pinctrl: a3700: Fix uart2 group selection register mask 2017-06-22 9:13 ` [U-Boot] [PATCH 1/2] pinctrl: a3700: Fix uart2 group selection register mask make at marvell.com 2017-06-22 9:20 ` Stefan Roese @ 2017-06-23 8:40 ` Stefan Roese 1 sibling, 0 replies; 6+ messages in thread From: Stefan Roese @ 2017-06-23 8:40 UTC (permalink / raw) To: u-boot On 22.06.2017 11:13, make at marvell.com wrote: > From: Ken Ma <make@marvell.com> > > If north bridge selection register bit1 is clear, pins [10:8] are for > SDIO0 Resetn, Wakeup, and PDN while if bit1 is set, pins [10:8]are for > GPIO; when bit1 is clear, pin 9 and pin 10 can be used for uart2 RTSn > and CTSn, so bit1 should be added to uart2 group and it must be set > for both "gpio" and "uart" functions of uart2 group. > > Signed-off-by: Ken Ma <make@marvell.com> > Cc: Stefan Roese <sr@denx.de> > Cc: Kostya Porotchkin <kostap@marvell.com> > Cc: Gregory CLEMENT <gregory.clement@free-electrons.com> > Cc: Nadav Haklai <nadavh@marvell.com> > Cc: Wilson Ding <dingwei@marvell.com> Applied to u-boot-marvell/master. Thanks, Stefan ^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2017-06-23 8:40 UTC | newest] Thread overview: 6+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2017-06-22 6:38 [U-Boot] [PATCH 0/2] *** SUBJECT HERE *** make at marvell.com 2017-06-22 6:38 ` [U-Boot] [PATCH 1/2] pinctrl: a3700: Fix uart2 group selection register mask make at marvell.com 2017-06-22 6:38 ` [U-Boot] [PATCH 2/2] pinctrl: a3700: Fix the issue that gpio controller is registered with wrong node id make at marvell.com -- strict thread matches above, loose matches on Subject: below -- 2017-06-22 9:13 [U-Boot] [PATCH 0/2] *** SUBJECT HERE *** make at marvell.com 2017-06-22 9:13 ` [U-Boot] [PATCH 1/2] pinctrl: a3700: Fix uart2 group selection register mask make at marvell.com 2017-06-22 9:20 ` Stefan Roese 2017-06-23 8:40 ` Stefan Roese
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