[PATCHv6 0/3]

[PATCHv6 0/3]

[Hean-Loong, Ong]

From: Ong Hean Loong <hean.loong.ong@intel.com>

The FPGA FrameBuffer Soft IP could be seen  as the GPU and 
the DRM driver patch here is allocating memory for 
information to be streamed from the ARM/Linux to the display port.
Basically the driver just wraps the information such as the pixels to 
be drawn by the FPGA FrameBuffer 2.

The piece of hardware in discussion is the SoC FPGA where Linux runs 
on the ARM chip and the FGPA is driven by its NIOS soft core with its 
own proprietary firmware.

For example the application from the ARM Linux would have to write  
information on the /dev/fb0 with the information stored in the SDRAM 
to be fetched by the FPGA framebuffer IP and displayed on the Display 
Port Monitor.

Ong Hean Loong (3):
  ARM:dt-bindings Intel FPGA Video and Image Processing Suite
  ARM:socfpga-defconfig Intel FPGA Video and Image Processing Suite
  ARM:drm ivip Intel FPGA Video and Image Processing Suite

 .../devicetree/bindings/display/altr,vip-fb2.txt   |  42 +++++
 arch/arm/configs/socfpga_defconfig                 |   6 +
 drivers/gpu/drm/Kconfig                            |   2 +
 drivers/gpu/drm/Makefile                           |   1 +
 drivers/gpu/drm/ivip/Kconfig                       |  14 ++
 drivers/gpu/drm/ivip/Makefile                      |   9 +
 drivers/gpu/drm/ivip/intel_vip_conn.c              |  96 ++++++++++
 drivers/gpu/drm/ivip/intel_vip_core.c              | 162 +++++++++++++++++
 drivers/gpu/drm/ivip/intel_vip_drv.h               |  52 ++++++
 drivers/gpu/drm/ivip/intel_vip_of.c                | 194 +++++++++++++++++++++
 10 files changed, 578 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/display/altr,vip-fb2.txt
 create mode 100644 drivers/gpu/drm/ivip/Kconfig
 create mode 100644 drivers/gpu/drm/ivip/Makefile
 create mode 100644 drivers/gpu/drm/ivip/intel_vip_conn.c
 create mode 100644 drivers/gpu/drm/ivip/intel_vip_core.c
 create mode 100644 drivers/gpu/drm/ivip/intel_vip_drv.h
 create mode 100644 drivers/gpu/drm/ivip/intel_vip_of.c

-- 
2.7.4

[PATCHv6 0/3]

[Hean-Loong, Ong]

From: Ong Hean Loong <hean.loong.ong@intel.com>

The FPGA FrameBuffer Soft IP could be seen  as the GPU and 
the DRM driver patch here is allocating memory for 
information to be streamed from the ARM/Linux to the display port.
Basically the driver just wraps the information such as the pixels to 
be drawn by the FPGA FrameBuffer 2.

The piece of hardware in discussion is the SoC FPGA where Linux runs 
on the ARM chip and the FGPA is driven by its NIOS soft core with its 
own proprietary firmware.

For example the application from the ARM Linux would have to write  
information on the /dev/fb0 with the information stored in the SDRAM 
to be fetched by the FPGA framebuffer IP and displayed on the Display 
Port Monitor.

Ong Hean Loong (3):
  ARM:dt-bindings Intel FPGA Video and Image Processing Suite
  ARM:socfpga-defconfig Intel FPGA Video and Image Processing Suite
  ARM:drm ivip Intel FPGA Video and Image Processing Suite

 .../devicetree/bindings/display/altr,vip-fb2.txt   |  42 +++++
 arch/arm/configs/socfpga_defconfig                 |   6 +
 drivers/gpu/drm/Kconfig                            |   2 +
 drivers/gpu/drm/Makefile                           |   1 +
 drivers/gpu/drm/ivip/Kconfig                       |  14 ++
 drivers/gpu/drm/ivip/Makefile                      |   9 +
 drivers/gpu/drm/ivip/intel_vip_conn.c              |  96 ++++++++++
 drivers/gpu/drm/ivip/intel_vip_core.c              | 162 +++++++++++++++++
 drivers/gpu/drm/ivip/intel_vip_drv.h               |  52 ++++++
 drivers/gpu/drm/ivip/intel_vip_of.c                | 194 +++++++++++++++++++++
 10 files changed, 578 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/display/altr,vip-fb2.txt
 create mode 100644 drivers/gpu/drm/ivip/Kconfig
 create mode 100644 drivers/gpu/drm/ivip/Makefile
 create mode 100644 drivers/gpu/drm/ivip/intel_vip_conn.c
 create mode 100644 drivers/gpu/drm/ivip/intel_vip_core.c
 create mode 100644 drivers/gpu/drm/ivip/intel_vip_drv.h
 create mode 100644 drivers/gpu/drm/ivip/intel_vip_of.c

-- 
2.7.4

[PATCHv6 0/3]

[Hean-Loong, Ong]

From: Ong Hean Loong <hean.loong.ong-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>

The FPGA FrameBuffer Soft IP could be seen  as the GPU and 
the DRM driver patch here is allocating memory for 
information to be streamed from the ARM/Linux to the display port.
Basically the driver just wraps the information such as the pixels to 
be drawn by the FPGA FrameBuffer 2.

The piece of hardware in discussion is the SoC FPGA where Linux runs 
on the ARM chip and the FGPA is driven by its NIOS soft core with its 
own proprietary firmware.

For example the application from the ARM Linux would have to write  
information on the /dev/fb0 with the information stored in the SDRAM 
to be fetched by the FPGA framebuffer IP and displayed on the Display 
Port Monitor.

Ong Hean Loong (3):
  ARM:dt-bindings Intel FPGA Video and Image Processing Suite
  ARM:socfpga-defconfig Intel FPGA Video and Image Processing Suite
  ARM:drm ivip Intel FPGA Video and Image Processing Suite

 .../devicetree/bindings/display/altr,vip-fb2.txt   |  42 +++++
 arch/arm/configs/socfpga_defconfig                 |   6 +
 drivers/gpu/drm/Kconfig                            |   2 +
 drivers/gpu/drm/Makefile                           |   1 +
 drivers/gpu/drm/ivip/Kconfig                       |  14 ++
 drivers/gpu/drm/ivip/Makefile                      |   9 +
 drivers/gpu/drm/ivip/intel_vip_conn.c              |  96 ++++++++++
 drivers/gpu/drm/ivip/intel_vip_core.c              | 162 +++++++++++++++++
 drivers/gpu/drm/ivip/intel_vip_drv.h               |  52 ++++++
 drivers/gpu/drm/ivip/intel_vip_of.c                | 194 +++++++++++++++++++++
 10 files changed, 578 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/display/altr,vip-fb2.txt
 create mode 100644 drivers/gpu/drm/ivip/Kconfig
 create mode 100644 drivers/gpu/drm/ivip/Makefile
 create mode 100644 drivers/gpu/drm/ivip/intel_vip_conn.c
 create mode 100644 drivers/gpu/drm/ivip/intel_vip_core.c
 create mode 100644 drivers/gpu/drm/ivip/intel_vip_drv.h
 create mode 100644 drivers/gpu/drm/ivip/intel_vip_of.c

-- 
2.7.4

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[PATCHv6 1/3] ARM:dt-bindings Intel FPGA Video and Image Processing Suite

[Hean-Loong, Ong]

From: Ong Hean Loong <hean.loong.ong@intel.com>

Device tree binding for Intel FPGA Video and Image
Processing Suite. The binding involved would be generated
from the Altera (Intel) Qsys system. The bindings would
set the max width, max height, buts per pixel and memory
port width. The device tree binding only supports the Intel
Arria10 devkit and its variants. Vendor name retained as
altr.

Signed-off-by: Ong, Hean Loong <hean.loong.ong@intel.com>
---
V6:
Fix comments for description

V5:
*Fix comments on description
*remove bindings for bits per symbol as it has only one value which is 8

V4:
*Fix comments on description

V3:
*Fix comments on description

V2:
*Fix comments on description

V1:
*Fix comments on description
---
---
 .../devicetree/bindings/display/altr,vip-fb2.txt   | 42 ++++++++++++++++++++++
 1 file changed, 42 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/display/altr,vip-fb2.txt

diff --git a/Documentation/devicetree/bindings/display/altr,vip-fb2.txt b/Documentation/devicetree/bindings/display/altr,vip-fb2.txt
new file mode 100644
index 0000000..57d8869
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/altr,vip-fb2.txt
@@ -0,0 +1,42 @@
+Intel Video and Image Processing(VIP) Frame Buffer II bindings
+
+Supported hardware: Intel FPGA SoC Arria10 and above with display port IP
+
+The hardware associated with this device tree is a SoC FPGA.
+Where there is an microprocessor and a FPGA device.
+The microprocessor would host the OS while the FPGA device runs
+on its individual IP firmware. The Intel VIP Frame Buffer II
+system would be driving data from the to the FPGA device
+programmed with the Frame Buffer II IP to render pixels to be streamed
+to the Display Port connector.
+
+The Frame Buffer II device is a simple frame buffer device. The device
+contains the display properties and the bridge or connector register.
+The output for this device currently is a dedicated to a single Display Port.
+Currently the max resolution supported is 1280 x 720 at 60Hz.
+
+More information the FPGA video IP component can be acquired from
+https://www.altera.com/content/dam/altera-www/global/en_US/pdfs\
+/literature/ug/ug_vip.pdf
+
+New bindings:
+=============
+Required properties:
+----------------------------
+- compatible: "altr,vip-frame-buffer-2.0"
+- reg: Physical base address and length of the framebuffer controller's
+	registers.
+- altr,max-width: The maximum width of the framebuffer in pixels.
+- altr,max-height: The maximum height of the framebuffer in pixels.
+- altr,mem-port-width: the bus width of the avalon master port
+	on the frame reader
+
+Example:
+----------------------------
+       dp_0_frame_buf: display-controller@100000280 {
+                       compatible = "altr,vip-frame-buffer-2.0";
+                       reg = <0x00000001 0x00000280 0x00000040>;
+                       altr,max-width = <1280>;
+                       altr,max-height = <720>;
+                       altr,mem-port-width = <128>;
+       };
-- 
2.7.4

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[PATCHv6 1/3] ARM:dt-bindings Intel FPGA Video and Image Processing Suite

[Hean-Loong, Ong]

From: Ong Hean Loong <hean.loong.ong@intel.com>

Device tree binding for Intel FPGA Video and Image
Processing Suite. The binding involved would be generated
from the Altera (Intel) Qsys system. The bindings would
set the max width, max height, buts per pixel and memory
port width. The device tree binding only supports the Intel
Arria10 devkit and its variants. Vendor name retained as
altr.

Signed-off-by: Ong, Hean Loong <hean.loong.ong@intel.com>
---
V6:
Fix comments for description

V5:
*Fix comments on description
*remove bindings for bits per symbol as it has only one value which is 8

V4:
*Fix comments on description

V3:
*Fix comments on description

V2:
*Fix comments on description

V1:
*Fix comments on description
---
---
 .../devicetree/bindings/display/altr,vip-fb2.txt   | 42 ++++++++++++++++++++++
 1 file changed, 42 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/display/altr,vip-fb2.txt

diff --git a/Documentation/devicetree/bindings/display/altr,vip-fb2.txt b/Documentation/devicetree/bindings/display/altr,vip-fb2.txt
new file mode 100644
index 0000000..57d8869
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/altr,vip-fb2.txt
@@ -0,0 +1,42 @@
+Intel Video and Image Processing(VIP) Frame Buffer II bindings
+
+Supported hardware: Intel FPGA SoC Arria10 and above with display port IP
+
+The hardware associated with this device tree is a SoC FPGA.
+Where there is an microprocessor and a FPGA device.
+The microprocessor would host the OS while the FPGA device runs
+on its individual IP firmware. The Intel VIP Frame Buffer II
+system would be driving data from the to the FPGA device
+programmed with the Frame Buffer II IP to render pixels to be streamed
+to the Display Port connector.
+
+The Frame Buffer II device is a simple frame buffer device. The device
+contains the display properties and the bridge or connector register.
+The output for this device currently is a dedicated to a single Display Port.
+Currently the max resolution supported is 1280 x 720 at 60Hz.
+
+More information the FPGA video IP component can be acquired from
+https://www.altera.com/content/dam/altera-www/global/en_US/pdfs\
+/literature/ug/ug_vip.pdf
+
+New bindings:
+=============
+Required properties:
+----------------------------
+- compatible: "altr,vip-frame-buffer-2.0"
+- reg: Physical base address and length of the framebuffer controller's
+	registers.
+- altr,max-width: The maximum width of the framebuffer in pixels.
+- altr,max-height: The maximum height of the framebuffer in pixels.
+- altr,mem-port-width: the bus width of the avalon master port
+	on the frame reader
+
+Example:
+----------------------------
+       dp_0_frame_buf: display-controller@100000280 {
+                       compatible = "altr,vip-frame-buffer-2.0";
+                       reg = <0x00000001 0x00000280 0x00000040>;
+                       altr,max-width = <1280>;
+                       altr,max-height = <720>;
+                       altr,mem-port-width = <128>;
+       };
-- 
2.7.4

[PATCHv6 1/3] ARM:dt-bindings Intel FPGA Video and Image Processing Suite

[Rob Herring]

On Fri, Aug 11, 2017 at 02:49:45PM +0800, Hean-Loong, Ong wrote:
> From: Ong Hean Loong <hean.loong.ong@intel.com>

"dt-bindings: display: ..." for the subject. With that,

Acked-by: Rob Herring <robh@kernel.org>

> 
> Device tree binding for Intel FPGA Video and Image
> Processing Suite. The binding involved would be generated
> from the Altera (Intel) Qsys system. The bindings would
> set the max width, max height, buts per pixel and memory
> port width. The device tree binding only supports the Intel
> Arria10 devkit and its variants. Vendor name retained as
> altr.
> 
> Signed-off-by: Ong, Hean Loong <hean.loong.ong@intel.com>
> ---
> V6:
> Fix comments for description

A completely useless version history. You should describe the diff 
between versions.

> 
> V5:
> *Fix comments on description
> *remove bindings for bits per symbol as it has only one value which is 8
> 
> V4:
> *Fix comments on description
> 
> V3:
> *Fix comments on description
> 
> V2:
> *Fix comments on description
> 
> V1:
> *Fix comments on description
> ---
> ---
>  .../devicetree/bindings/display/altr,vip-fb2.txt   | 42 ++++++++++++++++++++++
>  1 file changed, 42 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/display/altr,vip-fb2.txt

Re: [PATCHv6 1/3] ARM:dt-bindings Intel FPGA Video and Image Processing Suite

[Rob Herring]

On Fri, Aug 11, 2017 at 02:49:45PM +0800, Hean-Loong, Ong wrote:
> From: Ong Hean Loong <hean.loong.ong@intel.com>

"dt-bindings: display: ..." for the subject. With that,

Acked-by: Rob Herring <robh@kernel.org>

> 
> Device tree binding for Intel FPGA Video and Image
> Processing Suite. The binding involved would be generated
> from the Altera (Intel) Qsys system. The bindings would
> set the max width, max height, buts per pixel and memory
> port width. The device tree binding only supports the Intel
> Arria10 devkit and its variants. Vendor name retained as
> altr.
> 
> Signed-off-by: Ong, Hean Loong <hean.loong.ong@intel.com>
> ---
> V6:
> Fix comments for description

A completely useless version history. You should describe the diff 
between versions.

> 
> V5:
> *Fix comments on description
> *remove bindings for bits per symbol as it has only one value which is 8
> 
> V4:
> *Fix comments on description
> 
> V3:
> *Fix comments on description
> 
> V2:
> *Fix comments on description
> 
> V1:
> *Fix comments on description
> ---
> ---
>  .../devicetree/bindings/display/altr,vip-fb2.txt   | 42 ++++++++++++++++++++++
>  1 file changed, 42 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/display/altr,vip-fb2.txt

Re: [PATCHv6 1/3] ARM:dt-bindings Intel FPGA Video and Image Processing Suite

[Rob Herring]

On Fri, Aug 11, 2017 at 02:49:45PM +0800, Hean-Loong, Ong wrote:
> From: Ong Hean Loong <hean.loong.ong-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>

"dt-bindings: display: ..." for the subject. With that,

Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>

> 
> Device tree binding for Intel FPGA Video and Image
> Processing Suite. The binding involved would be generated
> from the Altera (Intel) Qsys system. The bindings would
> set the max width, max height, buts per pixel and memory
> port width. The device tree binding only supports the Intel
> Arria10 devkit and its variants. Vendor name retained as
> altr.
> 
> Signed-off-by: Ong, Hean Loong <hean.loong.ong-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
> ---
> V6:
> Fix comments for description

A completely useless version history. You should describe the diff 
between versions.

> 
> V5:
> *Fix comments on description
> *remove bindings for bits per symbol as it has only one value which is 8
> 
> V4:
> *Fix comments on description
> 
> V3:
> *Fix comments on description
> 
> V2:
> *Fix comments on description
> 
> V1:
> *Fix comments on description
> ---
> ---
>  .../devicetree/bindings/display/altr,vip-fb2.txt   | 42 ++++++++++++++++++++++
>  1 file changed, 42 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/display/altr,vip-fb2.txt
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[PATCHv6 1/3] ARM:dt-bindings Intel FPGA Video and Image Processing Suite

[Ong, Hean Loong]

On Thu, 2017-08-17 at 10:22 -0500, Rob Herring wrote:
> On Fri, Aug 11, 2017 at 02:49:45PM +0800, Hean-Loong, Ong wrote:
> > 
> > From: Ong Hean Loong <hean.loong.ong@intel.com>
> "dt-bindings: display: ..." for the subject. With that,
> 
> Acked-by: Rob Herring <robh@kernel.org>
> 
> > 
> > 
> > Device tree binding for Intel FPGA Video and Image
> > Processing Suite. The binding involved would be generated
> > from the Altera (Intel) Qsys system. The bindings would
> > set the max width, max height, buts per pixel and memory
> > port width. The device tree binding only supports the Intel
> > Arria10 devkit and its variants. Vendor name retained as
> > altr.
> > 
> > Signed-off-by: Ong, Hean Loong <hean.loong.ong@intel.com>
> > ---
> > V6:
> > Fix comments for description
> A completely useless version history. You should describe the diff?
> between versions.
> 
Noted. Would make the necessary changes
> > 
> > 
> > V5:
> > *Fix comments on description
> > *remove bindings for bits per symbol as it has only one value which
> > is 8
> > 
> > V4:
> > *Fix comments on description
> > 
> > V3:
> > *Fix comments on description
> > 
> > V2:
> > *Fix comments on description
> > 
> > V1:
> > *Fix comments on description
> > ---
> > ---
> > ?.../devicetree/bindings/display/altr,vip-fb2.txt???| 42
> > ++++++++++++++++++++++
> > ?1 file changed, 42 insertions(+)
> > ?create mode 100644
> > Documentation/devicetree/bindings/display/altr,vip-fb2.txt

Re: [PATCHv6 1/3] ARM:dt-bindings Intel FPGA Video and Image Processing Suite

[Ong, Hean Loong]

On Thu, 2017-08-17 at 10:22 -0500, Rob Herring wrote:
> On Fri, Aug 11, 2017 at 02:49:45PM +0800, Hean-Loong, Ong wrote:
> > 
> > From: Ong Hean Loong <hean.loong.ong@intel.com>
> "dt-bindings: display: ..." for the subject. With that,
> 
> Acked-by: Rob Herring <robh@kernel.org>
> 
> > 
> > 
> > Device tree binding for Intel FPGA Video and Image
> > Processing Suite. The binding involved would be generated
> > from the Altera (Intel) Qsys system. The bindings would
> > set the max width, max height, buts per pixel and memory
> > port width. The device tree binding only supports the Intel
> > Arria10 devkit and its variants. Vendor name retained as
> > altr.
> > 
> > Signed-off-by: Ong, Hean Loong <hean.loong.ong@intel.com>
> > ---
> > V6:
> > Fix comments for description
> A completely useless version history. You should describe the diff 
> between versions.
> 
Noted. Would make the necessary changes
> > 
> > 
> > V5:
> > *Fix comments on description
> > *remove bindings for bits per symbol as it has only one value which
> > is 8
> > 
> > V4:
> > *Fix comments on description
> > 
> > V3:
> > *Fix comments on description
> > 
> > V2:
> > *Fix comments on description
> > 
> > V1:
> > *Fix comments on description
> > ---
> > ---
> >  .../devicetree/bindings/display/altr,vip-fb2.txt   | 42
> > ++++++++++++++++++++++
> >  1 file changed, 42 insertions(+)
> >  create mode 100644
> > Documentation/devicetree/bindings/display/altr,vip-fb2.txt

Re: [PATCHv6 1/3] ARM:dt-bindings Intel FPGA Video and Image Processing Suite

[Ong, Hean Loong]

On Thu, 2017-08-17 at 10:22 -0500, Rob Herring wrote:
> On Fri, Aug 11, 2017 at 02:49:45PM +0800, Hean-Loong, Ong wrote:
> > 
> > From: Ong Hean Loong <hean.loong.ong@intel.com>
> "dt-bindings: display: ..." for the subject. With that,
> 
> Acked-by: Rob Herring <robh@kernel.org>
> 
> > 
> > 
> > Device tree binding for Intel FPGA Video and Image
> > Processing Suite. The binding involved would be generated
> > from the Altera (Intel) Qsys system. The bindings would
> > set the max width, max height, buts per pixel and memory
> > port width. The device tree binding only supports the Intel
> > Arria10 devkit and its variants. Vendor name retained as
> > altr.
> > 
> > Signed-off-by: Ong, Hean Loong <hean.loong.ong@intel.com>
> > ---
> > V6:
> > Fix comments for description
> A completely useless version history. You should describe the diff 
> between versions.
> 
Noted. Would make the necessary changes
> > 
> > 
> > V5:
> > *Fix comments on description
> > *remove bindings for bits per symbol as it has only one value which
> > is 8
> > 
> > V4:
> > *Fix comments on description
> > 
> > V3:
> > *Fix comments on description
> > 
> > V2:
> > *Fix comments on description
> > 
> > V1:
> > *Fix comments on description
> > ---
> > ---
> >  .../devicetree/bindings/display/altr,vip-fb2.txt   | 42
> > ++++++++++++++++++++++
> >  1 file changed, 42 insertions(+)
> >  create mode 100644
> > Documentation/devicetree/bindings/display/altr,vip-fb2.txt

[PATCHv6 2/3] ARM:socfpga-defconfig Intel FPGA Video and Image Processing Suite

[Hean-Loong, Ong]

From: Ong Hean Loong <hean.loong.ong@intel.com>

Intel FPGA Video and Image Processing Suite Frame Buffer II
driver config for Arria 10 devkit and its variants

Signed-off-by: Ong, Hean Loong <hean.loong.ong@intel.com>
---
 arch/arm/configs/socfpga_defconfig | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm/configs/socfpga_defconfig b/arch/arm/configs/socfpga_defconfig
index 2620ce7..255f553 100644
--- a/arch/arm/configs/socfpga_defconfig
+++ b/arch/arm/configs/socfpga_defconfig
@@ -111,6 +111,12 @@ CONFIG_MFD_ALTERA_A10SR=y
 CONFIG_MFD_STMPE=y
 CONFIG_REGULATOR=y
 CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_DRM=m
+CONFIG_DRM_IVIP=m
+CONFIG_DRM_IVIP_OF=m
+CONFIG_FB=y
+CONFIG_FB_SIMPLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=m
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_DWC2=y
-- 
2.7.4

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[PATCHv6 2/3] ARM:socfpga-defconfig Intel FPGA Video and Image Processing Suite

[Hean-Loong, Ong]

From: Ong Hean Loong <hean.loong.ong@intel.com>

Intel FPGA Video and Image Processing Suite Frame Buffer II
driver config for Arria 10 devkit and its variants

Signed-off-by: Ong, Hean Loong <hean.loong.ong@intel.com>
---
 arch/arm/configs/socfpga_defconfig | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm/configs/socfpga_defconfig b/arch/arm/configs/socfpga_defconfig
index 2620ce7..255f553 100644
--- a/arch/arm/configs/socfpga_defconfig
+++ b/arch/arm/configs/socfpga_defconfig
@@ -111,6 +111,12 @@ CONFIG_MFD_ALTERA_A10SR=y
 CONFIG_MFD_STMPE=y
 CONFIG_REGULATOR=y
 CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_DRM=m
+CONFIG_DRM_IVIP=m
+CONFIG_DRM_IVIP_OF=m
+CONFIG_FB=y
+CONFIG_FB_SIMPLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=m
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_DWC2=y
-- 
2.7.4

[PATCHv6 3/3] ARM:drm ivip Intel FPGA Video and Image Processing Suite

[Hean-Loong, Ong]

From: Ong Hean Loong <hean.loong.ong@intel.com>

Driver for Intel FPGA Video and Image Processing Suite Frame Buffer II.
The driver only supports the Intel Arria10 devkit and its variants.
This driver can be either loaded staticlly or in modules.
The OF device tree binding is located at:
Documentation/devicetree/bindings/display/altr,vip-fb2.txt

Signed-off-by: Ong Hean Loong <hean.loong.ong@intel.com>
---
V6:
*Fix Comments for Makefile and Kconfig

V5:
*Fix Comments

V4:
*Fix Comments

V3:
*Changes to fixing drm_simple_pipe
*Used drm_fb_cma_get_gem_addr

V2:
*Adding drm_simple_display_pipe_init

---
---
 drivers/gpu/drm/Kconfig               |   2 +
 drivers/gpu/drm/Makefile              |   1 +
 drivers/gpu/drm/ivip/Kconfig          |  14 +++
 drivers/gpu/drm/ivip/Makefile         |   9 ++
 drivers/gpu/drm/ivip/intel_vip_conn.c |  96 +++++++++++++++++
 drivers/gpu/drm/ivip/intel_vip_core.c | 162 ++++++++++++++++++++++++++++
 drivers/gpu/drm/ivip/intel_vip_drv.h  |  52 +++++++++
 drivers/gpu/drm/ivip/intel_vip_of.c   | 194 ++++++++++++++++++++++++++++++++++
 8 files changed, 530 insertions(+)
 create mode 100644 drivers/gpu/drm/ivip/Kconfig
 create mode 100644 drivers/gpu/drm/ivip/Makefile
 create mode 100644 drivers/gpu/drm/ivip/intel_vip_conn.c
 create mode 100644 drivers/gpu/drm/ivip/intel_vip_core.c
 create mode 100644 drivers/gpu/drm/ivip/intel_vip_drv.h
 create mode 100644 drivers/gpu/drm/ivip/intel_vip_of.c

diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig
index 83cb2a8..38a184d 100644
--- a/drivers/gpu/drm/Kconfig
+++ b/drivers/gpu/drm/Kconfig
@@ -195,6 +195,8 @@ source "drivers/gpu/drm/nouveau/Kconfig"
 
 source "drivers/gpu/drm/i915/Kconfig"
 
+source "drivers/gpu/drm/ivip/Kconfig"
+
 config DRM_VGEM
 	tristate "Virtual GEM provider"
 	depends on DRM
diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile
index 24a066e..4162a0e 100644
--- a/drivers/gpu/drm/Makefile
+++ b/drivers/gpu/drm/Makefile
@@ -58,6 +58,7 @@ obj-$(CONFIG_DRM_AMDGPU)+= amd/amdgpu/
 obj-$(CONFIG_DRM_MGA)	+= mga/
 obj-$(CONFIG_DRM_I810)	+= i810/
 obj-$(CONFIG_DRM_I915)	+= i915/
+obj-$(CONFIG_DRM_IVIP) += ivip/
 obj-$(CONFIG_DRM_MGAG200) += mgag200/
 obj-$(CONFIG_DRM_VC4)  += vc4/
 obj-$(CONFIG_DRM_CIRRUS_QEMU) += cirrus/
diff --git a/drivers/gpu/drm/ivip/Kconfig b/drivers/gpu/drm/ivip/Kconfig
new file mode 100644
index 0000000..398c9ab
--- /dev/null
+++ b/drivers/gpu/drm/ivip/Kconfig
@@ -0,0 +1,14 @@
+config DRM_IVIP
+        tristate "Intel FGPA Video and Image Processing"
+        depends on DRM && OF
+        select DRM_GEM_CMA_HELPER
+        select DRM_KMS_HELPER
+        select DRM_KMS_FB_HELPER
+        select DRM_KMS_CMA_HELPER
+        help
+            Choose this option if you have a Intel FPGA Arria 10 system
+            and above with an Intel Display Port IP. This does not support
+            legacy Intel FPGA Cyclone V display port. Currently only single
+            frame buffer is supported. Note that ACPI and X_86 architecture
+            is not supported for Arria10.If M is selected the module will be
+            called ivip.
diff --git a/drivers/gpu/drm/ivip/Makefile b/drivers/gpu/drm/ivip/Makefile
new file mode 100644
index 0000000..cc55b04
--- /dev/null
+++ b/drivers/gpu/drm/ivip/Makefile
@@ -0,0 +1,9 @@
+#
+# Makefile for the drm device driver.  This driver provides support for the
+# Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher.
+
+ccflags-y := -Iinclude/drm
+
+obj-$(CONFIG_DRM_IVIP) += ivip.o
+ivip-objs := intel_vip_of.o intel_vip_core.o \
+	intel_vip_conn.o
diff --git a/drivers/gpu/drm/ivip/intel_vip_conn.c b/drivers/gpu/drm/ivip/intel_vip_conn.c
new file mode 100644
index 0000000..c88df23
--- /dev/null
+++ b/drivers/gpu/drm/ivip/intel_vip_conn.c
@@ -0,0 +1,96 @@
+/*
+ * intel_vip_conn.c -- Intel Video and Image Processing(VIP)
+ * Frame Buffer II driver
+ *
+ * This driver supports the Intel VIP Frame Reader component.
+ * More info on the hardware can be found in the Intel Video
+ * and Image Processing Suite User Guide at this address
+ * http://www.altera.com/literature/ug/ug_vip.pdf.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * Authors:
+ * Ong, Hean-Loong <hean.loong.ong@intel.com>
+ *
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <drm/drm_atomic_helper.h>
+#include <drm/drm_crtc_helper.h>
+#include <drm/drm_encoder_slave.h>
+#include <drm/drm_plane_helper.h>
+
+static enum drm_connector_status
+intelvipfb_drm_connector_detect(struct drm_connector *connector, bool force)
+{
+	return connector_status_connected;
+}
+
+static void intelvipfb_drm_connector_destroy(struct drm_connector *connector)
+{
+	drm_connector_unregister(connector);
+	drm_connector_cleanup(connector);
+}
+
+static const struct drm_connector_funcs intelvipfb_drm_connector_funcs = {
+	.dpms = drm_atomic_helper_connector_dpms,
+	.reset = drm_atomic_helper_connector_reset,
+	.detect = intelvipfb_drm_connector_detect,
+	.fill_modes = drm_helper_probe_single_connector_modes,
+	.destroy = intelvipfb_drm_connector_destroy,
+	.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
+	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
+};
+
+static int intelvipfb_drm_connector_get_modes(struct drm_connector *connector)
+{
+	struct drm_device *drm = connector->dev;
+	int count;
+
+	count = drm_add_modes_noedid(connector, drm->mode_config.max_width,
+			drm->mode_config.max_height);
+	drm_set_preferred_mode(connector, drm->mode_config.max_width,
+			drm->mode_config.max_height);
+	return count;
+}
+
+static const struct drm_connector_helper_funcs
+intelvipfb_drm_connector_helper_funcs = {
+	.get_modes = intelvipfb_drm_connector_get_modes,
+};
+
+struct drm_connector *
+intelvipfb_conn_setup(struct drm_device *drm)
+{
+	struct drm_connector *conn;
+	int ret;
+
+	conn = devm_kzalloc(drm->dev, sizeof(*conn), GFP_KERNEL);
+	if (IS_ERR(conn))
+		return NULL;
+
+	ret = drm_connector_init(drm, conn, &intelvipfb_drm_connector_funcs,
+			DRM_MODE_CONNECTOR_DisplayPort);
+	if (ret < 0) {
+		dev_err(drm->dev, "failed to initialize drm connector\n");
+		ret = -ENOMEM;
+		goto error_connector_cleanup;
+	}
+
+	drm_connector_helper_add(conn, &intelvipfb_drm_connector_helper_funcs);
+
+	return conn;
+
+error_connector_cleanup:
+	drm_connector_cleanup(conn);
+
+	return NULL;
+}
diff --git a/drivers/gpu/drm/ivip/intel_vip_core.c b/drivers/gpu/drm/ivip/intel_vip_core.c
new file mode 100644
index 0000000..6b43c13
--- /dev/null
+++ b/drivers/gpu/drm/ivip/intel_vip_core.c
@@ -0,0 +1,162 @@
+/*
+ * intel_vip_core.c -- Intel Video and Image Processing(VIP)
+ * Frame Buffer II driver
+ *
+ * This driver supports the Intel VIP Frame Reader component.
+ * More info on the hardware can be found in the Intel Video
+ * and Image Processing Suite User Guide at this address
+ * http://www.altera.com/literature/ug/ug_vip.pdf.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * Authors:
+ * Ong, Hean-Loong <hean.loong.ong@intel.com>
+ *
+ */
+
+#include <drm/drmP.h>
+#include <drm/drm_atomic.h>
+#include <drm/drm_atomic_helper.h>
+#include <drm/drm_crtc_helper.h>
+#include <drm/drm_fb_helper.h>
+#include <drm/drm_fb_cma_helper.h>
+#include <drm/drm_gem_cma_helper.h>
+#include <drm/drm_plane_helper.h>
+#include <drm/drm_simple_kms_helper.h>
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+
+#include "intel_vip_drv.h"
+
+static void intelvipfb_enable(struct drm_simple_display_pipe *pipe,
+	       struct drm_crtc_state *crtc_state)
+{
+	/*
+	 * The frameinfo variable has to correspond to the size of the VIP Suite
+	 * Frame Reader register 7 which will determine the maximum size used
+	 * in this frameinfo
+	 */
+
+	u32 frameinfo;
+	struct intelvipfb_priv *priv = pipe->plane.dev->dev_private;
+	void __iomem *base = priv->base;
+	struct drm_plane_state *state = pipe->plane.state;
+	dma_addr_t addr;
+
+	addr = drm_fb_cma_get_gem_addr(state->fb, state, 0);
+
+	dev_info(pipe->plane.dev->dev, "Address 0x%x\n", addr);
+
+	frameinfo =
+		readl(base + INTELVIPFB_FRAME_READER) & 0x00ffffff;
+	writel(frameinfo, base + INTELVIPFB_FRAME_INFO);
+	writel(addr, base + INTELVIPFB_FRAME_START);
+	/* Finally set the control register to 1 to start streaming */
+	writel(1, base + INTELVIPFB_CONTROL);
+}
+
+static void intelvipfb_disable(struct drm_simple_display_pipe *pipe)
+{
+	struct intelvipfb_priv *priv = pipe->plane.dev->dev_private;
+	void __iomem *base = priv->base;
+	/* set the control register to 0 to stop streaming */
+	writel(0, base + INTELVIPFB_CONTROL);
+}
+
+static const struct drm_mode_config_funcs intelvipfb_mode_config_funcs = {
+	.fb_create = drm_fb_cma_create,
+	.atomic_check = drm_atomic_helper_check,
+	.atomic_commit = drm_atomic_helper_commit,
+};
+
+static void intelvipfb_setup_mode_config(struct drm_device *drm)
+{
+	drm_mode_config_init(drm);
+	drm->mode_config.funcs = &intelvipfb_mode_config_funcs;
+}
+
+static int intelvipfb_pipe_prepare_fb(struct drm_simple_display_pipe *pipe,
+					struct drm_plane_state *plane_state)
+{
+	return drm_fb_cma_prepare_fb(&pipe->plane, plane_state);
+}
+
+
+static struct drm_simple_display_pipe_funcs fbpriv_funcs = {
+	.prepare_fb = intelvipfb_pipe_prepare_fb,
+	.enable = intelvipfb_enable,
+	.disable = intelvipfb_disable
+};
+
+int intelvipfb_probe(struct device *dev)
+{
+	int retval;
+	struct drm_device *drm;
+	struct intelvipfb_priv *fbpriv = dev_get_drvdata(dev);
+	struct drm_connector *connector;
+	u32 formats[] = {DRM_FORMAT_XRGB8888};
+
+	drm = fbpriv->drm;
+
+	drm->dev_private = fbpriv;
+
+	intelvipfb_setup_mode_config(drm);
+
+	connector = intelvipfb_conn_setup(drm);
+	if (!connector) {
+		dev_err(drm->dev, "Connector setup failed\n");
+		goto err_mode_config;
+	}
+
+	retval = drm_simple_display_pipe_init(drm, &fbpriv->pipe,
+			&fbpriv_funcs, formats,
+			ARRAY_SIZE(formats), connector);
+	if (retval < 0) {
+		dev_err(drm->dev, "Cannot setup simple display pipe\n");
+		goto err_mode_config;
+	}
+
+	fbpriv->fbcma = drm_fbdev_cma_init(drm,
+			drm->mode_config.preferred_depth,
+			drm->mode_config.num_connector);
+
+	drm_mode_config_reset(drm);
+
+	drm_dev_register(drm, 0);
+
+	return retval;
+
+err_mode_config:
+
+	drm_mode_config_cleanup(drm);
+	return -ENODEV;
+}
+
+int intelvipfb_remove(struct device *dev)
+{
+	struct intelvipfb_priv *fbpriv = dev_get_drvdata(dev);
+	struct drm_device *drm =  fbpriv->drm;
+
+	drm_dev_unregister(drm);
+
+	if (fbpriv->fbcma)
+		drm_fbdev_cma_fini(fbpriv->fbcma);
+
+	drm_mode_config_cleanup(drm);
+	drm_dev_unref(drm);
+
+	return 0;
+}
+
+MODULE_AUTHOR("Ong, Hean-Loong <hean.loong.ong@intel.com>");
+MODULE_DESCRIPTION("Intel VIP Frame Buffer II driver");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/gpu/drm/ivip/intel_vip_drv.h b/drivers/gpu/drm/ivip/intel_vip_drv.h
new file mode 100644
index 0000000..0a3555d
--- /dev/null
+++ b/drivers/gpu/drm/ivip/intel_vip_drv.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright (C) 2017 Intel Corporation.
+ *
+ * Intel Video and Image Processing(VIP) Frame Buffer II driver.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ * Authors:
+ * Ong, Hean-Loong <hean.loong.ong@intel.com>
+ *
+ */
+#ifndef _INTEL_VIP_DRV_H
+#define _INTEL_VIP_DRV_H
+
+#define DRIVER_NAME    "intelvipfb"
+#define BYTES_PER_PIXEL	 4
+#define CRTC_NUM	        1
+#define CONN_NUM	        1
+
+/* control registers */
+#define INTELVIPFB_CONTROL	      0
+#define INTELVIPFB_STATUS	       0x4
+#define INTELVIPFB_INTERRUPT	    0x8
+#define INTELVIPFB_FRAME_COUNTER	0xC
+#define INTELVIPFB_FRAME_DROP	   0x10
+#define INTELVIPFB_FRAME_INFO	   0x14
+#define INTELVIPFB_FRAME_START	  0x18
+#define INTELVIPFB_FRAME_READER	         0x1C
+
+int intelvipfb_probe(struct device *dev);
+int intelvipfb_remove(struct device *dev);
+int intelvipfb_setup_crtc(struct drm_device *drm);
+struct drm_connector *intelvipfb_conn_setup(struct drm_device *drm);
+
+struct intelvipfb_priv {
+	struct drm_simple_display_pipe pipe;
+	struct drm_fbdev_cma *fbcma;
+	struct drm_device *drm;
+	void    __iomem *base;
+};
+
+#endif
diff --git a/drivers/gpu/drm/ivip/intel_vip_of.c b/drivers/gpu/drm/ivip/intel_vip_of.c
new file mode 100644
index 0000000..b46f789
--- /dev/null
+++ b/drivers/gpu/drm/ivip/intel_vip_of.c
@@ -0,0 +1,194 @@
+/*
+ * intel_vip_of.c -- Intel Video and Image Processing(VIP)
+ * Frame Buffer II driver
+ *
+ * This driver supports the Intel VIP Frame Reader component.
+ * More info on the hardware can be found in the Intel Video
+ * and Image Processing Suite User Guide at this address
+ * http://www.altera.com/literature/ug/ug_vip.pdf.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * Authors:
+ * Ong, Hean-Loong <hean.loong.ong@intel.com>
+ *
+ */
+#include <drm/drm_fb_helper.h>
+#include <drm/drm_fb_cma_helper.h>
+#include <drm/drm_gem_cma_helper.h>
+#include <drm/drm_of.h>
+#include <drm/drm_simple_kms_helper.h>
+
+#include <linux/component.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+
+#include "intel_vip_drv.h"
+
+DEFINE_DRM_GEM_CMA_FOPS(drm_fops);
+
+static void intelvipfb_lastclose(struct drm_device *drm)
+{
+	struct intelvipfb_priv *priv = drm->dev_private;
+
+	drm_fbdev_cma_restore_mode(priv->fbcma);
+}
+
+static struct drm_driver intelvipfb_drm = {
+	.driver_features =
+			DRIVER_MODESET | DRIVER_GEM |
+			DRIVER_PRIME | DRIVER_ATOMIC,
+	.gem_free_object_unlocked = drm_gem_cma_free_object,
+	.gem_vm_ops = &drm_gem_cma_vm_ops,
+	.dumb_create = drm_gem_cma_dumb_create,
+	.dumb_map_offset = drm_gem_cma_dumb_map_offset,
+	.dumb_destroy = drm_gem_dumb_destroy,
+	.prime_handle_to_fd = drm_gem_prime_handle_to_fd,
+	.prime_fd_to_handle = drm_gem_prime_fd_to_handle,
+	.gem_prime_export = drm_gem_prime_export,
+	.gem_prime_import = drm_gem_prime_import,
+	.gem_prime_get_sg_table = drm_gem_cma_prime_get_sg_table,
+	.gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table,
+	.gem_prime_vmap = drm_gem_cma_prime_vmap,
+	.gem_prime_vunmap = drm_gem_cma_prime_vunmap,
+	.gem_prime_mmap = drm_gem_cma_prime_mmap,
+	.lastclose = intelvipfb_lastclose,
+	.name = DRIVER_NAME,
+	.date = "20170729",
+	.desc = "Intel FPGA VIP SUITE",
+	.major = 1,
+	.minor = 0,
+	.ioctls = NULL,
+	.patchlevel = 0,
+	.fops = &drm_fops,
+};
+
+/*
+ * Setting up information derived from OF Device Tree Nodes
+ * max-width, max-height, bits per pixel, memory port width
+ */
+
+static int intelvipfb_drm_setup(struct device *dev,
+				struct intelvipfb_priv *fbpriv)
+{
+	struct drm_device *drm = fbpriv->drm;
+	struct device_node *np = dev->of_node;
+	int mem_word_width;
+	int max_h, max_w;
+	int ret;
+
+	ret = of_property_read_u32(np, "altr,max-width", &max_w);
+	if (ret) {
+		dev_err(dev,
+			"Missing required parameter 'altr,max-width'");
+		return ret;
+	}
+
+	ret = of_property_read_u32(np, "altr,max-height", &max_h);
+	if (ret) {
+		dev_err(dev,
+			"Missing required parameter 'altr,max-height'");
+		return ret;
+	}
+
+	ret = of_property_read_u32(np, "altr,mem-port-width", &mem_word_width);
+	if (ret) {
+		dev_err(dev, "Missing required parameter 'altr,mem-port-width '");
+		return ret;
+	}
+
+	if (!(mem_word_width >= 32 && mem_word_width % 32 == 0)) {
+		dev_err(dev,
+			"mem-word-width is set to %i. must be >= 32 and multiple of 32.",
+			 mem_word_width);
+		return -ENODEV;
+	}
+
+	drm->mode_config.min_width = 640;
+	drm->mode_config.min_height = 480;
+	drm->mode_config.max_width = max_w;
+	drm->mode_config.max_height = max_h;
+	drm->mode_config.preferred_depth = 32;
+
+	return 0;
+}
+
+static int intelvipfb_of_probe(struct platform_device *pdev)
+{
+	int retval;
+	struct resource *reg_res;
+	struct intelvipfb_priv *fbpriv;
+	struct device *dev = &pdev->dev;
+	struct drm_device *drm;
+
+	fbpriv = devm_kzalloc(dev, sizeof(*fbpriv), GFP_KERNEL);
+	if (!fbpriv)
+		return -ENOMEM;
+
+	/*setup DRM */
+	drm = drm_dev_alloc(&intelvipfb_drm, dev);
+	if (IS_ERR(drm))
+		return PTR_ERR(drm);
+
+	retval = dma_set_mask_and_coherent(drm->dev, DMA_BIT_MASK(32));
+	if (retval)
+		return -ENODEV;
+
+	fbpriv->drm = drm;
+
+	reg_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!reg_res)
+		return -ENOMEM;
+
+	fbpriv->base = devm_ioremap_resource(dev, reg_res);
+
+	if (IS_ERR(fbpriv->base)) {
+		dev_err(dev, "devm_ioremap_resource failed\n");
+		retval = PTR_ERR(fbpriv->base);
+		return -ENOMEM;
+	}
+
+	intelvipfb_drm_setup(dev, fbpriv);
+
+	dev_set_drvdata(dev, fbpriv);
+
+	return intelvipfb_probe(dev);
+}
+
+static int intelvipfb_of_remove(struct platform_device *pdev)
+{
+	return intelvipfb_remove(&pdev->dev);
+}
+
+/*
+ * The name vip-frame-buffer-2.0 is derived from
+ * http://www.altera.com/literature/ug/ug_vip.pdf
+ * frame buffer IP cores section 14
+ */
+
+static const struct of_device_id intelvipfb_of_match[] = {
+	{ .compatible = "altr,vip-frame-buffer-2.0" },
+	{},
+};
+
+MODULE_DEVICE_TABLE(of, intelvipfb_of_match);
+
+static struct platform_driver intelvipfb_driver = {
+	.probe = intelvipfb_of_probe,
+	.remove = intelvipfb_of_remove,
+	.driver = {
+		.name = DRIVER_NAME,
+		.of_match_table = intelvipfb_of_match,
+	},
+};
+
+module_platform_driver(intelvipfb_driver);
-- 
2.7.4

[PATCHv6 3/3] ARM:drm ivip Intel FPGA Video and Image Processing Suite

[Hean-Loong, Ong]

From: Ong Hean Loong <hean.loong.ong@intel.com>

Driver for Intel FPGA Video and Image Processing Suite Frame Buffer II.
The driver only supports the Intel Arria10 devkit and its variants.
This driver can be either loaded staticlly or in modules.
The OF device tree binding is located at:
Documentation/devicetree/bindings/display/altr,vip-fb2.txt

Signed-off-by: Ong Hean Loong <hean.loong.ong@intel.com>
---
V6:
*Fix Comments for Makefile and Kconfig

V5:
*Fix Comments

V4:
*Fix Comments

V3:
*Changes to fixing drm_simple_pipe
*Used drm_fb_cma_get_gem_addr

V2:
*Adding drm_simple_display_pipe_init

---
---
 drivers/gpu/drm/Kconfig               |   2 +
 drivers/gpu/drm/Makefile              |   1 +
 drivers/gpu/drm/ivip/Kconfig          |  14 +++
 drivers/gpu/drm/ivip/Makefile         |   9 ++
 drivers/gpu/drm/ivip/intel_vip_conn.c |  96 +++++++++++++++++
 drivers/gpu/drm/ivip/intel_vip_core.c | 162 ++++++++++++++++++++++++++++
 drivers/gpu/drm/ivip/intel_vip_drv.h  |  52 +++++++++
 drivers/gpu/drm/ivip/intel_vip_of.c   | 194 ++++++++++++++++++++++++++++++++++
 8 files changed, 530 insertions(+)
 create mode 100644 drivers/gpu/drm/ivip/Kconfig
 create mode 100644 drivers/gpu/drm/ivip/Makefile
 create mode 100644 drivers/gpu/drm/ivip/intel_vip_conn.c
 create mode 100644 drivers/gpu/drm/ivip/intel_vip_core.c
 create mode 100644 drivers/gpu/drm/ivip/intel_vip_drv.h
 create mode 100644 drivers/gpu/drm/ivip/intel_vip_of.c

diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig
index 83cb2a8..38a184d 100644
--- a/drivers/gpu/drm/Kconfig
+++ b/drivers/gpu/drm/Kconfig
@@ -195,6 +195,8 @@ source "drivers/gpu/drm/nouveau/Kconfig"
 
 source "drivers/gpu/drm/i915/Kconfig"
 
+source "drivers/gpu/drm/ivip/Kconfig"
+
 config DRM_VGEM
 	tristate "Virtual GEM provider"
 	depends on DRM
diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile
index 24a066e..4162a0e 100644
--- a/drivers/gpu/drm/Makefile
+++ b/drivers/gpu/drm/Makefile
@@ -58,6 +58,7 @@ obj-$(CONFIG_DRM_AMDGPU)+= amd/amdgpu/
 obj-$(CONFIG_DRM_MGA)	+= mga/
 obj-$(CONFIG_DRM_I810)	+= i810/
 obj-$(CONFIG_DRM_I915)	+= i915/
+obj-$(CONFIG_DRM_IVIP) += ivip/
 obj-$(CONFIG_DRM_MGAG200) += mgag200/
 obj-$(CONFIG_DRM_VC4)  += vc4/
 obj-$(CONFIG_DRM_CIRRUS_QEMU) += cirrus/
diff --git a/drivers/gpu/drm/ivip/Kconfig b/drivers/gpu/drm/ivip/Kconfig
new file mode 100644
index 0000000..398c9ab
--- /dev/null
+++ b/drivers/gpu/drm/ivip/Kconfig
@@ -0,0 +1,14 @@
+config DRM_IVIP
+        tristate "Intel FGPA Video and Image Processing"
+        depends on DRM && OF
+        select DRM_GEM_CMA_HELPER
+        select DRM_KMS_HELPER
+        select DRM_KMS_FB_HELPER
+        select DRM_KMS_CMA_HELPER
+        help
+            Choose this option if you have a Intel FPGA Arria 10 system
+            and above with an Intel Display Port IP. This does not support
+            legacy Intel FPGA Cyclone V display port. Currently only single
+            frame buffer is supported. Note that ACPI and X_86 architecture
+            is not supported for Arria10.If M is selected the module will be
+            called ivip.
diff --git a/drivers/gpu/drm/ivip/Makefile b/drivers/gpu/drm/ivip/Makefile
new file mode 100644
index 0000000..cc55b04
--- /dev/null
+++ b/drivers/gpu/drm/ivip/Makefile
@@ -0,0 +1,9 @@
+#
+# Makefile for the drm device driver.  This driver provides support for the
+# Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher.
+
+ccflags-y := -Iinclude/drm
+
+obj-$(CONFIG_DRM_IVIP) += ivip.o
+ivip-objs := intel_vip_of.o intel_vip_core.o \
+	intel_vip_conn.o
diff --git a/drivers/gpu/drm/ivip/intel_vip_conn.c b/drivers/gpu/drm/ivip/intel_vip_conn.c
new file mode 100644
index 0000000..c88df23
--- /dev/null
+++ b/drivers/gpu/drm/ivip/intel_vip_conn.c
@@ -0,0 +1,96 @@
+/*
+ * intel_vip_conn.c -- Intel Video and Image Processing(VIP)
+ * Frame Buffer II driver
+ *
+ * This driver supports the Intel VIP Frame Reader component.
+ * More info on the hardware can be found in the Intel Video
+ * and Image Processing Suite User Guide at this address
+ * http://www.altera.com/literature/ug/ug_vip.pdf.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * Authors:
+ * Ong, Hean-Loong <hean.loong.ong@intel.com>
+ *
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <drm/drm_atomic_helper.h>
+#include <drm/drm_crtc_helper.h>
+#include <drm/drm_encoder_slave.h>
+#include <drm/drm_plane_helper.h>
+
+static enum drm_connector_status
+intelvipfb_drm_connector_detect(struct drm_connector *connector, bool force)
+{
+	return connector_status_connected;
+}
+
+static void intelvipfb_drm_connector_destroy(struct drm_connector *connector)
+{
+	drm_connector_unregister(connector);
+	drm_connector_cleanup(connector);
+}
+
+static const struct drm_connector_funcs intelvipfb_drm_connector_funcs = {
+	.dpms = drm_atomic_helper_connector_dpms,
+	.reset = drm_atomic_helper_connector_reset,
+	.detect = intelvipfb_drm_connector_detect,
+	.fill_modes = drm_helper_probe_single_connector_modes,
+	.destroy = intelvipfb_drm_connector_destroy,
+	.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
+	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
+};
+
+static int intelvipfb_drm_connector_get_modes(struct drm_connector *connector)
+{
+	struct drm_device *drm = connector->dev;
+	int count;
+
+	count = drm_add_modes_noedid(connector, drm->mode_config.max_width,
+			drm->mode_config.max_height);
+	drm_set_preferred_mode(connector, drm->mode_config.max_width,
+			drm->mode_config.max_height);
+	return count;
+}
+
+static const struct drm_connector_helper_funcs
+intelvipfb_drm_connector_helper_funcs = {
+	.get_modes = intelvipfb_drm_connector_get_modes,
+};
+
+struct drm_connector *
+intelvipfb_conn_setup(struct drm_device *drm)
+{
+	struct drm_connector *conn;
+	int ret;
+
+	conn = devm_kzalloc(drm->dev, sizeof(*conn), GFP_KERNEL);
+	if (IS_ERR(conn))
+		return NULL;
+
+	ret = drm_connector_init(drm, conn, &intelvipfb_drm_connector_funcs,
+			DRM_MODE_CONNECTOR_DisplayPort);
+	if (ret < 0) {
+		dev_err(drm->dev, "failed to initialize drm connector\n");
+		ret = -ENOMEM;
+		goto error_connector_cleanup;
+	}
+
+	drm_connector_helper_add(conn, &intelvipfb_drm_connector_helper_funcs);
+
+	return conn;
+
+error_connector_cleanup:
+	drm_connector_cleanup(conn);
+
+	return NULL;
+}
diff --git a/drivers/gpu/drm/ivip/intel_vip_core.c b/drivers/gpu/drm/ivip/intel_vip_core.c
new file mode 100644
index 0000000..6b43c13
--- /dev/null
+++ b/drivers/gpu/drm/ivip/intel_vip_core.c
@@ -0,0 +1,162 @@
+/*
+ * intel_vip_core.c -- Intel Video and Image Processing(VIP)
+ * Frame Buffer II driver
+ *
+ * This driver supports the Intel VIP Frame Reader component.
+ * More info on the hardware can be found in the Intel Video
+ * and Image Processing Suite User Guide at this address
+ * http://www.altera.com/literature/ug/ug_vip.pdf.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * Authors:
+ * Ong, Hean-Loong <hean.loong.ong@intel.com>
+ *
+ */
+
+#include <drm/drmP.h>
+#include <drm/drm_atomic.h>
+#include <drm/drm_atomic_helper.h>
+#include <drm/drm_crtc_helper.h>
+#include <drm/drm_fb_helper.h>
+#include <drm/drm_fb_cma_helper.h>
+#include <drm/drm_gem_cma_helper.h>
+#include <drm/drm_plane_helper.h>
+#include <drm/drm_simple_kms_helper.h>
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+
+#include "intel_vip_drv.h"
+
+static void intelvipfb_enable(struct drm_simple_display_pipe *pipe,
+	       struct drm_crtc_state *crtc_state)
+{
+	/*
+	 * The frameinfo variable has to correspond to the size of the VIP Suite
+	 * Frame Reader register 7 which will determine the maximum size used
+	 * in this frameinfo
+	 */
+
+	u32 frameinfo;
+	struct intelvipfb_priv *priv = pipe->plane.dev->dev_private;
+	void __iomem *base = priv->base;
+	struct drm_plane_state *state = pipe->plane.state;
+	dma_addr_t addr;
+
+	addr = drm_fb_cma_get_gem_addr(state->fb, state, 0);
+
+	dev_info(pipe->plane.dev->dev, "Address 0x%x\n", addr);
+
+	frameinfo =
+		readl(base + INTELVIPFB_FRAME_READER) & 0x00ffffff;
+	writel(frameinfo, base + INTELVIPFB_FRAME_INFO);
+	writel(addr, base + INTELVIPFB_FRAME_START);
+	/* Finally set the control register to 1 to start streaming */
+	writel(1, base + INTELVIPFB_CONTROL);
+}
+
+static void intelvipfb_disable(struct drm_simple_display_pipe *pipe)
+{
+	struct intelvipfb_priv *priv = pipe->plane.dev->dev_private;
+	void __iomem *base = priv->base;
+	/* set the control register to 0 to stop streaming */
+	writel(0, base + INTELVIPFB_CONTROL);
+}
+
+static const struct drm_mode_config_funcs intelvipfb_mode_config_funcs = {
+	.fb_create = drm_fb_cma_create,
+	.atomic_check = drm_atomic_helper_check,
+	.atomic_commit = drm_atomic_helper_commit,
+};
+
+static void intelvipfb_setup_mode_config(struct drm_device *drm)
+{
+	drm_mode_config_init(drm);
+	drm->mode_config.funcs = &intelvipfb_mode_config_funcs;
+}
+
+static int intelvipfb_pipe_prepare_fb(struct drm_simple_display_pipe *pipe,
+					struct drm_plane_state *plane_state)
+{
+	return drm_fb_cma_prepare_fb(&pipe->plane, plane_state);
+}
+
+
+static struct drm_simple_display_pipe_funcs fbpriv_funcs = {
+	.prepare_fb = intelvipfb_pipe_prepare_fb,
+	.enable = intelvipfb_enable,
+	.disable = intelvipfb_disable
+};
+
+int intelvipfb_probe(struct device *dev)
+{
+	int retval;
+	struct drm_device *drm;
+	struct intelvipfb_priv *fbpriv = dev_get_drvdata(dev);
+	struct drm_connector *connector;
+	u32 formats[] = {DRM_FORMAT_XRGB8888};
+
+	drm = fbpriv->drm;
+
+	drm->dev_private = fbpriv;
+
+	intelvipfb_setup_mode_config(drm);
+
+	connector = intelvipfb_conn_setup(drm);
+	if (!connector) {
+		dev_err(drm->dev, "Connector setup failed\n");
+		goto err_mode_config;
+	}
+
+	retval = drm_simple_display_pipe_init(drm, &fbpriv->pipe,
+			&fbpriv_funcs, formats,
+			ARRAY_SIZE(formats), connector);
+	if (retval < 0) {
+		dev_err(drm->dev, "Cannot setup simple display pipe\n");
+		goto err_mode_config;
+	}
+
+	fbpriv->fbcma = drm_fbdev_cma_init(drm,
+			drm->mode_config.preferred_depth,
+			drm->mode_config.num_connector);
+
+	drm_mode_config_reset(drm);
+
+	drm_dev_register(drm, 0);
+
+	return retval;
+
+err_mode_config:
+
+	drm_mode_config_cleanup(drm);
+	return -ENODEV;
+}
+
+int intelvipfb_remove(struct device *dev)
+{
+	struct intelvipfb_priv *fbpriv = dev_get_drvdata(dev);
+	struct drm_device *drm =  fbpriv->drm;
+
+	drm_dev_unregister(drm);
+
+	if (fbpriv->fbcma)
+		drm_fbdev_cma_fini(fbpriv->fbcma);
+
+	drm_mode_config_cleanup(drm);
+	drm_dev_unref(drm);
+
+	return 0;
+}
+
+MODULE_AUTHOR("Ong, Hean-Loong <hean.loong.ong@intel.com>");
+MODULE_DESCRIPTION("Intel VIP Frame Buffer II driver");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/gpu/drm/ivip/intel_vip_drv.h b/drivers/gpu/drm/ivip/intel_vip_drv.h
new file mode 100644
index 0000000..0a3555d
--- /dev/null
+++ b/drivers/gpu/drm/ivip/intel_vip_drv.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright (C) 2017 Intel Corporation.
+ *
+ * Intel Video and Image Processing(VIP) Frame Buffer II driver.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ * Authors:
+ * Ong, Hean-Loong <hean.loong.ong@intel.com>
+ *
+ */
+#ifndef _INTEL_VIP_DRV_H
+#define _INTEL_VIP_DRV_H
+
+#define DRIVER_NAME    "intelvipfb"
+#define BYTES_PER_PIXEL	 4
+#define CRTC_NUM	        1
+#define CONN_NUM	        1
+
+/* control registers */
+#define INTELVIPFB_CONTROL	      0
+#define INTELVIPFB_STATUS	       0x4
+#define INTELVIPFB_INTERRUPT	    0x8
+#define INTELVIPFB_FRAME_COUNTER	0xC
+#define INTELVIPFB_FRAME_DROP	   0x10
+#define INTELVIPFB_FRAME_INFO	   0x14
+#define INTELVIPFB_FRAME_START	  0x18
+#define INTELVIPFB_FRAME_READER	         0x1C
+
+int intelvipfb_probe(struct device *dev);
+int intelvipfb_remove(struct device *dev);
+int intelvipfb_setup_crtc(struct drm_device *drm);
+struct drm_connector *intelvipfb_conn_setup(struct drm_device *drm);
+
+struct intelvipfb_priv {
+	struct drm_simple_display_pipe pipe;
+	struct drm_fbdev_cma *fbcma;
+	struct drm_device *drm;
+	void    __iomem *base;
+};
+
+#endif
diff --git a/drivers/gpu/drm/ivip/intel_vip_of.c b/drivers/gpu/drm/ivip/intel_vip_of.c
new file mode 100644
index 0000000..b46f789
--- /dev/null
+++ b/drivers/gpu/drm/ivip/intel_vip_of.c
@@ -0,0 +1,194 @@
+/*
+ * intel_vip_of.c -- Intel Video and Image Processing(VIP)
+ * Frame Buffer II driver
+ *
+ * This driver supports the Intel VIP Frame Reader component.
+ * More info on the hardware can be found in the Intel Video
+ * and Image Processing Suite User Guide at this address
+ * http://www.altera.com/literature/ug/ug_vip.pdf.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * Authors:
+ * Ong, Hean-Loong <hean.loong.ong@intel.com>
+ *
+ */
+#include <drm/drm_fb_helper.h>
+#include <drm/drm_fb_cma_helper.h>
+#include <drm/drm_gem_cma_helper.h>
+#include <drm/drm_of.h>
+#include <drm/drm_simple_kms_helper.h>
+
+#include <linux/component.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+
+#include "intel_vip_drv.h"
+
+DEFINE_DRM_GEM_CMA_FOPS(drm_fops);
+
+static void intelvipfb_lastclose(struct drm_device *drm)
+{
+	struct intelvipfb_priv *priv = drm->dev_private;
+
+	drm_fbdev_cma_restore_mode(priv->fbcma);
+}
+
+static struct drm_driver intelvipfb_drm = {
+	.driver_features =
+			DRIVER_MODESET | DRIVER_GEM |
+			DRIVER_PRIME | DRIVER_ATOMIC,
+	.gem_free_object_unlocked = drm_gem_cma_free_object,
+	.gem_vm_ops = &drm_gem_cma_vm_ops,
+	.dumb_create = drm_gem_cma_dumb_create,
+	.dumb_map_offset = drm_gem_cma_dumb_map_offset,
+	.dumb_destroy = drm_gem_dumb_destroy,
+	.prime_handle_to_fd = drm_gem_prime_handle_to_fd,
+	.prime_fd_to_handle = drm_gem_prime_fd_to_handle,
+	.gem_prime_export = drm_gem_prime_export,
+	.gem_prime_import = drm_gem_prime_import,
+	.gem_prime_get_sg_table = drm_gem_cma_prime_get_sg_table,
+	.gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table,
+	.gem_prime_vmap = drm_gem_cma_prime_vmap,
+	.gem_prime_vunmap = drm_gem_cma_prime_vunmap,
+	.gem_prime_mmap = drm_gem_cma_prime_mmap,
+	.lastclose = intelvipfb_lastclose,
+	.name = DRIVER_NAME,
+	.date = "20170729",
+	.desc = "Intel FPGA VIP SUITE",
+	.major = 1,
+	.minor = 0,
+	.ioctls = NULL,
+	.patchlevel = 0,
+	.fops = &drm_fops,
+};
+
+/*
+ * Setting up information derived from OF Device Tree Nodes
+ * max-width, max-height, bits per pixel, memory port width
+ */
+
+static int intelvipfb_drm_setup(struct device *dev,
+				struct intelvipfb_priv *fbpriv)
+{
+	struct drm_device *drm = fbpriv->drm;
+	struct device_node *np = dev->of_node;
+	int mem_word_width;
+	int max_h, max_w;
+	int ret;
+
+	ret = of_property_read_u32(np, "altr,max-width", &max_w);
+	if (ret) {
+		dev_err(dev,
+			"Missing required parameter 'altr,max-width'");
+		return ret;
+	}
+
+	ret = of_property_read_u32(np, "altr,max-height", &max_h);
+	if (ret) {
+		dev_err(dev,
+			"Missing required parameter 'altr,max-height'");
+		return ret;
+	}
+
+	ret = of_property_read_u32(np, "altr,mem-port-width", &mem_word_width);
+	if (ret) {
+		dev_err(dev, "Missing required parameter 'altr,mem-port-width '");
+		return ret;
+	}
+
+	if (!(mem_word_width >= 32 && mem_word_width % 32 == 0)) {
+		dev_err(dev,
+			"mem-word-width is set to %i. must be >= 32 and multiple of 32.",
+			 mem_word_width);
+		return -ENODEV;
+	}
+
+	drm->mode_config.min_width = 640;
+	drm->mode_config.min_height = 480;
+	drm->mode_config.max_width = max_w;
+	drm->mode_config.max_height = max_h;
+	drm->mode_config.preferred_depth = 32;
+
+	return 0;
+}
+
+static int intelvipfb_of_probe(struct platform_device *pdev)
+{
+	int retval;
+	struct resource *reg_res;
+	struct intelvipfb_priv *fbpriv;
+	struct device *dev = &pdev->dev;
+	struct drm_device *drm;
+
+	fbpriv = devm_kzalloc(dev, sizeof(*fbpriv), GFP_KERNEL);
+	if (!fbpriv)
+		return -ENOMEM;
+
+	/*setup DRM */
+	drm = drm_dev_alloc(&intelvipfb_drm, dev);
+	if (IS_ERR(drm))
+		return PTR_ERR(drm);
+
+	retval = dma_set_mask_and_coherent(drm->dev, DMA_BIT_MASK(32));
+	if (retval)
+		return -ENODEV;
+
+	fbpriv->drm = drm;
+
+	reg_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!reg_res)
+		return -ENOMEM;
+
+	fbpriv->base = devm_ioremap_resource(dev, reg_res);
+
+	if (IS_ERR(fbpriv->base)) {
+		dev_err(dev, "devm_ioremap_resource failed\n");
+		retval = PTR_ERR(fbpriv->base);
+		return -ENOMEM;
+	}
+
+	intelvipfb_drm_setup(dev, fbpriv);
+
+	dev_set_drvdata(dev, fbpriv);
+
+	return intelvipfb_probe(dev);
+}
+
+static int intelvipfb_of_remove(struct platform_device *pdev)
+{
+	return intelvipfb_remove(&pdev->dev);
+}
+
+/*
+ * The name vip-frame-buffer-2.0 is derived from
+ * http://www.altera.com/literature/ug/ug_vip.pdf
+ * frame buffer IP cores section 14
+ */
+
+static const struct of_device_id intelvipfb_of_match[] = {
+	{ .compatible = "altr,vip-frame-buffer-2.0" },
+	{},
+};
+
+MODULE_DEVICE_TABLE(of, intelvipfb_of_match);
+
+static struct platform_driver intelvipfb_driver = {
+	.probe = intelvipfb_of_probe,
+	.remove = intelvipfb_of_remove,
+	.driver = {
+		.name = DRIVER_NAME,
+		.of_match_table = intelvipfb_of_match,
+	},
+};
+
+module_platform_driver(intelvipfb_driver);
-- 
2.7.4

[PATCHv6 3/3] ARM:drm ivip Intel FPGA Video and Image Processing Suite

[Hean-Loong, Ong]

From: Ong Hean Loong <hean.loong.ong@intel.com>

Driver for Intel FPGA Video and Image Processing Suite Frame Buffer II.
The driver only supports the Intel Arria10 devkit and its variants.
This driver can be either loaded staticlly or in modules.
The OF device tree binding is located at:
Documentation/devicetree/bindings/display/altr,vip-fb2.txt

Signed-off-by: Ong Hean Loong <hean.loong.ong@intel.com>
---
V6:
*Fix Comments for Makefile and Kconfig

V5:
*Fix Comments

V4:
*Fix Comments

V3:
*Changes to fixing drm_simple_pipe
*Used drm_fb_cma_get_gem_addr

V2:
*Adding drm_simple_display_pipe_init

---
---
 drivers/gpu/drm/Kconfig               |   2 +
 drivers/gpu/drm/Makefile              |   1 +
 drivers/gpu/drm/ivip/Kconfig          |  14 +++
 drivers/gpu/drm/ivip/Makefile         |   9 ++
 drivers/gpu/drm/ivip/intel_vip_conn.c |  96 +++++++++++++++++
 drivers/gpu/drm/ivip/intel_vip_core.c | 162 ++++++++++++++++++++++++++++
 drivers/gpu/drm/ivip/intel_vip_drv.h  |  52 +++++++++
 drivers/gpu/drm/ivip/intel_vip_of.c   | 194 ++++++++++++++++++++++++++++++++++
 8 files changed, 530 insertions(+)
 create mode 100644 drivers/gpu/drm/ivip/Kconfig
 create mode 100644 drivers/gpu/drm/ivip/Makefile
 create mode 100644 drivers/gpu/drm/ivip/intel_vip_conn.c
 create mode 100644 drivers/gpu/drm/ivip/intel_vip_core.c
 create mode 100644 drivers/gpu/drm/ivip/intel_vip_drv.h
 create mode 100644 drivers/gpu/drm/ivip/intel_vip_of.c

diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig
index 83cb2a8..38a184d 100644
--- a/drivers/gpu/drm/Kconfig
+++ b/drivers/gpu/drm/Kconfig
@@ -195,6 +195,8 @@ source "drivers/gpu/drm/nouveau/Kconfig"
 
 source "drivers/gpu/drm/i915/Kconfig"
 
+source "drivers/gpu/drm/ivip/Kconfig"
+
 config DRM_VGEM
 	tristate "Virtual GEM provider"
 	depends on DRM
diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile
index 24a066e..4162a0e 100644
--- a/drivers/gpu/drm/Makefile
+++ b/drivers/gpu/drm/Makefile
@@ -58,6 +58,7 @@ obj-$(CONFIG_DRM_AMDGPU)+= amd/amdgpu/
 obj-$(CONFIG_DRM_MGA)	+= mga/
 obj-$(CONFIG_DRM_I810)	+= i810/
 obj-$(CONFIG_DRM_I915)	+= i915/
+obj-$(CONFIG_DRM_IVIP) += ivip/
 obj-$(CONFIG_DRM_MGAG200) += mgag200/
 obj-$(CONFIG_DRM_VC4)  += vc4/
 obj-$(CONFIG_DRM_CIRRUS_QEMU) += cirrus/
diff --git a/drivers/gpu/drm/ivip/Kconfig b/drivers/gpu/drm/ivip/Kconfig
new file mode 100644
index 0000000..398c9ab
--- /dev/null
+++ b/drivers/gpu/drm/ivip/Kconfig
@@ -0,0 +1,14 @@
+config DRM_IVIP
+        tristate "Intel FGPA Video and Image Processing"
+        depends on DRM && OF
+        select DRM_GEM_CMA_HELPER
+        select DRM_KMS_HELPER
+        select DRM_KMS_FB_HELPER
+        select DRM_KMS_CMA_HELPER
+        help
+            Choose this option if you have a Intel FPGA Arria 10 system
+            and above with an Intel Display Port IP. This does not support
+            legacy Intel FPGA Cyclone V display port. Currently only single
+            frame buffer is supported. Note that ACPI and X_86 architecture
+            is not supported for Arria10.If M is selected the module will be
+            called ivip.
diff --git a/drivers/gpu/drm/ivip/Makefile b/drivers/gpu/drm/ivip/Makefile
new file mode 100644
index 0000000..cc55b04
--- /dev/null
+++ b/drivers/gpu/drm/ivip/Makefile
@@ -0,0 +1,9 @@
+#
+# Makefile for the drm device driver.  This driver provides support for the
+# Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher.
+
+ccflags-y := -Iinclude/drm
+
+obj-$(CONFIG_DRM_IVIP) += ivip.o
+ivip-objs := intel_vip_of.o intel_vip_core.o \
+	intel_vip_conn.o
diff --git a/drivers/gpu/drm/ivip/intel_vip_conn.c b/drivers/gpu/drm/ivip/intel_vip_conn.c
new file mode 100644
index 0000000..c88df23
--- /dev/null
+++ b/drivers/gpu/drm/ivip/intel_vip_conn.c
@@ -0,0 +1,96 @@
+/*
+ * intel_vip_conn.c -- Intel Video and Image Processing(VIP)
+ * Frame Buffer II driver
+ *
+ * This driver supports the Intel VIP Frame Reader component.
+ * More info on the hardware can be found in the Intel Video
+ * and Image Processing Suite User Guide at this address
+ * http://www.altera.com/literature/ug/ug_vip.pdf.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * Authors:
+ * Ong, Hean-Loong <hean.loong.ong@intel.com>
+ *
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <drm/drm_atomic_helper.h>
+#include <drm/drm_crtc_helper.h>
+#include <drm/drm_encoder_slave.h>
+#include <drm/drm_plane_helper.h>
+
+static enum drm_connector_status
+intelvipfb_drm_connector_detect(struct drm_connector *connector, bool force)
+{
+	return connector_status_connected;
+}
+
+static void intelvipfb_drm_connector_destroy(struct drm_connector *connector)
+{
+	drm_connector_unregister(connector);
+	drm_connector_cleanup(connector);
+}
+
+static const struct drm_connector_funcs intelvipfb_drm_connector_funcs = {
+	.dpms = drm_atomic_helper_connector_dpms,
+	.reset = drm_atomic_helper_connector_reset,
+	.detect = intelvipfb_drm_connector_detect,
+	.fill_modes = drm_helper_probe_single_connector_modes,
+	.destroy = intelvipfb_drm_connector_destroy,
+	.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
+	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
+};
+
+static int intelvipfb_drm_connector_get_modes(struct drm_connector *connector)
+{
+	struct drm_device *drm = connector->dev;
+	int count;
+
+	count = drm_add_modes_noedid(connector, drm->mode_config.max_width,
+			drm->mode_config.max_height);
+	drm_set_preferred_mode(connector, drm->mode_config.max_width,
+			drm->mode_config.max_height);
+	return count;
+}
+
+static const struct drm_connector_helper_funcs
+intelvipfb_drm_connector_helper_funcs = {
+	.get_modes = intelvipfb_drm_connector_get_modes,
+};
+
+struct drm_connector *
+intelvipfb_conn_setup(struct drm_device *drm)
+{
+	struct drm_connector *conn;
+	int ret;
+
+	conn = devm_kzalloc(drm->dev, sizeof(*conn), GFP_KERNEL);
+	if (IS_ERR(conn))
+		return NULL;
+
+	ret = drm_connector_init(drm, conn, &intelvipfb_drm_connector_funcs,
+			DRM_MODE_CONNECTOR_DisplayPort);
+	if (ret < 0) {
+		dev_err(drm->dev, "failed to initialize drm connector\n");
+		ret = -ENOMEM;
+		goto error_connector_cleanup;
+	}
+
+	drm_connector_helper_add(conn, &intelvipfb_drm_connector_helper_funcs);
+
+	return conn;
+
+error_connector_cleanup:
+	drm_connector_cleanup(conn);
+
+	return NULL;
+}
diff --git a/drivers/gpu/drm/ivip/intel_vip_core.c b/drivers/gpu/drm/ivip/intel_vip_core.c
new file mode 100644
index 0000000..6b43c13
--- /dev/null
+++ b/drivers/gpu/drm/ivip/intel_vip_core.c
@@ -0,0 +1,162 @@
+/*
+ * intel_vip_core.c -- Intel Video and Image Processing(VIP)
+ * Frame Buffer II driver
+ *
+ * This driver supports the Intel VIP Frame Reader component.
+ * More info on the hardware can be found in the Intel Video
+ * and Image Processing Suite User Guide at this address
+ * http://www.altera.com/literature/ug/ug_vip.pdf.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * Authors:
+ * Ong, Hean-Loong <hean.loong.ong@intel.com>
+ *
+ */
+
+#include <drm/drmP.h>
+#include <drm/drm_atomic.h>
+#include <drm/drm_atomic_helper.h>
+#include <drm/drm_crtc_helper.h>
+#include <drm/drm_fb_helper.h>
+#include <drm/drm_fb_cma_helper.h>
+#include <drm/drm_gem_cma_helper.h>
+#include <drm/drm_plane_helper.h>
+#include <drm/drm_simple_kms_helper.h>
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+
+#include "intel_vip_drv.h"
+
+static void intelvipfb_enable(struct drm_simple_display_pipe *pipe,
+	       struct drm_crtc_state *crtc_state)
+{
+	/*
+	 * The frameinfo variable has to correspond to the size of the VIP Suite
+	 * Frame Reader register 7 which will determine the maximum size used
+	 * in this frameinfo
+	 */
+
+	u32 frameinfo;
+	struct intelvipfb_priv *priv = pipe->plane.dev->dev_private;
+	void __iomem *base = priv->base;
+	struct drm_plane_state *state = pipe->plane.state;
+	dma_addr_t addr;
+
+	addr = drm_fb_cma_get_gem_addr(state->fb, state, 0);
+
+	dev_info(pipe->plane.dev->dev, "Address 0x%x\n", addr);
+
+	frameinfo =
+		readl(base + INTELVIPFB_FRAME_READER) & 0x00ffffff;
+	writel(frameinfo, base + INTELVIPFB_FRAME_INFO);
+	writel(addr, base + INTELVIPFB_FRAME_START);
+	/* Finally set the control register to 1 to start streaming */
+	writel(1, base + INTELVIPFB_CONTROL);
+}
+
+static void intelvipfb_disable(struct drm_simple_display_pipe *pipe)
+{
+	struct intelvipfb_priv *priv = pipe->plane.dev->dev_private;
+	void __iomem *base = priv->base;
+	/* set the control register to 0 to stop streaming */
+	writel(0, base + INTELVIPFB_CONTROL);
+}
+
+static const struct drm_mode_config_funcs intelvipfb_mode_config_funcs = {
+	.fb_create = drm_fb_cma_create,
+	.atomic_check = drm_atomic_helper_check,
+	.atomic_commit = drm_atomic_helper_commit,
+};
+
+static void intelvipfb_setup_mode_config(struct drm_device *drm)
+{
+	drm_mode_config_init(drm);
+	drm->mode_config.funcs = &intelvipfb_mode_config_funcs;
+}
+
+static int intelvipfb_pipe_prepare_fb(struct drm_simple_display_pipe *pipe,
+					struct drm_plane_state *plane_state)
+{
+	return drm_fb_cma_prepare_fb(&pipe->plane, plane_state);
+}
+
+
+static struct drm_simple_display_pipe_funcs fbpriv_funcs = {
+	.prepare_fb = intelvipfb_pipe_prepare_fb,
+	.enable = intelvipfb_enable,
+	.disable = intelvipfb_disable
+};
+
+int intelvipfb_probe(struct device *dev)
+{
+	int retval;
+	struct drm_device *drm;
+	struct intelvipfb_priv *fbpriv = dev_get_drvdata(dev);
+	struct drm_connector *connector;
+	u32 formats[] = {DRM_FORMAT_XRGB8888};
+
+	drm = fbpriv->drm;
+
+	drm->dev_private = fbpriv;
+
+	intelvipfb_setup_mode_config(drm);
+
+	connector = intelvipfb_conn_setup(drm);
+	if (!connector) {
+		dev_err(drm->dev, "Connector setup failed\n");
+		goto err_mode_config;
+	}
+
+	retval = drm_simple_display_pipe_init(drm, &fbpriv->pipe,
+			&fbpriv_funcs, formats,
+			ARRAY_SIZE(formats), connector);
+	if (retval < 0) {
+		dev_err(drm->dev, "Cannot setup simple display pipe\n");
+		goto err_mode_config;
+	}
+
+	fbpriv->fbcma = drm_fbdev_cma_init(drm,
+			drm->mode_config.preferred_depth,
+			drm->mode_config.num_connector);
+
+	drm_mode_config_reset(drm);
+
+	drm_dev_register(drm, 0);
+
+	return retval;
+
+err_mode_config:
+
+	drm_mode_config_cleanup(drm);
+	return -ENODEV;
+}
+
+int intelvipfb_remove(struct device *dev)
+{
+	struct intelvipfb_priv *fbpriv = dev_get_drvdata(dev);
+	struct drm_device *drm =  fbpriv->drm;
+
+	drm_dev_unregister(drm);
+
+	if (fbpriv->fbcma)
+		drm_fbdev_cma_fini(fbpriv->fbcma);
+
+	drm_mode_config_cleanup(drm);
+	drm_dev_unref(drm);
+
+	return 0;
+}
+
+MODULE_AUTHOR("Ong, Hean-Loong <hean.loong.ong@intel.com>");
+MODULE_DESCRIPTION("Intel VIP Frame Buffer II driver");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/gpu/drm/ivip/intel_vip_drv.h b/drivers/gpu/drm/ivip/intel_vip_drv.h
new file mode 100644
index 0000000..0a3555d
--- /dev/null
+++ b/drivers/gpu/drm/ivip/intel_vip_drv.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright (C) 2017 Intel Corporation.
+ *
+ * Intel Video and Image Processing(VIP) Frame Buffer II driver.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ * Authors:
+ * Ong, Hean-Loong <hean.loong.ong@intel.com>
+ *
+ */
+#ifndef _INTEL_VIP_DRV_H
+#define _INTEL_VIP_DRV_H
+
+#define DRIVER_NAME    "intelvipfb"
+#define BYTES_PER_PIXEL	 4
+#define CRTC_NUM	        1
+#define CONN_NUM	        1
+
+/* control registers */
+#define INTELVIPFB_CONTROL	      0
+#define INTELVIPFB_STATUS	       0x4
+#define INTELVIPFB_INTERRUPT	    0x8
+#define INTELVIPFB_FRAME_COUNTER	0xC
+#define INTELVIPFB_FRAME_DROP	   0x10
+#define INTELVIPFB_FRAME_INFO	   0x14
+#define INTELVIPFB_FRAME_START	  0x18
+#define INTELVIPFB_FRAME_READER	         0x1C
+
+int intelvipfb_probe(struct device *dev);
+int intelvipfb_remove(struct device *dev);
+int intelvipfb_setup_crtc(struct drm_device *drm);
+struct drm_connector *intelvipfb_conn_setup(struct drm_device *drm);
+
+struct intelvipfb_priv {
+	struct drm_simple_display_pipe pipe;
+	struct drm_fbdev_cma *fbcma;
+	struct drm_device *drm;
+	void    __iomem *base;
+};
+
+#endif
diff --git a/drivers/gpu/drm/ivip/intel_vip_of.c b/drivers/gpu/drm/ivip/intel_vip_of.c
new file mode 100644
index 0000000..b46f789
--- /dev/null
+++ b/drivers/gpu/drm/ivip/intel_vip_of.c
@@ -0,0 +1,194 @@
+/*
+ * intel_vip_of.c -- Intel Video and Image Processing(VIP)
+ * Frame Buffer II driver
+ *
+ * This driver supports the Intel VIP Frame Reader component.
+ * More info on the hardware can be found in the Intel Video
+ * and Image Processing Suite User Guide at this address
+ * http://www.altera.com/literature/ug/ug_vip.pdf.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * Authors:
+ * Ong, Hean-Loong <hean.loong.ong@intel.com>
+ *
+ */
+#include <drm/drm_fb_helper.h>
+#include <drm/drm_fb_cma_helper.h>
+#include <drm/drm_gem_cma_helper.h>
+#include <drm/drm_of.h>
+#include <drm/drm_simple_kms_helper.h>
+
+#include <linux/component.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+
+#include "intel_vip_drv.h"
+
+DEFINE_DRM_GEM_CMA_FOPS(drm_fops);
+
+static void intelvipfb_lastclose(struct drm_device *drm)
+{
+	struct intelvipfb_priv *priv = drm->dev_private;
+
+	drm_fbdev_cma_restore_mode(priv->fbcma);
+}
+
+static struct drm_driver intelvipfb_drm = {
+	.driver_features =
+			DRIVER_MODESET | DRIVER_GEM |
+			DRIVER_PRIME | DRIVER_ATOMIC,
+	.gem_free_object_unlocked = drm_gem_cma_free_object,
+	.gem_vm_ops = &drm_gem_cma_vm_ops,
+	.dumb_create = drm_gem_cma_dumb_create,
+	.dumb_map_offset = drm_gem_cma_dumb_map_offset,
+	.dumb_destroy = drm_gem_dumb_destroy,
+	.prime_handle_to_fd = drm_gem_prime_handle_to_fd,
+	.prime_fd_to_handle = drm_gem_prime_fd_to_handle,
+	.gem_prime_export = drm_gem_prime_export,
+	.gem_prime_import = drm_gem_prime_import,
+	.gem_prime_get_sg_table = drm_gem_cma_prime_get_sg_table,
+	.gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table,
+	.gem_prime_vmap = drm_gem_cma_prime_vmap,
+	.gem_prime_vunmap = drm_gem_cma_prime_vunmap,
+	.gem_prime_mmap = drm_gem_cma_prime_mmap,
+	.lastclose = intelvipfb_lastclose,
+	.name = DRIVER_NAME,
+	.date = "20170729",
+	.desc = "Intel FPGA VIP SUITE",
+	.major = 1,
+	.minor = 0,
+	.ioctls = NULL,
+	.patchlevel = 0,
+	.fops = &drm_fops,
+};
+
+/*
+ * Setting up information derived from OF Device Tree Nodes
+ * max-width, max-height, bits per pixel, memory port width
+ */
+
+static int intelvipfb_drm_setup(struct device *dev,
+				struct intelvipfb_priv *fbpriv)
+{
+	struct drm_device *drm = fbpriv->drm;
+	struct device_node *np = dev->of_node;
+	int mem_word_width;
+	int max_h, max_w;
+	int ret;
+
+	ret = of_property_read_u32(np, "altr,max-width", &max_w);
+	if (ret) {
+		dev_err(dev,
+			"Missing required parameter 'altr,max-width'");
+		return ret;
+	}
+
+	ret = of_property_read_u32(np, "altr,max-height", &max_h);
+	if (ret) {
+		dev_err(dev,
+			"Missing required parameter 'altr,max-height'");
+		return ret;
+	}
+
+	ret = of_property_read_u32(np, "altr,mem-port-width", &mem_word_width);
+	if (ret) {
+		dev_err(dev, "Missing required parameter 'altr,mem-port-width '");
+		return ret;
+	}
+
+	if (!(mem_word_width >= 32 && mem_word_width % 32 == 0)) {
+		dev_err(dev,
+			"mem-word-width is set to %i. must be >= 32 and multiple of 32.",
+			 mem_word_width);
+		return -ENODEV;
+	}
+
+	drm->mode_config.min_width = 640;
+	drm->mode_config.min_height = 480;
+	drm->mode_config.max_width = max_w;
+	drm->mode_config.max_height = max_h;
+	drm->mode_config.preferred_depth = 32;
+
+	return 0;
+}
+
+static int intelvipfb_of_probe(struct platform_device *pdev)
+{
+	int retval;
+	struct resource *reg_res;
+	struct intelvipfb_priv *fbpriv;
+	struct device *dev = &pdev->dev;
+	struct drm_device *drm;
+
+	fbpriv = devm_kzalloc(dev, sizeof(*fbpriv), GFP_KERNEL);
+	if (!fbpriv)
+		return -ENOMEM;
+
+	/*setup DRM */
+	drm = drm_dev_alloc(&intelvipfb_drm, dev);
+	if (IS_ERR(drm))
+		return PTR_ERR(drm);
+
+	retval = dma_set_mask_and_coherent(drm->dev, DMA_BIT_MASK(32));
+	if (retval)
+		return -ENODEV;
+
+	fbpriv->drm = drm;
+
+	reg_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!reg_res)
+		return -ENOMEM;
+
+	fbpriv->base = devm_ioremap_resource(dev, reg_res);
+
+	if (IS_ERR(fbpriv->base)) {
+		dev_err(dev, "devm_ioremap_resource failed\n");
+		retval = PTR_ERR(fbpriv->base);
+		return -ENOMEM;
+	}
+
+	intelvipfb_drm_setup(dev, fbpriv);
+
+	dev_set_drvdata(dev, fbpriv);
+
+	return intelvipfb_probe(dev);
+}
+
+static int intelvipfb_of_remove(struct platform_device *pdev)
+{
+	return intelvipfb_remove(&pdev->dev);
+}
+
+/*
+ * The name vip-frame-buffer-2.0 is derived from
+ * http://www.altera.com/literature/ug/ug_vip.pdf
+ * frame buffer IP cores section 14
+ */
+
+static const struct of_device_id intelvipfb_of_match[] = {
+	{ .compatible = "altr,vip-frame-buffer-2.0" },
+	{},
+};
+
+MODULE_DEVICE_TABLE(of, intelvipfb_of_match);
+
+static struct platform_driver intelvipfb_driver = {
+	.probe = intelvipfb_of_probe,
+	.remove = intelvipfb_of_remove,
+	.driver = {
+		.name = DRIVER_NAME,
+		.of_match_table = intelvipfb_of_match,
+	},
+};
+
+module_platform_driver(intelvipfb_driver);
-- 
2.7.4

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[PATCHv6 3/3] ARM:drm ivip Intel FPGA Video and Image Processing Suite

[Randy Dunlap]

On 08/10/2017 11:49 PM, Hean-Loong, Ong wrote:
> diff --git a/drivers/gpu/drm/ivip/Kconfig b/drivers/gpu/drm/ivip/Kconfig
> new file mode 100644
> index 0000000..398c9ab
> --- /dev/null
> +++ b/drivers/gpu/drm/ivip/Kconfig
> @@ -0,0 +1,14 @@
> +config DRM_IVIP
> +        tristate "Intel FGPA Video and Image Processing"
> +        depends on DRM && OF
> +        select DRM_GEM_CMA_HELPER
> +        select DRM_KMS_HELPER
> +        select DRM_KMS_FB_HELPER
> +        select DRM_KMS_CMA_HELPER
> +        help
> +            Choose this option if you have a Intel FPGA Arria 10 system

                                              an

> +            and above with an Intel Display Port IP. This does not support
> +            legacy Intel FPGA Cyclone V display port. Currently only single
> +            frame buffer is supported. Note that ACPI and X_86 architecture
> +            is not supported for Arria10.If M is selected the module will be

                                    Arria10. If M is

> +            called ivip.

All of the help text should be indented with one tab + 2 spaces
according to coding-style.rst.


-- 
~Randy

Re: [PATCHv6 3/3] ARM:drm ivip Intel FPGA Video and Image Processing Suite

[Randy Dunlap]

On 08/10/2017 11:49 PM, Hean-Loong, Ong wrote:
> diff --git a/drivers/gpu/drm/ivip/Kconfig b/drivers/gpu/drm/ivip/Kconfig
> new file mode 100644
> index 0000000..398c9ab
> --- /dev/null
> +++ b/drivers/gpu/drm/ivip/Kconfig
> @@ -0,0 +1,14 @@
> +config DRM_IVIP
> +        tristate "Intel FGPA Video and Image Processing"
> +        depends on DRM && OF
> +        select DRM_GEM_CMA_HELPER
> +        select DRM_KMS_HELPER
> +        select DRM_KMS_FB_HELPER
> +        select DRM_KMS_CMA_HELPER
> +        help
> +            Choose this option if you have a Intel FPGA Arria 10 system

                                              an

> +            and above with an Intel Display Port IP. This does not support
> +            legacy Intel FPGA Cyclone V display port. Currently only single
> +            frame buffer is supported. Note that ACPI and X_86 architecture
> +            is not supported for Arria10.If M is selected the module will be

                                    Arria10. If M is

> +            called ivip.

All of the help text should be indented with one tab + 2 spaces
according to coding-style.rst.


-- 
~Randy

[PATCHv6 3/3] ARM:drm ivip Intel FPGA Video and Image Processing Suite

[Ong, Hean Loong]

On Fri, 2017-08-11 at 08:21 -0700, Randy Dunlap wrote:
> On 08/10/2017 11:49 PM, Hean-Loong, Ong wrote:
> > 
> > diff --git a/drivers/gpu/drm/ivip/Kconfig
> > b/drivers/gpu/drm/ivip/Kconfig
> > new file mode 100644
> > index 0000000..398c9ab
> > --- /dev/null
> > +++ b/drivers/gpu/drm/ivip/Kconfig
> > @@ -0,0 +1,14 @@
> > +config DRM_IVIP
> > +????????tristate "Intel FGPA Video and Image Processing"
> > +????????depends on DRM && OF
> > +????????select DRM_GEM_CMA_HELPER
> > +????????select DRM_KMS_HELPER
> > +????????select DRM_KMS_FB_HELPER
> > +????????select DRM_KMS_CMA_HELPER
> > +????????help
> > +????????????Choose this option if you have a Intel FPGA Arria 10
> > system
> ??????????????????????????????????????????????an
> 
> > 
> > +????????????and above with an Intel Display Port IP. This does not
> > support
> > +????????????legacy Intel FPGA Cyclone V display port. Currently
> > only single
> > +????????????frame buffer is supported. Note that ACPI and X_86
> > architecture
> > +????????????is not supported for Arria10.If M is selected the
> > module will be
> ????????????????????????????????????Arria10. If M is
> 
> > 
> > +????????????called ivip.
> All of the help text should be indented with one tab + 2 spaces
> according to coding-style.rst.
> 
> 
Noted.

Re: [PATCHv6 3/3] ARM:drm ivip Intel FPGA Video and Image Processing Suite

[Ong, Hean Loong]

On Fri, 2017-08-11 at 08:21 -0700, Randy Dunlap wrote:
> On 08/10/2017 11:49 PM, Hean-Loong, Ong wrote:
> > 
> > diff --git a/drivers/gpu/drm/ivip/Kconfig
> > b/drivers/gpu/drm/ivip/Kconfig
> > new file mode 100644
> > index 0000000..398c9ab
> > --- /dev/null
> > +++ b/drivers/gpu/drm/ivip/Kconfig
> > @@ -0,0 +1,14 @@
> > +config DRM_IVIP
> > +        tristate "Intel FGPA Video and Image Processing"
> > +        depends on DRM && OF
> > +        select DRM_GEM_CMA_HELPER
> > +        select DRM_KMS_HELPER
> > +        select DRM_KMS_FB_HELPER
> > +        select DRM_KMS_CMA_HELPER
> > +        help
> > +            Choose this option if you have a Intel FPGA Arria 10
> > system
>                                               an
> 
> > 
> > +            and above with an Intel Display Port IP. This does not
> > support
> > +            legacy Intel FPGA Cyclone V display port. Currently
> > only single
> > +            frame buffer is supported. Note that ACPI and X_86
> > architecture
> > +            is not supported for Arria10.If M is selected the
> > module will be
>                                     Arria10. If M is
> 
> > 
> > +            called ivip.
> All of the help text should be indented with one tab + 2 spaces
> according to coding-style.rst.
> 
> 
Noted.

Re: [PATCHv6 3/3] ARM:drm ivip Intel FPGA Video and Image Processing Suite

[Ong, Hean Loong]

[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain; charset="utf-8", Size: 1673 bytes --]

On Fri, 2017-08-11 at 08:21 -0700, Randy Dunlap wrote:
> On 08/10/2017 11:49 PM, Hean-Loong, Ong wrote:
> > 
> > diff --git a/drivers/gpu/drm/ivip/Kconfig
> > b/drivers/gpu/drm/ivip/Kconfig
> > new file mode 100644
> > index 0000000..398c9ab
> > --- /dev/null
> > +++ b/drivers/gpu/drm/ivip/Kconfig
> > @@ -0,0 +1,14 @@
> > +config DRM_IVIP
> > +        tristate "Intel FGPA Video and Image Processing"
> > +        depends on DRM && OF
> > +        select DRM_GEM_CMA_HELPER
> > +        select DRM_KMS_HELPER
> > +        select DRM_KMS_FB_HELPER
> > +        select DRM_KMS_CMA_HELPER
> > +        help
> > +            Choose this option if you have a Intel FPGA Arria 10
> > system
>                                               an
> 
> > 
> > +            and above with an Intel Display Port IP. This does not
> > support
> > +            legacy Intel FPGA Cyclone V display port. Currently
> > only single
> > +            frame buffer is supported. Note that ACPI and X_86
> > architecture
> > +            is not supported for Arria10.If M is selected the
> > module will be
>                                     Arria10. If M is
> 
> > 
> > +            called ivip.
> All of the help text should be indented with one tab + 2 spaces
> according to coding-style.rst.
> 
> 
Noted.N‹§²æìr¸›yúèšØb²X¬¶Ç§vØ^–)Þº{.nÇ+‰·zøœzÚÞz)í…æèw*\x1fjg¬±¨\x1e¶‰šŽŠÝ¢j.ïÛ°\½½MŽúgjÌæa×\x02››–' ™©Þ¢¸\f¢·¦j:+v‰¨ŠwèjØm¶Ÿÿ¾\a«‘êçzZ+ƒùšŽŠÝ¢j"ú!¶i

Re: [PATCHv6 1/3] ARM:dt-bindings Intel FPGA Video and Image Processing Suite

[Laurent Pinchart]

Hi Hean Loong,

(CC'ing dri-devel again as I noticed it wasn't CC'ed anymore)

On Friday 18 Aug 2017 08:34:44 Ong, Hean Loong wrote:
> Hi Laurent,
> Thanks for the comments, I drafted a copy of the DT bindings based on
> your recommendations and inputs. I inserted the changes below the
> previous comments. 

[snip]

> Intel Video and Image Processing(VIP) Frame Buffer II bindings
> 
> Supported hardware: Intel FPGA SoC Arria10 and above with display port
> IP
> 
> The Video Frame Buffer II in Video Image Processing (VIP) suite is an IP
> core that interfaces between system memory and Avalon-ST video ports. The IP
> core can be configured to support the memory reader (from memory to Avalon-
> ST) and/or memory writer (from Avalon-ST to memory) interfaces.
> 
> Connections between the Frame Buffer II and other video IP cores in the
> system are modelled using the OF graph DT bindings. The Frame Buffer II node
> has up to two OF graph ports. When the memory writer interface is enabled,
> port 0 maps to the Avalon-ST Input (din) port. When the memory reader
> interface is enabled, port 1 maps to the Avalon-ST Output (dout) port.
> 
> More information the FPGA video IP component can be acquired from
> https://www.altera.com/content/dam/altera-www/global/en_US/pdfs\
> /literature/ug/ug_vip.pdf
> 
> New bindings:
> =============

How are the bindings "new" ? You can omit that title.

> Required properties:
> ----------------------------
> - compatible: "altr,vip-frame-buffer-2.0"
> - reg: Physical base address and length of the framebuffer controller's
> 	registers.
> - altr,max-width: The maximum width of the framebuffer in pixels.
> - altr,max-height: The maximum height of the framebuffer in pixels.
> - altr,mem-port-width = the bus width of the avalon master port 
> 	on the frame reader

You need to mention the ports here as they are mandatory. I would move the 
second paragraph from the introduction to here. You should also refer to the 
file defining the OF graph DT bindings. You can find examples in other DT 
bindings.

> Example:
> ----------------------------
>  +-----+      +-----------+      +------------+      +-----------+
>  |  D  |      | Frame     |      | DP/HDMI TX |      | DP/HDMI   |
>  |  D  |----->| Buffer II |----->| Controller |----->| Connector |
>  |  R  |      |           |      |            |      |           |
>  +-----+      +-----------+      +------------+      +-----------+
> 
> framebuffer@100000280 {
>         compatible = "altr,vip-frame-buffer-2.0";
>         reg = <0x00000001 0x00000280 0x00000040>;
>         altr,max-width = <1280>;
>         altr,max-height = <720>;
>         altr,mem-port-width = <128>;
> 
>         ports {
>                 #address-cells = <1>;
>                 #size-cells = <0>;
> 
>                 port@1 {
>                         reg = <1>;
>                         fb_output: endpoint {
>                                 remote-endpoint = <&dp_encoder_input>;
>                         };
>                 };
>         };
> };
> 
> If there is a need to scale the Frame Buffer II IP cores in
> the pipeline, each node would have its own node, connected
> through ports and endpoints. 
> 
> hdmi-encoder@......... {
>         compatible = "altr,hdmi-tx-16.0";

This was just an example, please use the real compatible string of the HDMI 
controller (and please submit DT bindings for the HDMI controller :-)). Please 
also fill the reg property with values from a real example.

>         reg = <.....>;
>         /* Other IP-specific properties here */
> 
>         ports {
>                 #address-cells = <1>;
>                 #size-cells = <0>;
> 
>                 port@0 {
>                         reg = <0>;
>                         hdmi_tx_input: endpoint {
>                                 remote-endpoint = <&fb_output>;
>                         };
>                 };
> 
>                 port@1 {
>                         reg = <1>;
>                         hdmi_tx_output: endpoint {
>                                 remote-endpoint = <&hdmi_conn_input>;
>                         };
>                 };
>         };
> };
> 
> hdmi-connector@0 {
>         compatible = "hdmi-connector";
>         type = "a";
> 
>         port {
>                 hdmi_conn_input: endpoint {
>                         remote-endpoint = <&hdmi_tx_output>;
>                 };
>         };
> };

-- 
Regards,

Laurent Pinchart

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Re: [PATCHv6 1/3] ARM:dt-bindings Intel FPGA Video and Image Processing Suite

[Ong, Hean Loong]

Hi Laurent Thanks. my replies are below

On Fri, 2017-08-18 at 16:11 +0300, Laurent Pinchart wrote:
> Hi Hean Loong,
> 
> (CC'ing dri-devel again as I noticed it wasn't CC'ed anymore)
> 
> On Friday 18 Aug 2017 08:34:44 Ong, Hean Loong wrote:
> > 
> > Hi Laurent,
> > Thanks for the comments, I drafted a copy of the DT bindings based
> > on
> > your recommendations and inputs. I inserted the changes below the
> > previous comments. 
> [snip]
> 
> > 
> > Intel Video and Image Processing(VIP) Frame Buffer II bindings
> > 
> > Supported hardware: Intel FPGA SoC Arria10 and above with display
> > port
> > IP
> > 
> > The Video Frame Buffer II in Video Image Processing (VIP) suite is
> > an IP
> > core that interfaces between system memory and Avalon-ST video
> > ports. The IP
> > core can be configured to support the memory reader (from memory to
> > Avalon-
> > ST) and/or memory writer (from Avalon-ST to memory) interfaces.
> > 
> > Connections between the Frame Buffer II and other video IP cores in
> > the
> > system are modelled using the OF graph DT bindings. The Frame
> > Buffer II node
> > has up to two OF graph ports. When the memory writer interface is
> > enabled,
> > port 0 maps to the Avalon-ST Input (din) port. When the memory
> > reader
> > interface is enabled, port 1 maps to the Avalon-ST Output (dout)
> > port.
> > 
> > More information the FPGA video IP component can be acquired from
> > https://www.altera.com/content/dam/altera-www/global/en_US/pdfs\
> > /literature/ug/ug_vip.pdf
> > 
> > New bindings:
> > =============
> How are the bindings "new" ? You can omit that title.
> 

Noted.
> > 
> > Required properties:
> > ----------------------------
> > - compatible: "altr,vip-frame-buffer-2.0"
> > - reg: Physical base address and length of the framebuffer
> > controller's
> > 	registers.
> > - altr,max-width: The maximum width of the framebuffer in pixels.
> > - altr,max-height: The maximum height of the framebuffer in pixels.
> > - altr,mem-port-width = the bus width of the avalon master port 
> > 	on the frame reader
> You need to mention the ports here as they are mandatory. I would
> move the 
> second paragraph from the introduction to here. You should also refer
> to the 
> file defining the OF graph DT bindings. You can find examples in
> other DT 
> bindings.
> 
Noted
> > 
> > Example:
> > ----------------------------
> >  +-----+      +-----------+      +------------+      +-----------+
> >  |  D  |      | Frame     |      | DP/HDMI TX |      | DP/HDMI   |
> >  |  D  |----->| Buffer II |----->| Controller |----->| Connector |
> >  |  R  |      |           |      |            |      |           |
> >  +-----+      +-----------+      +------------+      +-----------+
> > 
> > framebuffer@100000280 {
> >         compatible = "altr,vip-frame-buffer-2.0";
> >         reg = <0x00000001 0x00000280 0x00000040>;
> >         altr,max-width = <1280>;
> >         altr,max-height = <720>;
> >         altr,mem-port-width = <128>;
> > 
> >         ports {
> >                 #address-cells = <1>;
> >                 #size-cells = <0>;
> > 
> >                 port@1 {
> >                         reg = <1>;
> >                         fb_output: endpoint {
> >                                 remote-endpoint =
> > <&dp_encoder_input>;
> >                         };
> >                 };
> >         };
> > };
> > 
> > If there is a need to scale the Frame Buffer II IP cores in
> > the pipeline, each node would have its own node, connected
> > through ports and endpoints. 
> > 
> > hdmi-encoder@......... {
> >         compatible = "altr,hdmi-tx-16.0";
> This was just an example, please use the real compatible string of
> the HDMI 
> controller (and please submit DT bindings for the HDMI controller :-
> )). Please 
> also fill the reg property with values from a real example.
> 
I was trying to get overall picture to be correct before I proceed
further. We currently do not have support for HDMI therefore I would
omit this until a HDMI IP is available. The only values are available
for the Display Port.
> > 
> >         reg = <.....>;
> >         /* Other IP-specific properties here */
> > 
> >         ports {
> >                 #address-cells = <1>;
> >                 #size-cells = <0>;
> > 
> >                 port@0 {
> >                         reg = <0>;
> >                         hdmi_tx_input: endpoint {
> >                                 remote-endpoint = <&fb_output>;
> >                         };
> >                 };
> > 
> >                 port@1 {
> >                         reg = <1>;
> >                         hdmi_tx_output: endpoint {
> >                                 remote-endpoint =
> > <&hdmi_conn_input>;
> >                         };
> >                 };
> >         };
> > };
> > 
> > hdmi-connector@0 {
> >         compatible = "hdmi-connector";
> >         type = "a";
> > 
> >         port {
> >                 hdmi_conn_input: endpoint {
> >                         remote-endpoint = <&hdmi_tx_output>;
> >                 };
> >         };
> > };
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Re: [PATCHv6 1/3] ARM:dt-bindings Intel FPGA Video and Image Processing Suite

[Laurent Pinchart]

Hi Hean Loong,

On Monday, 21 August 2017 04:40:09 EEST Ong, Hean Loong wrote:
> On Fri, 2017-08-18 at 16:11 +0300, Laurent Pinchart wrote:
> > On Friday 18 Aug 2017 08:34:44 Ong, Hean Loong wrote:
> > > 
> > > Hi Laurent,
> > > Thanks for the comments, I drafted a copy of the DT bindings based
> > > on your recommendations and inputs. I inserted the changes below the
> > > previous comments. 
> > 
> > [snip]
> > 
> > > 
> > > Intel Video and Image Processing(VIP) Frame Buffer II bindings
> > > 
> > > Supported hardware: Intel FPGA SoC Arria10 and above with display
> > > portIP
> > > 
> > > The Video Frame Buffer II in Video Image Processing (VIP) suite is
> > > an IP core that interfaces between system memory and Avalon-ST video
> > > ports. The IP core can be configured to support the memory reader (from
> > > memory to Avalon-ST) and/or memory writer (from Avalon-ST to memory)
> > > interfaces.
> > > 
> > > Connections between the Frame Buffer II and other video IP cores in
> > > the system are modelled using the OF graph DT bindings. The Frame
> > > Buffer II node has up to two OF graph ports. When the memory writer
> > > interface is enabled, port 0 maps to the Avalon-ST Input (din) port.
> > > When the memory reader interface is enabled, port 1 maps to the Avalon-
> > > ST Output (dout) port.
> > > 
> > > More information the FPGA video IP component can be acquired from
> > > https://www.altera.com/content/dam/altera-www/global/en_US/pdfs\
> > > /literature/ug/ug_vip.pdf
> > > 
> > > New bindings:
> > > =============
> > 
> > How are the bindings "new" ? You can omit that title.
> 
> Noted.
> 
> > > 
> > > Required properties:
> > > ----------------------------
> > > - compatible: "altr,vip-frame-buffer-2.0"
> > > - reg: Physical base address and length of the framebuffer
> > > controller's registers.
> > > - altr,max-width: The maximum width of the framebuffer in pixels.
> > > - altr,max-height: The maximum height of the framebuffer in pixels.
> > > - altr,mem-port-width = the bus width of the avalon master port 
> > > 	on the frame reader
> > 
> > You need to mention the ports here as they are mandatory. I would
> > move the second paragraph from the introduction to here. You should also
> > refer to the file defining the OF graph DT bindings. You can find examples
> > in other DT bindings.
> 
> Noted
> 
> > > 
> > > Example:
> > > ----------------------------
> > >  +-----+      +-----------+      +------------+      +-----------+
> > >  |  D  |      | Frame     |      | DP/HDMI TX |      | DP/HDMI   |
> > >  |  D  |----->| Buffer II |----->| Controller |----->| Connector |
> > >  |  R  |      |           |      |            |      |           |
> > >  +-----+      +-----------+      +------------+      +-----------+
> > > 
> > > framebuffer@100000280 {
> > >         compatible = "altr,vip-frame-buffer-2.0";
> > >         reg = <0x00000001 0x00000280 0x00000040>;
> > >         altr,max-width = <1280>;
> > >         altr,max-height = <720>;
> > >         altr,mem-port-width = <128>;
> > > 
> > >         ports {
> > >                 #address-cells = <1>;
> > >                 #size-cells = <0>;
> > > 
> > >                 port@1 {
> > >                         reg = <1>;
> > >                         fb_output: endpoint {
> > >                                 remote-endpoint =
> > > <&dp_encoder_input>;
> > >                         };
> > >                 };
> > >         };
> > > };
> > > 
> > > If there is a need to scale the Frame Buffer II IP cores in
> > > the pipeline, each node would have its own node, connected
> > > through ports and endpoints. 
> > > 
> > > hdmi-encoder@......... {
> > >         compatible = "altr,hdmi-tx-16.0";
> > 
> > This was just an example, please use the real compatible string of
> > the HDMI controller (and please submit DT bindings for the HDMI controller
> > :-)). Please also fill the reg property with values from a real example.
> 
> I was trying to get overall picture to be correct before I proceed
> further. We currently do not have support for HDMI therefore I would
> omit this until a HDMI IP is available. The only values are available
> for the Display Port.

No problem. In that case the best option is to replace the HDMI encoder with a 
DisplayPort encoder in the example.

> > >         reg = <.....>;
> > >         /* Other IP-specific properties here */
> > > 
> > >         ports {
> > >                 #address-cells = <1>;
> > >                 #size-cells = <0>;
> > > 
> > >                 port@0 {
> > >                         reg = <0>;
> > >                         hdmi_tx_input: endpoint {
> > >                                 remote-endpoint = <&fb_output>;
> > >                         };
> > >                 };
> > > 
> > >                 port@1 {
> > >                         reg = <1>;
> > >                         hdmi_tx_output: endpoint {
> > >                                 remote-endpoint =
> > > <&hdmi_conn_input>;
> > >                         };
> > >                 };
> > >         };
> > > };
> > > 
> > > hdmi-connector@0 {
> > >         compatible = "hdmi-connector";
> > >         type = "a";
> > > 
> > >         port {
> > >                 hdmi_conn_input: endpoint {
> > >                         remote-endpoint = <&hdmi_tx_output>;
> > >                 };
> > >         };
> > > };


-- 
Regards,

Laurent Pinchart

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Re: [PATCHv6 1/3] ARM:dt-bindings Intel FPGA Video and Image Processing Suite

[Ong, Hean Loong]

Hi Laurent,

I removed the examples for the HDMI in the draft below. The connections
between the VIP and Display Port IP or any display connector are
determined by HW logic. There are currently no SW defined encoders or
connectors that is connected to the AVALON-ST other than the Intel VIP
Frame Buffer II. Therefore there are no examples for the Display Port
encoder and connector.

On Mon, 2017-08-21 at 08:09 +0300, Laurent Pinchart wrote:
> Hi Hean Loong,
> 
> On Monday, 21 August 2017 04:40:09 EEST Ong, Hean Loong wrote:
> > 
> > On Fri, 2017-08-18 at 16:11 +0300, Laurent Pinchart wrote:
> > > 
> > > On Friday 18 Aug 2017 08:34:44 Ong, Hean Loong wrote:
> > > > 
> > > > 
> > > > Hi Laurent,
> > > > Thanks for the comments, I drafted a copy of the DT bindings
> > > > based
> > > > on your recommendations and inputs. I inserted the changes
> > > > below the
> > > > previous comments. 
> > > [snip]
> > > 
> > > > 
> > > > 
> > > > Intel Video and Image Processing(VIP) Frame Buffer II bindings
> > > > 
> > > > Supported hardware: Intel FPGA SoC Arria10 and above with
> > > > display
> > > > portIP
> > > > 
> > > > The Video Frame Buffer II in Video Image Processing (VIP) suite
> > > > is
> > > > an IP core that interfaces between system memory and Avalon-ST
> > > > video
> > > > ports. The IP core can be configured to support the memory
> > > > reader (from
> > > > memory to Avalon-ST) and/or memory writer (from Avalon-ST to
> > > > memory)
> > > > interfaces.
> > > > 
> > > > Connections between the Frame Buffer II and other video IP
> > > > cores in
> > > > the system are modelled using the OF graph DT bindings. The
> > > > Frame
> > > > Buffer II node has up to two OF graph ports. When the memory
> > > > writer
> > > > interface is enabled, port 0 maps to the Avalon-ST Input (din)
> > > > port.
> > > > When the memory reader interface is enabled, port 1 maps to the
> > > > Avalon-
> > > > ST Output (dout) port.
> > > > 
> > > > More information the FPGA video IP component can be acquired
> > > > from
> > > > https://www.altera.com/content/dam/altera-www/global/en_US/pdfs
> > > > \
> > > > /literature/ug/ug_vip.pdf
> > > > 
> > > > New bindings:
> > > > =============
> > > How are the bindings "new" ? You can omit that title.
> > Noted.
> > 
> > > 
> > > > 
> > > > 
> > > > Required properties:
> > > > ----------------------------
> > > > - compatible: "altr,vip-frame-buffer-2.0"
> > > > - reg: Physical base address and length of the framebuffer
> > > > controller's registers.
> > > > - altr,max-width: The maximum width of the framebuffer in
> > > > pixels.
> > > > - altr,max-height: The maximum height of the framebuffer in
> > > > pixels.
> > > > - altr,mem-port-width = the bus width of the avalon master
> > > > port 
> > > > 	on the frame reader
> > > You need to mention the ports here as they are mandatory. I would
> > > move the second paragraph from the introduction to here. You
> > > should also
> > > refer to the file defining the OF graph DT bindings. You can find
> > > examples
> > > in other DT bindings.
> > Noted
> > 
> > > 
> > > > 
> > > > 
> > > > Example:
> > > > ----------------------------
> > > >  +-----+      +-----------+      +------------+      +---------
> > > > --+
> > > >  |  D  |      | Frame     |      | DP/HDMI TX |      |
> > > > DP/HDMI   |
> > > >  |  D  |----->| Buffer II |----->| Controller |----->|
> > > > Connector |
> > > >  |  R  |      |           |      |            |      |         
> > > >   |
> > > >  +-----+      +-----------+      +------------+      +---------
> > > > --+
> > > > 
> > > > framebuffer@100000280 {
> > > >         compatible = "altr,vip-frame-buffer-2.0";
> > > >         reg = <0x00000001 0x00000280 0x00000040>;
> > > >         altr,max-width = <1280>;
> > > >         altr,max-height = <720>;
> > > >         altr,mem-port-width = <128>;
> > > > 
> > > >         ports {
> > > >                 #address-cells = <1>;
> > > >                 #size-cells = <0>;
> > > > 
> > > >                 port@1 {
> > > >                         reg = <1>;
> > > >                         fb_output: endpoint {
> > > >                                 remote-endpoint =
> > > > <&dp_encoder_input>;
> > > >                         };
> > > >                 };
> > > >         };
> > > > };
> > > > 
> > > > If there is a need to scale the Frame Buffer II IP cores in
> > > > the pipeline, each node would have its own node, connected
> > > > through ports and endpoints. 
> > > > 
> > > > hdmi-encoder@......... {
> > > >         compatible = "altr,hdmi-tx-16.0";
> > > This was just an example, please use the real compatible string
> > > of
> > > the HDMI controller (and please submit DT bindings for the HDMI
> > > controller
> > > :-)). Please also fill the reg property with values from a real
> > > example.
> > I was trying to get overall picture to be correct before I proceed
> > further. We currently do not have support for HDMI therefore I
> > would
> > omit this until a HDMI IP is available. The only values are
> > available
> > for the Display Port.
> No problem. In that case the best option is to replace the HDMI
> encoder with a 
> DisplayPort encoder in the example.
> 
> > 
> > > 
> > > > 
> > > >         reg = <.....>;
> > > >         /* Other IP-specific properties here */
> > > > 
> > > >         ports {
> > > >                 #address-cells = <1>;
> > > >                 #size-cells = <0>;
> > > > 
> > > >                 port@0 {
> > > >                         reg = <0>;
> > > >                         hdmi_tx_input: endpoint {
> > > >                                 remote-endpoint = <&fb_output>;
> > > >                         };
> > > >                 };
> > > > 
> > > >                 port@1 {
> > > >                         reg = <1>;
> > > >                         hdmi_tx_output: endpoint {
> > > >                                 remote-endpoint =
> > > > <&hdmi_conn_input>;
> > > >                         };
> > > >                 };
> > > >         };
> > > > };
> > > > 
> > > > hdmi-connector@0 {
> > > >         compatible = "hdmi-connector";
> > > >         type = "a";
> > > > 
> > > >         port {
> > > >                 hdmi_conn_input: endpoint {
> > > >                         remote-endpoint = <&hdmi_tx_output>;
> > > >                 };
> > > >         };
> > > > };
> 

Intel Video and Image Processing(VIP) Frame Buffer II bindings

Supported hardware: Intel FPGA SoC Arria10 and above with display port
IP

The Video Frame Buffer II in Video Image Processing (VIP) suite is an
IP core 
that interfaces between system memory and Avalon-ST video ports. The IP
core 
can be configured to support the memory reader (from memory to Avalon-
ST) 
and/or memory writer (from Avalon-ST to memory) interfaces.

More information the FPGA video IP component can be acquired from
https://www.altera.com/content/dam/altera-www/global/en_US/pdfs\
/literature/ug/ug_vip.pdf

DT-Bindings:
=============
Required properties:
----------------------------
- compatible: "altr,vip-frame-buffer-2.0"
- reg: Physical base address and length of the framebuffer controller's
	registers.
- altr,max-width: The maximum width of the framebuffer in pixels.
- altr,max-height: The maximum height of the framebuffer in pixels.
- altr,mem-port-width = the bus width of the avalon master port 
	on the frame reader

Connections between the Frame Buffer II and other video IP cores in the
system
are modelled using the OF graph DT bindings. The Frame Buffer II node
has up
to two OF graph ports. When the memory writer interface is enabled,
port 0
maps to the Avalon-ST Input (din) port. When the memory reader
interface is
enabled, port 1 maps to the Avalon-ST Output (dout) port.

If there is a need to scale the Frame Buffer II IP cores in
the pipeline, each node would have its own node, connected
through ports and endpoints.

Currently only a Display Port IP input endpoint is supported. 

	Port 0			Port1
---------------------------------------------------------
ARRIA10 AVALON_ST (DIN)		AVALON_ST (DOUT)

Example:
----------------------------
 +-----+      +-----------+      +------------+      +-----------+
 |  D  |      | Frame     |      | DP/HDMI TX |      | DP/HDMI   |
 |  D  |----->| Buffer II |----->| Controller |----->| Connector |
 |  R  |      |           |      |            |      |           |
 +-----+      +-----------+      +------------+      +-----------+

framebuffer@100000280 {
        compatible = "altr,vip-frame-buffer-2.0";
        reg = <0x00000001 0x00000280 0x00000040>;
        altr,max-width = <1280>;
        altr,max-height = <720>;
        altr,mem-port-width = <128>;

        ports {
                #address-cells = <1>;
                #size-cells = <0>;

                port@1 {
                        reg = <1>;
                        fb_output: endpoint {
                                remote-endpoint = <&dp_encoder_input>;
                        };
                };
        };
};
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Re: [PATCHv6 1/3] ARM:dt-bindings Intel FPGA Video and Image Processing Suite

[Laurent Pinchart]

Hi Hean Loong,

On Thursday, 24 August 2017 08:41:50 EEST Ong, Hean Loong wrote:
> Hi Laurent,
> 
> I removed the examples for the HDMI in the draft below. The connections
> between the VIP and Display Port IP or any display connector are
> determined by HW logic. There are currently no SW defined encoders or
> connectors that is connected to the AVALON-ST other than the Intel VIP
> Frame Buffer II. Therefore there are no examples for the Display Port
> encoder and connector.

But there must be an encoder, even if its default configuration makes it 
usable without a softwarer driver at the moment. As the encoder is there in 
hardware, it should be described in DT.

-- 
Regards,

Laurent Pinchart

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Re: [PATCHv6 1/3] ARM:dt-bindings Intel FPGA Video and Image Processing Suite

[Ong, Hean Loong]

Hi Laurent,

The encoder resides as a hardware logic as part of the FPGA fabric. The
software driver has no direct access to the encoder. The VIP is created
in such a way that the software i.e Linux Driver only streams data
through the VIP. What happens beyond the VIP Frame buffer directly
boils down to the FGPA logic design that is provided in the dev kit.

In this example the hardware A10 dev kit has a Display Port IP attached
to the VIP therefore from the drivers perspective we only know that the
endpoint is a Display Port

The system design uses the VIP FRame Buffer II as the default display
interface for various FPGA display IP (HDMI/DP). The FPGA bridge design
only provides the drivers to access the VIP.

Note there is also a soft Processor running on the FPGA that drives the
video signal transceivers for the Display Port or any other display
IP. 

The encoder used for the Intel FPGA VIP are hardware based therefore
the video device that is concerned here is the VIP Frame Buffer device
which streams data to whatever FPGA display hardware.

To describe the hardware encoder do I need to create it as part of the
device tree node or a explanation of it would suffice ?

On Thu, 2017-08-24 at 12:39 +0300, Laurent Pinchart wrote:
> Hi Hean Loong,
> 
> On Thursday, 24 August 2017 08:41:50 EEST Ong, Hean Loong wrote:
> > 
> > Hi Laurent,
> > 
> > I removed the examples for the HDMI in the draft below. The
> > connections
> > between the VIP and Display Port IP or any display connector are
> > determined by HW logic. There are currently no SW defined encoders
> > or
> > connectors that is connected to the AVALON-ST other than the Intel
> > VIP
> > Frame Buffer II. Therefore there are no examples for the Display
> > Port
> > encoder and connector.
> But there must be an encoder, even if its default configuration makes
> it 
> usable without a softwarer driver at the moment. As the encoder is
> there in 
> hardware, it should be described in DT.
> 
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Re: [PATCHv6 1/3] ARM:dt-bindings Intel FPGA Video and Image Processing Suite

[Laurent Pinchart]

Hello Hean Loon,

On Friday, 25 August 2017 04:21:17 EEST Ong, Hean Loong wrote:
> Hi Laurent,
> 
> The encoder resides as a hardware logic as part of the FPGA fabric. The
> software driver has no direct access to the encoder. The VIP is created
> in such a way that the software i.e Linux Driver only streams data
> through the VIP. What happens beyond the VIP Frame buffer directly
> boils down to the FGPA logic design that is provided in the dev kit.
> 
> In this example the hardware A10 dev kit has a Display Port IP attached
> to the VIP therefore from the drivers perspective we only know that the
> endpoint is a Display Port
> 
> The system design uses the VIP FRame Buffer II as the default display
> interface for various FPGA display IP (HDMI/DP). The FPGA bridge design
> only provides the drivers to access the VIP.
> 
> Note there is also a soft Processor running on the FPGA that drives the
> video signal transceivers for the Display Port or any other display
> IP. 
> 
> The encoder used for the Intel FPGA VIP are hardware based therefore
> the video device that is concerned here is the VIP Frame Buffer device
> which streams data to whatever FPGA display hardware.
> 
> To describe the hardware encoder do I need to create it as part of the
> device tree node or a explanation of it would suffice ?

Regardless of whether the display port encoder is a soft IP or a hard IP, it 
should be described in DT as it is there. Obviously it should not be 
controlled by the VIP Frame Buffer II driver, but I expect at least some of 
the encoders to have registers exposed to the ARM processor running Linux, so 
you will need a device driver for them at some point.

-- 
Regards,

Laurent Pinchart

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Re: [PATCHv6 1/3] ARM:dt-bindings Intel FPGA Video and Image Processing Suite

[Ong, Hean Loong]

Hi Laurent,

On Thu, 2017-08-24 at 12:39 +0300, Laurent Pinchart wrote:
> Hi Hean Loong,
> 
> On Thursday, 24 August 2017 08:41:50 EEST Ong, Hean Loong wrote:
> > 
> > Hi Laurent,
> > 
> > I removed the examples for the HDMI in the draft below. The
> > connections
> > between the VIP and Display Port IP or any display connector are
> > determined by HW logic. There are currently no SW defined encoders
> > or
> > connectors that is connected to the AVALON-ST other than the Intel
> > VIP
> > Frame Buffer II. Therefore there are no examples for the Display
> > Port
> > encoder and connector.
> But there must be an encoder, even if its default configuration makes
> it 
> usable without a softwarer driver at the moment. As the encoder is
> there in 
> hardware, it should be described in DT.
> 
I attach some links regarding the simple example designs for the
Display Port IP

The link below has a example design of how the VIP is built along with
the Display Port IP 
into the FPGA connected to the DDR RAM accessed by ARM or any
controller. Please look at the
Introduction section of the link below
http://www.alterawiki.com/wiki/DisplayPort_Design_Example_14.0_(RX_and_
TX)#DisplayPort_IP_Core

The proposed design in the link above and the design we are
implementing are almost the same (FPGA part)
That the Intel(Altera) FPGA VIP is the sole interface for the ARM
controller to connect to via memory mapping
on the DDR

Please go to Source Functional Description section in the PDF below. It
has information
on how the encoder is built for the FPGA design of the Display Port
https://www.altera.com/ja_JP/pdfs/literature/ug/ug_displayport.pdf

More information on the Display Port IP encoder could be found in the
link below.
The Tx Transceiver interface has some information on how the source
clocks works in
the FPGA tranceiver
https://www.altera.com/documentation/hco1410462777019.html#hco141046232
3311
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Re: [PATCHv6 1/3] ARM:dt-bindings Intel FPGA Video and Image Processing Suite

[Ong, Hean Loong]

Hi Laurent,

On Mon, 2017-08-28 at 13:06 +0800, Ong, Hean Loong wrote:
> Hi Laurent,
> 
> On Thu, 2017-08-24 at 12:39 +0300, Laurent Pinchart wrote:
> > 
> > Hi Hean Loong,
> > 
> > On Thursday, 24 August 2017 08:41:50 EEST Ong, Hean Loong wrote:
> > > 
> > > 
> > > Hi Laurent,
> > > 
> > > I removed the examples for the HDMI in the draft below. The
> > > connections
> > > between the VIP and Display Port IP or any display connector are
> > > determined by HW logic. There are currently no SW defined
> > > encoders
> > > or
> > > connectors that is connected to the AVALON-ST other than the
> > > Intel
> > > VIP
> > > Frame Buffer II. Therefore there are no examples for the Display
> > > Port
> > > encoder and connector.
> > But there must be an encoder, even if its default configuration
> > makes
> > it 
> > usable without a softwarer driver at the moment. As the encoder is
> > there in 
> > hardware, it should be described in DT.
> > 
> I attach some links regarding the simple example designs for the
> Display Port IP
> 
> The link below has a example design of how the VIP is built along
> with
> the Display Port IP 
> into the FPGA connected to the DDR RAM accessed by ARM or any
> controller. Please look at the
> Introduction section of the link below
> http://www.alterawiki.com/wiki/DisplayPort_Design_Example_14.0_(RX_an
> d_
> TX)#DisplayPort_IP_Core
> 
> The proposed design in the link above and the design we are
> implementing are almost the same (FPGA part)
> That the Intel(Altera) FPGA VIP is the sole interface for the ARM
> controller to connect to via memory mapping
> on the DDR
> 
> Please go to Source Functional Description section in the PDF below.
> It
> has information
> on how the encoder is built for the FPGA design of the Display Port
> https://www.altera.com/ja_JP/pdfs/literature/ug/ug_displayport.pdf
> 
> More information on the Display Port IP encoder could be found in the
> link below.
> The Tx Transceiver interface has some information on how the source
> clocks works in
> the FPGA tranceiver
> https://www.altera.com/documentation/hco1410462777019.html#hco1410462
> 32
> 3311

Would the information provided in the above links suffice to explain
the relationship between DDR, VIP and Display Port IP ?

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Re: [PATCHv6 1/3] ARM:dt-bindings Intel FPGA Video and Image Processing Suite

[Laurent Pinchart]

Hi Hean Loong,

On Monday, 4 September 2017 09:09:11 EEST Ong, Hean Loong wrote:
> On Mon, 2017-08-28 at 13:06 +0800, Ong, Hean Loong wrote:
> > On Thu, 2017-08-24 at 12:39 +0300, Laurent Pinchart wrote:
> >> On Thursday, 24 August 2017 08:41:50 EEST Ong, Hean Loong wrote:
> >>> 
> >>> Hi Laurent,
> >>> 
> >>> I removed the examples for the HDMI in the draft below. The
> >>> connections between the VIP and Display Port IP or any display
> >>> connector are determined by HW logic. There are currently no SW
> >>> defined encoders or connectors that is connected to the AVALON-ST
> >>> other than the Intel VIP Frame Buffer II. Therefore there are no
> >>> examples for the Display Port encoder and connector.
> >> 
> >> But there must be an encoder, even if its default configuration
> >> makes it usable without a softwarer driver at the moment. As the
> >> encoder is there in hardware, it should be described in DT.
> > 
> > I attach some links regarding the simple example designs for the
> > Display Port IP
> > 
> > The link below has a example design of how the VIP is built along
> > with the Display Port IP  into the FPGA connected to the DDR RAM accessed
> > by ARM or any controller. Please look at the Introduction section of the
> > link below
> > http://www.alterawiki.com/wiki/DisplayPort_Design_Example_14.0_(RX_an
> > d_TX)#DisplayPort_IP_Core
> > 
> > The proposed design in the link above and the design we are
> > implementing are almost the same (FPGA part)
> > That the Intel(Altera) FPGA VIP is the sole interface for the ARM
> > controller to connect to via memory mapping on the DDR
> > 
> > Please go to Source Functional Description section in the PDF below.
> > It has information on how the encoder is built for the FPGA design of the
> > Display Port
> > https://www.altera.com/ja_JP/pdfs/literature/ug/ug_displayport.pdf
> > 
> > More information on the Display Port IP encoder could be found in the
> > link below. The Tx Transceiver interface has some information on how the
> > source clocks works in the FPGA tranceiver
> > https://www.altera.com/documentation/hco1410462777019.html#hco1410462
> > 323311
> 
> Would the information provided in the above links suffice to explain
> the relationship between DDR, VIP and Display Port IP ?

It does, thank you, and sorry for the late reply.

The documents you've provided show that the Display Port transmitter is an IP 
core in the FPGA, connected to the VIP output, and configurable from the ARM 
side through memory-mapped registers. It should thus be modelled in DT with a 
separate DT node, and connections should be modelled using the OF graph DT 
bindings, like you've done in the latest version of your patch series.

The Display Port transmitter should also have DT bindings, and a Linux kernel 
driver, but that can be submitted in a separate patch series.

-- 
Regards,

Laurent Pinchart

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