From: "Kani, Toshi" <toshi.kani@hpe.com>
To: "torvalds@linux-foundation.org" <torvalds@linux-foundation.org>,
"benh@kernel.crashing.org" <benh@kernel.crashing.org>
Cc: "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"alex.williamson@redhat.com" <alex.williamson@redhat.com>,
"linux-block@vger.kernel.org" <linux-block@vger.kernel.org>,
"linux-rdma@vger.kernel.org" <linux-rdma@vger.kernel.org>,
"hch@lst.de" <hch@lst.de>, "axboe@kernel.dk" <axboe@kernel.dk>,
"linux-nvdimm@lists.01.org" <linux-nvdimm@lists.01.org>,
"jglisse@redhat.com" <jglisse@redhat.com>,
"linux-nvme@lists.infradead.org" <linux-nvme@lists.infradead.org>,
"maxg@mellanox.com" <maxg@mellanox.com>,
"linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
"keith.busch@intel.com" <keith.busch@intel.com>,
"oliveroh@au1.ibm.com" <oliveroh@au1.ibm.com>,
"jgg@ziepe.ca" <jgg@ziepe.ca>,
"bhelgaas@google.com" <bhelgaas@google.com>
Subject: Re: [PATCH v2 00/10] Copy Offload in NVMe Fabrics with P2P PCI Memory
Date: Fri, 2 Mar 2018 16:22:24 +0000 [thread overview]
Message-ID: <1520010446.2693.19.camel@hpe.com> (raw)
In-Reply-To: <1519943658.4592.34.camel@kernel.crashing.org>
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WARNING: multiple messages have this Message-ID (diff)
From: "Kani, Toshi" <toshi.kani@hpe.com>
To: "torvalds@linux-foundation.org" <torvalds@linux-foundation.org>,
"benh@kernel.crashing.org" <benh@kernel.crashing.org>
Cc: "axboe@kernel.dk" <axboe@kernel.dk>,
"keith.busch@intel.com" <keith.busch@intel.com>,
"oliveroh@au1.ibm.com" <oliveroh@au1.ibm.com>,
"linux-nvdimm@lists.01.org" <linux-nvdimm@lists.01.org>,
"linux-rdma@vger.kernel.org" <linux-rdma@vger.kernel.org>,
"linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"linux-nvme@lists.infradead.org" <linux-nvme@lists.infradead.org>,
"linux-block@vger.kernel.org" <linux-block@vger.kernel.org>,
"jgg@ziepe.ca" <jgg@ziepe.ca>,
"alex.williamson@redhat.com" <alex.williamson@redhat.com>,
"jglisse@redhat.com" <jglisse@redhat.com>,
"bhelgaas@google.com" <bhelgaas@google.com>,
"maxg@mellanox.com" <maxg@mellanox.com>,
"hch@lst.de" <hch@lst.de>
Subject: Re: [PATCH v2 00/10] Copy Offload in NVMe Fabrics with P2P PCI Memory
Date: Fri, 2 Mar 2018 16:22:24 +0000 [thread overview]
Message-ID: <1520010446.2693.19.camel@hpe.com> (raw)
In-Reply-To: <1519943658.4592.34.camel@kernel.crashing.org>
On Fri, 2018-03-02 at 09:34 +1100, Benjamin Herrenschmidt wrote:
> On Thu, 2018-03-01 at 14:31 -0800, Linus Torvalds wrote:
> > On Thu, Mar 1, 2018 at 2:06 PM, Benjamin Herrenschmidt <benh@au1.ibm.com> wrote:
> > >
> > > Could be that x86 has the smarts to do the right thing, still trying to
> > > untangle the code :-)
> >
> > Afaik, x86 will not cache PCI unless the system is misconfigured, and
> > even then it's more likely to just raise a machine check exception
> > than cache things.
> >
> > The last-level cache is going to do fills and spills directly to the
> > memory controller, not to the PCIe side of things.
> >
> > (I guess you *can* do things differently, and I wouldn't be surprised
> > if some people inside Intel did try to do things differently with
> > trying nvram over PCIe, but in general I think the above is true)
> >
> > You won't find it in the kernel code either. It's in hardware with
> > firmware configuration of what addresses are mapped to the memory
> > controllers (and _how_ they are mapped) and which are not.
>
> Ah thanks ! Thanks explains. We can fix that on ppc64 in our linear
> mapping code by checking the address vs. memblocks to chose the right
> page table attributes.
FWIW, this thing is called MTRRs on x86, which are initialized by BIOS.
These registers effectively overwrite page table setups. Intel SDM
defines the effect as follows. 'PAT Entry Value' is the page table
setup.
MTRR Memory Type PAT Entry Value Effective Memory Type
--------------------------------------------------------
UC UC UC
UC WC WC
UC WT UC
UC WB UC
UC WP UC
On my system, BIOS sets MTRRs to cover the entire MMIO ranges with UC.
Other BIOSes may simply set the MTRR default type to UC, i.e. uncovered
ranges become UC.
# cat /proc/mtrr
:
reg01: base=0xc0000000000 (12582912MB), size=2097152MB, count=1:
uncachable
:
# cat /proc/iomem | grep 'PCI Bus'
:
c0000000000-c3fffffffff : PCI Bus 0000:00
c4000000000-c7fffffffff : PCI Bus 0000:11
c8000000000-cbfffffffff : PCI Bus 0000:36
cc000000000-cffffffffff : PCI Bus 0000:5b
d0000000000-d3fffffffff : PCI Bus 0000:80
d4000000000-d7fffffffff : PCI Bus 0000:85
d8000000000-dbfffffffff : PCI Bus 0000:ae
dc000000000-dffffffffff : PCI Bus 0000:d7
-Toshi
_______________________________________________
Linux-nvdimm mailing list
Linux-nvdimm@lists.01.org
https://lists.01.org/mailman/listinfo/linux-nvdimm
WARNING: multiple messages have this Message-ID (diff)
From: toshi.kani@hpe.com (Kani, Toshi)
Subject: [PATCH v2 00/10] Copy Offload in NVMe Fabrics with P2P PCI Memory
Date: Fri, 2 Mar 2018 16:22:24 +0000 [thread overview]
Message-ID: <1520010446.2693.19.camel@hpe.com> (raw)
In-Reply-To: <1519943658.4592.34.camel@kernel.crashing.org>
On Fri, 2018-03-02@09:34 +1100, Benjamin Herrenschmidt wrote:
> On Thu, 2018-03-01@14:31 -0800, Linus Torvalds wrote:
> > On Thu, Mar 1, 2018@2:06 PM, Benjamin Herrenschmidt <benh@au1.ibm.com> wrote:
> > >
> > > Could be that x86 has the smarts to do the right thing, still trying to
> > > untangle the code :-)
> >
> > Afaik, x86 will not cache PCI unless the system is misconfigured, and
> > even then it's more likely to just raise a machine check exception
> > than cache things.
> >
> > The last-level cache is going to do fills and spills directly to the
> > memory controller, not to the PCIe side of things.
> >
> > (I guess you *can* do things differently, and I wouldn't be surprised
> > if some people inside Intel did try to do things differently with
> > trying nvram over PCIe, but in general I think the above is true)
> >
> > You won't find it in the kernel code either. It's in hardware with
> > firmware configuration of what addresses are mapped to the memory
> > controllers (and _how_ they are mapped) and which are not.
>
> Ah thanks ! Thanks explains. We can fix that on ppc64 in our linear
> mapping code by checking the address vs. memblocks to chose the right
> page table attributes.
FWIW, this thing is called MTRRs on x86, which are initialized by BIOS.
These registers effectively overwrite page table setups. Intel SDM
defines the effect as follows. 'PAT Entry Value' is the page table
setup.
MTRR Memory Type PAT Entry Value Effective Memory Type
--------------------------------------------------------
UC UC UC
UC WC WC
UC WT UC
UC WB UC
UC WP UC
On my system, BIOS sets MTRRs to cover the entire MMIO ranges with UC.
Other BIOSes may simply set the MTRR default type to UC, i.e. uncovered
ranges become UC.
# cat /proc/mtrr
:
reg01: base=0xc0000000000 (12582912MB), size=2097152MB, count=1:
uncachable
:
# cat /proc/iomem | grep 'PCI Bus'
:
c0000000000-c3fffffffff : PCI Bus 0000:00
c4000000000-c7fffffffff : PCI Bus 0000:11
c8000000000-cbfffffffff : PCI Bus 0000:36
cc000000000-cffffffffff : PCI Bus 0000:5b
d0000000000-d3fffffffff : PCI Bus 0000:80
d4000000000-d7fffffffff : PCI Bus 0000:85
d8000000000-dbfffffffff : PCI Bus 0000:ae
dc000000000-dffffffffff : PCI Bus 0000:d7
-Toshi
WARNING: multiple messages have this Message-ID (diff)
From: "Kani, Toshi" <toshi.kani-ZPxbGqLxI0U@public.gmane.org>
To: "torvalds-de/tnXTf+JLsfHDXvbKv3WD2FQJk+8+b@public.gmane.org"
<torvalds-de/tnXTf+JLsfHDXvbKv3WD2FQJk+8+b@public.gmane.org>,
"benh-XVmvHMARGAS8U2dJNN8I7kB+6BGkLq7r@public.gmane.org"
<benh-XVmvHMARGAS8U2dJNN8I7kB+6BGkLq7r@public.gmane.org>
Cc: "axboe-tSWWG44O7X1aa/9Udqfwiw@public.gmane.org"
<axboe-tSWWG44O7X1aa/9Udqfwiw@public.gmane.org>,
"keith.busch-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org"
<keith.busch-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>,
"oliveroh-8fk3Idey6ehBDgjK7y7TUQ@public.gmane.org"
<oliveroh-8fk3Idey6ehBDgjK7y7TUQ@public.gmane.org>,
"linux-nvdimm-hn68Rpc1hR1g9hUCZPvPmw@public.gmane.org"
<linux-nvdimm-hn68Rpc1hR1g9hUCZPvPmw@public.gmane.org>,
"linux-rdma-u79uwXL29TY76Z2rM5mHXA@public.gmane.org"
<linux-rdma-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>,
"linux-pci-u79uwXL29TY76Z2rM5mHXA@public.gmane.org"
<linux-pci-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>,
"linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org"
<linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>,
"linux-nvme-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org"
<linux-nvme-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org>,
"linux-block-u79uwXL29TY76Z2rM5mHXA@public.gmane.org"
<linux-block-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>,
"jgg-uk2M96/98Pc@public.gmane.org"
<jgg-uk2M96/98Pc@public.gmane.org>,
"alex.williamson-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org"
<alex.williamson-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>,
"jglisse-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org"
<jglisse-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>,
"bhelgaas-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org"
<bhelgaas-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org>,
"maxg-VPRAkNaXOzVWk0Htik3J/w@public.gmane.org"
<maxg-VPRAkNaXOzVWk0Htik3J/w@public.gmane.org>,
"hch-jcswGhMUV9g@public.gmane.org"
<hch-jcswGhMUV9g@public.gmane.org>
Subject: Re: [PATCH v2 00/10] Copy Offload in NVMe Fabrics with P2P PCI Memory
Date: Fri, 2 Mar 2018 16:22:24 +0000 [thread overview]
Message-ID: <1520010446.2693.19.camel@hpe.com> (raw)
In-Reply-To: <1519943658.4592.34.camel-XVmvHMARGAS8U2dJNN8I7kB+6BGkLq7r@public.gmane.org>
On Fri, 2018-03-02 at 09:34 +1100, Benjamin Herrenschmidt wrote:
> On Thu, 2018-03-01 at 14:31 -0800, Linus Torvalds wrote:
> > On Thu, Mar 1, 2018 at 2:06 PM, Benjamin Herrenschmidt <benh-8fk3Idey6ehBDgjK7y7TUQ@public.gmane.org> wrote:
> > >
> > > Could be that x86 has the smarts to do the right thing, still trying to
> > > untangle the code :-)
> >
> > Afaik, x86 will not cache PCI unless the system is misconfigured, and
> > even then it's more likely to just raise a machine check exception
> > than cache things.
> >
> > The last-level cache is going to do fills and spills directly to the
> > memory controller, not to the PCIe side of things.
> >
> > (I guess you *can* do things differently, and I wouldn't be surprised
> > if some people inside Intel did try to do things differently with
> > trying nvram over PCIe, but in general I think the above is true)
> >
> > You won't find it in the kernel code either. It's in hardware with
> > firmware configuration of what addresses are mapped to the memory
> > controllers (and _how_ they are mapped) and which are not.
>
> Ah thanks ! Thanks explains. We can fix that on ppc64 in our linear
> mapping code by checking the address vs. memblocks to chose the right
> page table attributes.
FWIW, this thing is called MTRRs on x86, which are initialized by BIOS.
These registers effectively overwrite page table setups. Intel SDM
defines the effect as follows. 'PAT Entry Value' is the page table
setup.
MTRR Memory Type PAT Entry Value Effective Memory Type
--------------------------------------------------------
UC UC UC
UC WC WC
UC WT UC
UC WB UC
UC WP UC
On my system, BIOS sets MTRRs to cover the entire MMIO ranges with UC.
Other BIOSes may simply set the MTRR default type to UC, i.e. uncovered
ranges become UC.
# cat /proc/mtrr
:
reg01: base=0xc0000000000 (12582912MB), size=2097152MB, count=1:
uncachable
:
# cat /proc/iomem | grep 'PCI Bus'
:
c0000000000-c3fffffffff : PCI Bus 0000:00
c4000000000-c7fffffffff : PCI Bus 0000:11
c8000000000-cbfffffffff : PCI Bus 0000:36
cc000000000-cffffffffff : PCI Bus 0000:5b
d0000000000-d3fffffffff : PCI Bus 0000:80
d4000000000-d7fffffffff : PCI Bus 0000:85
d8000000000-dbfffffffff : PCI Bus 0000:ae
dc000000000-dffffffffff : PCI Bus 0000:d7
-Toshi
WARNING: multiple messages have this Message-ID (diff)
From: "Kani, Toshi" <toshi.kani@hpe.com>
To: "torvalds@linux-foundation.org" <torvalds@linux-foundation.org>,
"benh@kernel.crashing.org" <benh@kernel.crashing.org>
Cc: "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"alex.williamson@redhat.com" <alex.williamson@redhat.com>,
"linux-block@vger.kernel.org" <linux-block@vger.kernel.org>,
"linux-rdma@vger.kernel.org" <linux-rdma@vger.kernel.org>,
"hch@lst.de" <hch@lst.de>, "axboe@kernel.dk" <axboe@kernel.dk>,
"linux-nvdimm@lists.01.org" <linux-nvdimm@lists.01.org>,
"jglisse@redhat.com" <jglisse@redhat.com>,
"linux-nvme@lists.infradead.org" <linux-nvme@lists.infradead.org>,
"maxg@mellanox.com" <maxg@mellanox.com>,
"linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
"keith.busch@intel.com" <keith.busch@intel.com>,
"oliveroh@au1.ibm.com" <oliveroh@au1.ibm.com>,
"jgg@ziepe.ca" <jgg@ziepe.ca>,
"bhelgaas@google.com" <bhelgaas@google.com>
Subject: Re: [PATCH v2 00/10] Copy Offload in NVMe Fabrics with P2P PCI Memory
Date: Fri, 2 Mar 2018 16:22:24 +0000 [thread overview]
Message-ID: <1520010446.2693.19.camel@hpe.com> (raw)
In-Reply-To: <1519943658.4592.34.camel@kernel.crashing.org>
On Fri, 2018-03-02 at 09:34 +1100, Benjamin Herrenschmidt wrote:
> On Thu, 2018-03-01 at 14:31 -0800, Linus Torvalds wrote:
> > On Thu, Mar 1, 2018 at 2:06 PM, Benjamin Herrenschmidt <benh@au1.ibm.com> wrote:
> > >
> > > Could be that x86 has the smarts to do the right thing, still trying to
> > > untangle the code :-)
> >
> > Afaik, x86 will not cache PCI unless the system is misconfigured, and
> > even then it's more likely to just raise a machine check exception
> > than cache things.
> >
> > The last-level cache is going to do fills and spills directly to the
> > memory controller, not to the PCIe side of things.
> >
> > (I guess you *can* do things differently, and I wouldn't be surprised
> > if some people inside Intel did try to do things differently with
> > trying nvram over PCIe, but in general I think the above is true)
> >
> > You won't find it in the kernel code either. It's in hardware with
> > firmware configuration of what addresses are mapped to the memory
> > controllers (and _how_ they are mapped) and which are not.
>
> Ah thanks ! Thanks explains. We can fix that on ppc64 in our linear
> mapping code by checking the address vs. memblocks to chose the right
> page table attributes.
FWIW, this thing is called MTRRs on x86, which are initialized by BIOS.
These registers effectively overwrite page table setups. Intel SDM
defines the effect as follows. 'PAT Entry Value' is the page table
setup.
MTRR Memory Type PAT Entry Value Effective Memory Type
--------------------------------------------------------
UC UC UC
UC WC WC
UC WT UC
UC WB UC
UC WP UC
On my system, BIOS sets MTRRs to cover the entire MMIO ranges with UC.
Other BIOSes may simply set the MTRR default type to UC, i.e. uncovered
ranges become UC.
# cat /proc/mtrr
:
reg01: base=0xc0000000000 (12582912MB), size=2097152MB, count=1:
uncachable
:
# cat /proc/iomem | grep 'PCI Bus'
:
c0000000000-c3fffffffff : PCI Bus 0000:00
c4000000000-c7fffffffff : PCI Bus 0000:11
c8000000000-cbfffffffff : PCI Bus 0000:36
cc000000000-cffffffffff : PCI Bus 0000:5b
d0000000000-d3fffffffff : PCI Bus 0000:80
d4000000000-d7fffffffff : PCI Bus 0000:85
d8000000000-dbfffffffff : PCI Bus 0000:ae
dc000000000-dffffffffff : PCI Bus 0000:d7
-Toshi
next prev parent reply other threads:[~2018-03-02 16:22 UTC|newest]
Thread overview: 504+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-02-28 23:39 [PATCH v2 00/10] Copy Offload in NVMe Fabrics with P2P PCI Memory Logan Gunthorpe
2018-02-28 23:39 ` Logan Gunthorpe
2018-02-28 23:39 ` Logan Gunthorpe
2018-02-28 23:39 ` Logan Gunthorpe
2018-02-28 23:39 ` [PATCH v2 01/10] PCI/P2PDMA: Support peer to peer memory Logan Gunthorpe
2018-02-28 23:39 ` Logan Gunthorpe
2018-02-28 23:39 ` Logan Gunthorpe
2018-03-01 17:37 ` Bjorn Helgaas
2018-03-01 17:37 ` Bjorn Helgaas
2018-03-01 17:37 ` Bjorn Helgaas
2018-03-01 17:37 ` Bjorn Helgaas
2018-03-01 18:55 ` Logan Gunthorpe
2018-03-01 18:55 ` Logan Gunthorpe
2018-03-01 18:55 ` Logan Gunthorpe
2018-03-01 18:55 ` Logan Gunthorpe
2018-03-01 23:00 ` Bjorn Helgaas
2018-03-01 23:00 ` Bjorn Helgaas
2018-03-01 23:00 ` Bjorn Helgaas
2018-03-01 23:00 ` Bjorn Helgaas
2018-03-01 23:06 ` Logan Gunthorpe
2018-03-01 23:06 ` Logan Gunthorpe
2018-03-01 23:06 ` Logan Gunthorpe
2018-03-01 23:06 ` Logan Gunthorpe
2018-03-01 23:14 ` Stephen Bates
2018-03-01 23:14 ` Stephen Bates
2018-03-01 23:14 ` Stephen Bates
2018-03-01 23:14 ` Stephen Bates
2018-03-01 23:14 ` Stephen Bates
2018-03-01 23:45 ` Bjorn Helgaas
2018-03-01 23:45 ` Bjorn Helgaas
2018-03-01 23:45 ` Bjorn Helgaas
2018-03-01 23:45 ` Bjorn Helgaas
2018-02-28 23:39 ` [PATCH v2 02/10] PCI/P2PDMA: Add sysfs group to display p2pmem stats Logan Gunthorpe
2018-02-28 23:39 ` Logan Gunthorpe
2018-02-28 23:39 ` Logan Gunthorpe
2018-02-28 23:39 ` Logan Gunthorpe
2018-03-01 17:44 ` Bjorn Helgaas
2018-03-01 17:44 ` Bjorn Helgaas
2018-03-01 17:44 ` Bjorn Helgaas
2018-03-01 17:44 ` Bjorn Helgaas
2018-03-02 0:15 ` Logan Gunthorpe
2018-03-02 0:15 ` Logan Gunthorpe
2018-03-02 0:15 ` Logan Gunthorpe
2018-03-02 0:15 ` Logan Gunthorpe
2018-03-02 0:36 ` Dan Williams
2018-03-02 0:36 ` Dan Williams
2018-03-02 0:36 ` Dan Williams
2018-03-02 0:36 ` Dan Williams
2018-03-02 0:37 ` Logan Gunthorpe
2018-03-02 0:37 ` Logan Gunthorpe
2018-03-02 0:37 ` Logan Gunthorpe
2018-03-02 0:37 ` Logan Gunthorpe
2018-02-28 23:39 ` [PATCH v2 03/10] PCI/P2PDMA: Add PCI p2pmem dma mappings to adjust the bus offset Logan Gunthorpe
2018-02-28 23:39 ` Logan Gunthorpe
2018-02-28 23:39 ` Logan Gunthorpe
2018-03-01 17:49 ` Bjorn Helgaas
2018-03-01 17:49 ` Bjorn Helgaas
2018-03-01 17:49 ` Bjorn Helgaas
2018-03-01 17:49 ` Bjorn Helgaas
2018-03-01 19:36 ` Logan Gunthorpe
2018-03-01 19:36 ` Logan Gunthorpe
2018-03-01 19:36 ` Logan Gunthorpe
2018-03-01 19:36 ` Logan Gunthorpe
2018-02-28 23:40 ` [PATCH v2 04/10] PCI/P2PDMA: Clear ACS P2P flags for all devices behind switches Logan Gunthorpe
2018-02-28 23:40 ` Logan Gunthorpe
2018-02-28 23:40 ` Logan Gunthorpe
2018-02-28 23:40 ` Logan Gunthorpe
2018-03-01 18:02 ` Bjorn Helgaas
2018-03-01 18:02 ` Bjorn Helgaas
2018-03-01 18:02 ` Bjorn Helgaas
2018-03-01 18:02 ` Bjorn Helgaas
2018-03-01 18:54 ` Stephen Bates
2018-03-01 18:54 ` Stephen Bates
2018-03-01 18:54 ` Stephen Bates
2018-03-01 18:54 ` Stephen Bates
2018-03-01 18:54 ` Stephen Bates
2018-03-01 21:21 ` Alex Williamson
2018-03-01 21:21 ` Alex Williamson
2018-03-01 21:21 ` Alex Williamson
2018-03-01 21:21 ` Alex Williamson
2018-03-01 21:26 ` Logan Gunthorpe
2018-03-01 21:26 ` Logan Gunthorpe
2018-03-01 21:26 ` Logan Gunthorpe
2018-03-01 21:26 ` Logan Gunthorpe
2018-03-01 21:32 ` Stephen Bates
2018-03-01 21:32 ` Stephen Bates
2018-03-01 21:32 ` Stephen Bates
2018-03-01 21:32 ` Stephen Bates
2018-03-01 21:32 ` Stephen Bates
2018-03-01 21:35 ` Jerome Glisse
2018-03-01 21:35 ` Jerome Glisse
2018-03-01 21:35 ` Jerome Glisse
2018-03-01 21:35 ` Jerome Glisse
2018-03-01 21:35 ` Jerome Glisse
2018-03-01 21:37 ` Logan Gunthorpe
2018-03-01 21:37 ` Logan Gunthorpe
2018-03-01 21:37 ` Logan Gunthorpe
2018-03-01 21:37 ` Logan Gunthorpe
2018-03-01 23:15 ` Bjorn Helgaas
2018-03-01 23:15 ` Bjorn Helgaas
2018-03-01 23:15 ` Bjorn Helgaas
2018-03-01 23:15 ` Bjorn Helgaas
2018-03-01 23:59 ` Logan Gunthorpe
2018-03-01 23:59 ` Logan Gunthorpe
2018-03-01 23:59 ` Logan Gunthorpe
2018-03-01 23:59 ` Logan Gunthorpe
2018-03-01 19:13 ` Logan Gunthorpe
2018-03-01 19:13 ` Logan Gunthorpe
2018-03-01 19:13 ` Logan Gunthorpe
2018-03-01 19:13 ` Logan Gunthorpe
2018-03-05 22:28 ` Bjorn Helgaas
2018-03-05 22:28 ` Bjorn Helgaas
2018-03-05 22:28 ` Bjorn Helgaas
2018-03-05 22:28 ` Bjorn Helgaas
2018-03-05 23:01 ` Logan Gunthorpe
2018-03-05 23:01 ` Logan Gunthorpe
2018-03-05 23:01 ` Logan Gunthorpe
2018-03-05 23:01 ` Logan Gunthorpe
2018-02-28 23:40 ` [PATCH v2 05/10] block: Introduce PCI P2P flags for request and request queue Logan Gunthorpe
2018-02-28 23:40 ` Logan Gunthorpe
2018-02-28 23:40 ` Logan Gunthorpe
2018-02-28 23:40 ` Logan Gunthorpe
2018-03-01 11:08 ` Sagi Grimberg
2018-03-01 11:08 ` Sagi Grimberg
2018-03-01 11:08 ` Sagi Grimberg
2018-03-01 11:08 ` Sagi Grimberg
2018-02-28 23:40 ` [PATCH v2 06/10] IB/core: Add optional PCI P2P flag to rdma_rw_ctx_[init|destroy]() Logan Gunthorpe
2018-02-28 23:40 ` Logan Gunthorpe
2018-02-28 23:40 ` Logan Gunthorpe
2018-02-28 23:40 ` Logan Gunthorpe
2018-03-01 10:32 ` Sagi Grimberg
2018-03-01 10:32 ` Sagi Grimberg
2018-03-01 10:32 ` Sagi Grimberg
2018-03-01 10:32 ` Sagi Grimberg
2018-03-01 17:16 ` Logan Gunthorpe
2018-03-01 17:16 ` Logan Gunthorpe
2018-03-01 17:16 ` Logan Gunthorpe
2018-03-01 17:16 ` Logan Gunthorpe
2018-02-28 23:40 ` [PATCH v2 07/10] nvme-pci: Use PCI p2pmem subsystem to manage the CMB Logan Gunthorpe
2018-02-28 23:40 ` Logan Gunthorpe
2018-02-28 23:40 ` Logan Gunthorpe
2018-02-28 23:40 ` Logan Gunthorpe
2018-03-05 1:33 ` Oliver
2018-03-05 1:33 ` Oliver
2018-03-05 1:33 ` Oliver
2018-03-05 1:33 ` Oliver
2018-03-05 16:00 ` Keith Busch
2018-03-05 16:00 ` Keith Busch
2018-03-05 16:00 ` Keith Busch
2018-03-05 16:00 ` Keith Busch
2018-03-05 17:10 ` Logan Gunthorpe
2018-03-05 17:10 ` Logan Gunthorpe
2018-03-05 17:10 ` Logan Gunthorpe
2018-03-05 17:10 ` Logan Gunthorpe
2018-03-05 18:02 ` Sinan Kaya
2018-03-05 18:02 ` Sinan Kaya
2018-03-05 18:02 ` Sinan Kaya
2018-03-05 18:09 ` Logan Gunthorpe
2018-03-05 18:09 ` Logan Gunthorpe
2018-03-05 18:09 ` Logan Gunthorpe
2018-03-06 0:49 ` Oliver
2018-03-06 0:49 ` Oliver
2018-03-06 0:49 ` Oliver
2018-03-06 0:49 ` Oliver
2018-03-06 1:14 ` Logan Gunthorpe
2018-03-06 1:14 ` Logan Gunthorpe
2018-03-06 1:14 ` Logan Gunthorpe
2018-03-06 1:14 ` Logan Gunthorpe
2018-03-06 10:40 ` Oliver
2018-03-06 10:40 ` Oliver
2018-03-06 10:40 ` Oliver
2018-03-06 10:40 ` Oliver
2018-03-05 19:57 ` Sagi Grimberg
2018-03-05 19:57 ` Sagi Grimberg
2018-03-05 19:57 ` Sagi Grimberg
2018-03-05 19:57 ` Sagi Grimberg
2018-03-05 20:10 ` Jason Gunthorpe
2018-03-05 20:10 ` Jason Gunthorpe
2018-03-05 20:10 ` Jason Gunthorpe
2018-03-05 20:10 ` Jason Gunthorpe
2018-03-05 20:16 ` Logan Gunthorpe
2018-03-05 20:16 ` Logan Gunthorpe
2018-03-05 20:16 ` Logan Gunthorpe
2018-03-05 20:42 ` Keith Busch
2018-03-05 20:42 ` Keith Busch
2018-03-05 20:42 ` Keith Busch
2018-03-05 20:42 ` Keith Busch
2018-03-05 20:50 ` Jason Gunthorpe
2018-03-05 20:50 ` Jason Gunthorpe
2018-03-05 20:50 ` Jason Gunthorpe
2018-03-05 20:13 ` Logan Gunthorpe
2018-03-05 20:13 ` Logan Gunthorpe
2018-03-05 20:13 ` Logan Gunthorpe
2018-03-05 20:13 ` Logan Gunthorpe
2018-02-28 23:40 ` [PATCH v2 08/10] nvme-pci: Add support for P2P memory in requests Logan Gunthorpe
2018-02-28 23:40 ` Logan Gunthorpe
2018-02-28 23:40 ` Logan Gunthorpe
2018-02-28 23:40 ` Logan Gunthorpe
2018-03-01 11:07 ` Sagi Grimberg
2018-03-01 11:07 ` Sagi Grimberg
2018-03-01 11:07 ` Sagi Grimberg
2018-03-01 11:07 ` Sagi Grimberg
2018-03-01 15:58 ` Stephen Bates
2018-03-01 15:58 ` Stephen Bates
2018-03-01 15:58 ` Stephen Bates
2018-03-01 15:58 ` Stephen Bates
2018-03-01 15:58 ` Stephen Bates
2018-03-09 5:08 ` Bart Van Assche
2018-03-09 5:08 ` Bart Van Assche
2018-03-09 5:08 ` Bart Van Assche
2018-03-09 5:08 ` Bart Van Assche
2018-03-09 5:08 ` Bart Van Assche
2018-02-28 23:40 ` [PATCH v2 09/10] nvme-pci: Add a quirk for a pseudo CMB Logan Gunthorpe
2018-02-28 23:40 ` Logan Gunthorpe
2018-02-28 23:40 ` Logan Gunthorpe
2018-02-28 23:40 ` Logan Gunthorpe
2018-03-01 11:03 ` Sagi Grimberg
2018-03-01 11:03 ` Sagi Grimberg
2018-03-01 11:03 ` Sagi Grimberg
2018-03-01 11:03 ` Sagi Grimberg
2018-02-28 23:40 ` [PATCH v2 10/10] nvmet: Optionally use PCI P2P memory Logan Gunthorpe
2018-02-28 23:40 ` Logan Gunthorpe
2018-02-28 23:40 ` Logan Gunthorpe
2018-02-28 23:40 ` Logan Gunthorpe
2018-03-01 11:03 ` Sagi Grimberg
2018-03-01 11:03 ` Sagi Grimberg
2018-03-01 11:03 ` Sagi Grimberg
2018-03-01 11:03 ` Sagi Grimberg
2018-03-01 16:15 ` Stephen Bates
2018-03-01 16:15 ` Stephen Bates
2018-03-01 16:15 ` Stephen Bates
2018-03-01 16:15 ` Stephen Bates
2018-03-01 16:15 ` Stephen Bates
2018-03-01 17:40 ` Logan Gunthorpe
2018-03-01 17:40 ` Logan Gunthorpe
2018-03-01 17:40 ` Logan Gunthorpe
2018-03-01 17:40 ` Logan Gunthorpe
2018-03-01 18:35 ` Sagi Grimberg
2018-03-01 18:35 ` Sagi Grimberg
2018-03-01 18:35 ` Sagi Grimberg
2018-03-01 18:35 ` Sagi Grimberg
2018-03-01 18:42 ` Jason Gunthorpe
2018-03-01 18:42 ` Jason Gunthorpe
2018-03-01 19:01 ` Stephen Bates
2018-03-01 19:01 ` Stephen Bates
2018-03-01 19:01 ` Stephen Bates
2018-03-01 19:01 ` Stephen Bates
2018-03-01 19:01 ` Stephen Bates
2018-03-01 19:27 ` Logan Gunthorpe
2018-03-01 19:27 ` Logan Gunthorpe
2018-03-01 19:27 ` Logan Gunthorpe
2018-03-01 19:27 ` Logan Gunthorpe
2018-03-01 22:45 ` Jason Gunthorpe
2018-03-01 22:45 ` Jason Gunthorpe
2018-03-01 22:56 ` Logan Gunthorpe
2018-03-01 22:56 ` Logan Gunthorpe
2018-03-01 22:56 ` Logan Gunthorpe
2018-03-01 22:56 ` Logan Gunthorpe
2018-03-01 23:00 ` Stephen Bates
2018-03-01 23:00 ` Stephen Bates
2018-03-01 23:00 ` Stephen Bates
2018-03-01 23:00 ` Stephen Bates
2018-03-01 23:00 ` Stephen Bates
2018-03-01 23:20 ` Jason Gunthorpe
2018-03-01 23:20 ` Jason Gunthorpe
2018-03-01 23:20 ` Jason Gunthorpe
2018-03-01 23:29 ` Logan Gunthorpe
2018-03-01 23:29 ` Logan Gunthorpe
2018-03-01 23:29 ` Logan Gunthorpe
2018-03-01 23:29 ` Logan Gunthorpe
2018-03-01 23:32 ` Stephen Bates
2018-03-01 23:32 ` Stephen Bates
2018-03-01 23:32 ` Stephen Bates
2018-03-01 23:32 ` Stephen Bates
2018-03-01 23:32 ` Stephen Bates
2018-03-01 23:49 ` Keith Busch
2018-03-01 23:49 ` Keith Busch
2018-03-01 23:49 ` Keith Busch
2018-03-01 23:49 ` Keith Busch
2018-03-01 23:52 ` Logan Gunthorpe
2018-03-01 23:52 ` Logan Gunthorpe
2018-03-01 23:52 ` Logan Gunthorpe
2018-03-01 23:52 ` Logan Gunthorpe
2018-03-01 23:53 ` Stephen Bates
2018-03-01 23:53 ` Stephen Bates
2018-03-01 23:53 ` Stephen Bates
2018-03-01 23:53 ` Stephen Bates
2018-03-01 23:53 ` Stephen Bates
2018-03-02 15:53 ` Christoph Hellwig
2018-03-02 15:53 ` Christoph Hellwig
2018-03-02 15:53 ` Christoph Hellwig
2018-03-02 15:53 ` Christoph Hellwig
2018-03-02 20:51 ` Stephen Bates
2018-03-02 20:51 ` Stephen Bates
2018-03-02 20:51 ` Stephen Bates
2018-03-02 20:51 ` Stephen Bates
2018-03-01 23:57 ` Stephen Bates
2018-03-01 23:57 ` Stephen Bates
2018-03-01 23:57 ` Stephen Bates
2018-03-01 23:57 ` Stephen Bates
2018-03-01 23:57 ` Stephen Bates
2018-03-02 0:03 ` Logan Gunthorpe
2018-03-02 0:03 ` Logan Gunthorpe
2018-03-02 0:03 ` Logan Gunthorpe
2018-03-02 0:03 ` Logan Gunthorpe
2018-03-02 16:18 ` Jason Gunthorpe
2018-03-02 16:18 ` Jason Gunthorpe
2018-03-02 16:18 ` Jason Gunthorpe
2018-03-02 17:10 ` Logan Gunthorpe
2018-03-02 17:10 ` Logan Gunthorpe
2018-03-02 17:10 ` Logan Gunthorpe
2018-03-02 17:10 ` Logan Gunthorpe
2018-03-01 19:10 ` Logan Gunthorpe
2018-03-01 19:10 ` Logan Gunthorpe
2018-03-01 19:10 ` Logan Gunthorpe
2018-03-01 19:10 ` Logan Gunthorpe
2018-03-01 3:54 ` [PATCH v2 00/10] Copy Offload in NVMe Fabrics with P2P PCI Memory Benjamin Herrenschmidt
2018-03-01 3:54 ` Benjamin Herrenschmidt
2018-03-01 3:54 ` Benjamin Herrenschmidt
2018-03-01 3:54 ` Benjamin Herrenschmidt
2018-03-01 3:56 ` Benjamin Herrenschmidt
2018-03-01 3:56 ` Benjamin Herrenschmidt
2018-03-01 3:56 ` Benjamin Herrenschmidt
2018-03-01 3:56 ` Benjamin Herrenschmidt
2018-03-01 18:04 ` Logan Gunthorpe
2018-03-01 18:04 ` Logan Gunthorpe
2018-03-01 18:04 ` Logan Gunthorpe
2018-03-01 18:04 ` Logan Gunthorpe
2018-03-01 20:29 ` Benjamin Herrenschmidt
2018-03-01 20:29 ` Benjamin Herrenschmidt
2018-03-01 20:29 ` Benjamin Herrenschmidt
2018-03-01 20:29 ` Benjamin Herrenschmidt
2018-03-01 20:55 ` Jerome Glisse
2018-03-01 20:55 ` Jerome Glisse
2018-03-01 20:55 ` Jerome Glisse
2018-03-01 20:55 ` Jerome Glisse
2018-03-01 20:55 ` Jerome Glisse
2018-03-01 21:03 ` Logan Gunthorpe
2018-03-01 21:03 ` Logan Gunthorpe
2018-03-01 21:03 ` Logan Gunthorpe
2018-03-01 21:03 ` Logan Gunthorpe
2018-03-01 21:10 ` Jerome Glisse
2018-03-01 21:10 ` Jerome Glisse
2018-03-01 21:10 ` Jerome Glisse
2018-03-01 21:10 ` Jerome Glisse
2018-03-01 21:10 ` Jerome Glisse
2018-03-01 21:15 ` Logan Gunthorpe
2018-03-01 21:15 ` Logan Gunthorpe
2018-03-01 21:15 ` Logan Gunthorpe
2018-03-01 21:15 ` Logan Gunthorpe
2018-03-01 21:25 ` Jerome Glisse
2018-03-01 21:25 ` Jerome Glisse
2018-03-01 21:25 ` Jerome Glisse
2018-03-01 21:25 ` Jerome Glisse
2018-03-01 21:25 ` Jerome Glisse
2018-03-01 21:37 ` Stephen Bates
2018-03-01 21:37 ` Stephen Bates
2018-03-01 21:37 ` Stephen Bates
2018-03-01 21:37 ` Stephen Bates
2018-03-01 21:37 ` Stephen Bates
2018-03-02 21:38 ` Stephen Bates
2018-03-02 21:38 ` Stephen Bates
2018-03-02 21:38 ` Stephen Bates
2018-03-02 21:38 ` Stephen Bates
2018-03-02 21:38 ` Stephen Bates
2018-03-02 22:09 ` Jerome Glisse
2018-03-02 22:09 ` Jerome Glisse
2018-03-02 22:09 ` Jerome Glisse
2018-03-02 22:09 ` Jerome Glisse
2018-03-02 22:09 ` Jerome Glisse
2018-03-05 20:36 ` Stephen Bates
2018-03-05 20:36 ` Stephen Bates
2018-03-05 20:36 ` Stephen Bates
2018-03-05 20:36 ` Stephen Bates
2018-03-05 20:36 ` Stephen Bates
2018-03-01 20:55 ` Logan Gunthorpe
2018-03-01 20:55 ` Logan Gunthorpe
2018-03-01 20:55 ` Logan Gunthorpe
2018-03-01 20:55 ` Logan Gunthorpe
2018-03-01 18:09 ` Stephen Bates
2018-03-01 18:09 ` Stephen Bates
2018-03-01 18:09 ` Stephen Bates
2018-03-01 18:09 ` Stephen Bates
2018-03-01 18:09 ` Stephen Bates
2018-03-01 20:32 ` Benjamin Herrenschmidt
2018-03-01 20:32 ` Benjamin Herrenschmidt
2018-03-01 20:32 ` Benjamin Herrenschmidt
2018-03-01 20:32 ` Benjamin Herrenschmidt
2018-03-01 19:21 ` Dan Williams
2018-03-01 19:21 ` Dan Williams
2018-03-01 19:21 ` Dan Williams
2018-03-01 19:21 ` Dan Williams
2018-03-01 19:30 ` Logan Gunthorpe
2018-03-01 19:30 ` Logan Gunthorpe
2018-03-01 19:30 ` Logan Gunthorpe
2018-03-01 19:30 ` Logan Gunthorpe
2018-03-01 20:34 ` Benjamin Herrenschmidt
2018-03-01 20:34 ` Benjamin Herrenschmidt
2018-03-01 20:34 ` Benjamin Herrenschmidt
2018-03-01 20:34 ` Benjamin Herrenschmidt
2018-03-01 20:40 ` Benjamin Herrenschmidt
2018-03-01 20:40 ` Benjamin Herrenschmidt
2018-03-01 20:40 ` Benjamin Herrenschmidt
2018-03-01 20:40 ` Benjamin Herrenschmidt
2018-03-01 20:53 ` Jason Gunthorpe
2018-03-01 20:53 ` Jason Gunthorpe
2018-03-01 20:57 ` Logan Gunthorpe
2018-03-01 20:57 ` Logan Gunthorpe
2018-03-01 20:57 ` Logan Gunthorpe
2018-03-01 20:57 ` Logan Gunthorpe
2018-03-01 22:06 ` Benjamin Herrenschmidt
2018-03-01 22:06 ` Benjamin Herrenschmidt
2018-03-01 22:06 ` Benjamin Herrenschmidt
2018-03-01 22:06 ` Benjamin Herrenschmidt
2018-03-01 22:31 ` Linus Torvalds
2018-03-01 22:31 ` Linus Torvalds
2018-03-01 22:31 ` Linus Torvalds
2018-03-01 22:31 ` Linus Torvalds
2018-03-01 22:34 ` Benjamin Herrenschmidt
2018-03-01 22:34 ` Benjamin Herrenschmidt
2018-03-01 22:34 ` Benjamin Herrenschmidt
2018-03-01 22:34 ` Benjamin Herrenschmidt
2018-03-02 16:22 ` Kani, Toshi [this message]
2018-03-02 16:22 ` Kani, Toshi
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2018-03-02 16:57 ` Linus Torvalds
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2018-03-02 17:34 ` Linus Torvalds
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2018-03-02 17:38 ` Kani, Toshi
2018-03-02 17:38 ` Kani, Toshi
2018-03-02 17:38 ` Kani, Toshi
2018-03-02 17:38 ` Kani, Toshi
2018-03-02 17:38 ` Kani, Toshi
2018-03-01 21:37 ` Dan Williams
2018-03-01 21:37 ` Dan Williams
2018-03-01 21:37 ` Dan Williams
2018-03-01 21:37 ` Dan Williams
2018-03-01 21:45 ` Logan Gunthorpe
2018-03-01 21:45 ` Logan Gunthorpe
2018-03-01 21:45 ` Logan Gunthorpe
2018-03-01 21:57 ` Logan Gunthorpe
2018-03-01 21:57 ` Logan Gunthorpe
2018-03-01 21:57 ` Logan Gunthorpe
2018-03-01 21:57 ` Logan Gunthorpe
2018-03-01 23:00 ` Benjamin Herrenschmidt
2018-03-01 23:00 ` Benjamin Herrenschmidt
2018-03-01 23:00 ` Benjamin Herrenschmidt
2018-03-01 23:00 ` Benjamin Herrenschmidt
2018-03-01 23:19 ` Logan Gunthorpe
2018-03-01 23:19 ` Logan Gunthorpe
2018-03-01 23:19 ` Logan Gunthorpe
2018-03-01 23:19 ` Logan Gunthorpe
2018-03-01 23:25 ` Benjamin Herrenschmidt
2018-03-01 23:25 ` Benjamin Herrenschmidt
2018-03-01 23:25 ` Benjamin Herrenschmidt
2018-03-01 23:25 ` Benjamin Herrenschmidt
2018-03-02 21:44 ` Benjamin Herrenschmidt
2018-03-02 21:44 ` Benjamin Herrenschmidt
2018-03-02 21:44 ` Benjamin Herrenschmidt
2018-03-02 21:44 ` Benjamin Herrenschmidt
2018-03-02 22:24 ` Logan Gunthorpe
2018-03-02 22:24 ` Logan Gunthorpe
2018-03-02 22:24 ` Logan Gunthorpe
2018-03-02 22:24 ` Logan Gunthorpe
2018-03-01 23:26 ` Benjamin Herrenschmidt
2018-03-01 23:26 ` Benjamin Herrenschmidt
2018-03-01 23:26 ` Benjamin Herrenschmidt
2018-03-01 23:26 ` Benjamin Herrenschmidt
2018-03-01 23:54 ` Logan Gunthorpe
2018-03-01 23:54 ` Logan Gunthorpe
2018-03-01 23:54 ` Logan Gunthorpe
2018-03-01 23:54 ` Logan Gunthorpe
2018-03-01 21:03 ` Benjamin Herrenschmidt
2018-03-01 21:03 ` Benjamin Herrenschmidt
2018-03-01 21:03 ` Benjamin Herrenschmidt
2018-03-01 21:03 ` Benjamin Herrenschmidt
2018-03-01 21:11 ` Logan Gunthorpe
2018-03-01 21:11 ` Logan Gunthorpe
2018-03-01 21:11 ` Logan Gunthorpe
2018-03-01 21:11 ` Logan Gunthorpe
2018-03-01 21:18 ` Jerome Glisse
2018-03-01 21:18 ` Jerome Glisse
2018-03-01 21:18 ` Jerome Glisse
2018-03-01 21:18 ` Jerome Glisse
2018-03-01 21:18 ` Jerome Glisse
2018-03-01 21:22 ` Logan Gunthorpe
2018-03-01 21:22 ` Logan Gunthorpe
2018-03-01 21:22 ` Logan Gunthorpe
2018-03-01 21:22 ` Logan Gunthorpe
2018-03-01 10:31 ` Sagi Grimberg
2018-03-01 10:31 ` Sagi Grimberg
2018-03-01 10:31 ` Sagi Grimberg
2018-03-01 10:31 ` Sagi Grimberg
2018-03-01 19:33 ` Logan Gunthorpe
2018-03-01 19:33 ` Logan Gunthorpe
2018-03-01 19:33 ` Logan Gunthorpe
2018-03-01 19:33 ` Logan Gunthorpe
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