From: "Kani, Toshi" <toshi.kani@hpe.com>
To: "torvalds@linux-foundation.org" <torvalds@linux-foundation.org>
Cc: "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"alex.williamson@redhat.com" <alex.williamson@redhat.com>,
"linux-block@vger.kernel.org" <linux-block@vger.kernel.org>,
"linux-rdma@vger.kernel.org" <linux-rdma@vger.kernel.org>,
"bhelgaas@google.com" <bhelgaas@google.com>,
"hch@lst.de" <hch@lst.de>, "axboe@kernel.dk" <axboe@kernel.dk>,
"linux-nvdimm@lists.01.org" <linux-nvdimm@lists.01.org>,
"jglisse@redhat.com" <jglisse@redhat.com>,
"linux-nvme@lists.infradead.org" <linux-nvme@lists.infradead.org>,
"maxg@mellanox.com" <maxg@mellanox.com>,
"linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
"keith.busch@intel.com" <keith.busch@intel.com>,
"benh@kernel.crashing.org" <benh@kernel.crashing.org>,
"jgg@ziepe.ca" <jgg@ziepe.ca>,
"oliveroh@au1.ibm.com" <oliveroh@au1.ibm.com>
Subject: Re: [PATCH v2 00/10] Copy Offload in NVMe Fabrics with P2P PCI Memory
Date: Fri, 2 Mar 2018 17:38:58 +0000 [thread overview]
Message-ID: <1520015040.2693.38.camel@hpe.com> (raw)
In-Reply-To: <CA+55aFztf2D4NwEkRxnJkD6kK62CWKxmERbALMGoMgFEGLEJZA@mail.gmail.com>
T24gRnJpLCAyMDE4LTAzLTAyIGF0IDA4OjU3IC0wODAwLCBMaW51cyBUb3J2YWxkcyB3cm90ZToN
Cj4gT24gRnJpLCBNYXIgMiwgMjAxOCBhdCA4OjIyIEFNLCBLYW5pLCBUb3NoaSA8dG9zaGkua2Fu
aUBocGUuY29tPiB3cm90ZToNCj4gPiANCj4gPiBGV0lXLCB0aGlzIHRoaW5nIGlzIGNhbGxlZCBN
VFJScyBvbiB4ODYsIHdoaWNoIGFyZSBpbml0aWFsaXplZCBieSBCSU9TLg0KPiANCj4gTm8uDQo+
IA0KPiBPciByYXRoZXIsIHRoYXQncyBzaW1wbHkganVzdCBhbm90aGVyIChzbWFsbCkgcGFydCBv
ZiBpdCBhbGwgLSBhbmQgYW4NCj4gYXJjaGl0ZWN0ZWQgYW5kIGRvY3VtZW50ZWQgb25lIGF0IHRo
YXQuDQo+IA0KPiBMaWtlIHRoZSBwYWdlIHRhYmxlIGNhY2hpbmcgZW50cmllcywgdGhlIG1lbW9y
eSB0eXBlIHJhbmdlIHJlZ2lzdGVycw0KPiBhcmUgcmVhbGx5IGp1c3QgInNlY29uZGFyeSBpbmZv
cm1hdGlvbiIuIFRoZXkgZG9uJ3QgYWN0dWFsbHkgc2VsZWN0DQo+IGJldHdlZW4gUENJZSBhbmQg
UkFNLCB0aGV5IGp1c3QgYWZmZWN0IHRoZSBiZWhhdmlvciBvbiB0b3Agb2YgdGhhdC4NCj4gDQo+
IFRoZSByZWFsbHkgbml0dHktZ3JpdHR5IHN0dWZmIGlzIG5vdCBhcmNoaXRlY3RlZCwgYW5kIGdl
bmVyYWxseSBub3QNCj4gZG9jdW1lbnRlZCBvdXRzaWRlIChwb3NzaWJseSkgdGhlIEJJT1Mgd3Jp
dGVyJ3MgZ3VpZGUgdGhhdCBpcyBub3QgbWFkZQ0KPiBwdWJsaWMuDQo+IA0KPiBUaG9zZSBtYWdp
Y2FsIHJlZ2lzdGVycyBjb250YWluIGRldGFpbHMgbGlrZSBob3cgdGhlIERSQU0gaXMNCj4gaW50
ZXJsZWF2ZWQgKGlmIGl0IGlzKSwgd2hhdCB0aGUgdGltaW5ncyBhcmUsIHdoZXJlIHdoaWNoIG1l
bW9yeQ0KPiBjb250cm9sbGVyIGhhbmRsZXMgd2hpY2ggbWVtb3J5IHJhbmdlLCBhbmQgd2hhdCBh
cmUgZ29lcyB0byBQQ0llIGV0Yy4NCj4gDQo+IEJhc2ljYWxseSBhbGwgdGhlIGFjdHVhbCAqc3Rl
ZXJpbmcqIGluZm9ybWF0aW9uIGlzIHZlcnkgbXVjaCBoaWRkZW4NCj4gYXdheSBmcm9tIHRoZSBr
ZXJuZWwgKGFuZCBvZnRlbiBmcm9tIHRoZSBCSU9TIHRvbykuIFRoZSBwYXJ0cyB3ZSBzZWUNCj4g
YXQgYSBoaWdoZXIgbGV2ZWwgYXJlIGp1c3QgdHVuaW5nIGFuZCB0d2Vha3MuDQo+IA0KPiBOb3Rl
OiB0aGUgZGV0YWlscyBkaWZmZXIgX2Vub3Jtb3VzbHlfIGJldHdlZW4gZGlmZmVyZW50IGNoaXBz
LiBUaGUNCj4gc2V0dXAgY2FuIGJlIHZlcnkgZGlmZmVyZW50LCB3aXRoIHRoaW5ncyBsaWtlIEtu
aWdodHMgTGFuZGluZyBoYXZpbmcNCj4gdGhlIGV4dGVybmFsIGNhY2hlIHRoYXQgY2FuIGFsc28g
YWN0IGFzIGxvY2FsIG1lbW9yeSB0aGF0IGlzbid0IGENCj4gY2FjaGUgYnV0IG1hcHMgYXQgYSBk
aWZmZXJlbnQgcGh5c2ljYWwgYWRkcmVzcyBpbnN0ZWFkIGV0Yy4gVGhhdCdzIHRoZQ0KPiBraW5k
IG9mIHN0ZWVyaW5nIEknbSB0YWxraW5nIGFib3V0IC0gYXQgYSBsb3cgbGV2ZWwgaG93IHBoeXNp
Y2FsDQo+IGFkZHJlc3NlcyBnZXQgbWFwcGVkIHRvIGRpZmZlcmVudCBjYWNoZSBwYXJ0aXRpb25z
LCBtZW1vcnkNCj4gY29udHJvbGxlcnMsIG9yIHRvIHRoZSBJTyBzeXN0ZW0gZXRjLg0KDQpSaWdo
dCwgTVJDIGNvZGUgaXMgbm90IGRvY3VtZW50ZWQgcHVibGljbHksIGFuZCBpdCBpcyB2ZXJ5IG11
Y2ggQ1BVDQpkZXBlbmRlbnQuICBJdCBwcm9ncmFtcyBhZGRyZXNzIGRlY29kZXJzIGFuZCBtYXBz
IERSQU1zIHRvIHBoeXNpY2FsDQphZGRyZXNzIGFzIHlvdSBkZXNjcmliZWQuICBNVFJScyBoYXZl
IG5vdGhpbmcgdG8gZG8gd2l0aCB0aGlzIG1lbW9yeQ0KY29udHJvbGxlciBzZXR0aW5nLiAgVGhh
dCBzYWlkLCBNVFJScyBzcGVjaWZ5IENQVSdzIG1lbW9yeSBhY2Nlc3MgdHlwZSwNCnN1Y2ggYXMg
VUMgYW5kIFdCLg0KDQpUaGFua3MsDQotVG9zaGkNCg==
WARNING: multiple messages have this Message-ID (diff)
From: "Kani, Toshi" <toshi.kani@hpe.com>
To: "torvalds@linux-foundation.org" <torvalds@linux-foundation.org>
Cc: "axboe@kernel.dk" <axboe@kernel.dk>,
"keith.busch@intel.com" <keith.busch@intel.com>,
"oliveroh@au1.ibm.com" <oliveroh@au1.ibm.com>,
"linux-nvdimm@lists.01.org" <linux-nvdimm@lists.01.org>,
"linux-rdma@vger.kernel.org" <linux-rdma@vger.kernel.org>,
"linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"linux-nvme@lists.infradead.org" <linux-nvme@lists.infradead.org>,
"linux-block@vger.kernel.org" <linux-block@vger.kernel.org>,
"jgg@ziepe.ca" <jgg@ziepe.ca>,
"alex.williamson@redhat.com" <alex.williamson@redhat.com>,
"jglisse@redhat.com" <jglisse@redhat.com>,
"benh@kernel.crashing.org" <benh@kernel.crashing.org>,
"bhelgaas@google.com" <bhelgaas@google.com>,
"maxg@mellanox.com" <maxg@mellanox.com>,
"hch@lst.de" <hch@lst.de>
Subject: Re: [PATCH v2 00/10] Copy Offload in NVMe Fabrics with P2P PCI Memory
Date: Fri, 2 Mar 2018 17:38:58 +0000 [thread overview]
Message-ID: <1520015040.2693.38.camel@hpe.com> (raw)
In-Reply-To: <CA+55aFztf2D4NwEkRxnJkD6kK62CWKxmERbALMGoMgFEGLEJZA@mail.gmail.com>
On Fri, 2018-03-02 at 08:57 -0800, Linus Torvalds wrote:
> On Fri, Mar 2, 2018 at 8:22 AM, Kani, Toshi <toshi.kani@hpe.com> wrote:
> >
> > FWIW, this thing is called MTRRs on x86, which are initialized by BIOS.
>
> No.
>
> Or rather, that's simply just another (small) part of it all - and an
> architected and documented one at that.
>
> Like the page table caching entries, the memory type range registers
> are really just "secondary information". They don't actually select
> between PCIe and RAM, they just affect the behavior on top of that.
>
> The really nitty-gritty stuff is not architected, and generally not
> documented outside (possibly) the BIOS writer's guide that is not made
> public.
>
> Those magical registers contain details like how the DRAM is
> interleaved (if it is), what the timings are, where which memory
> controller handles which memory range, and what are goes to PCIe etc.
>
> Basically all the actual *steering* information is very much hidden
> away from the kernel (and often from the BIOS too). The parts we see
> at a higher level are just tuning and tweaks.
>
> Note: the details differ _enormously_ between different chips. The
> setup can be very different, with things like Knights Landing having
> the external cache that can also act as local memory that isn't a
> cache but maps at a different physical address instead etc. That's the
> kind of steering I'm talking about - at a low level how physical
> addresses get mapped to different cache partitions, memory
> controllers, or to the IO system etc.
Right, MRC code is not documented publicly, and it is very much CPU
dependent. It programs address decoders and maps DRAMs to physical
address as you described. MTRRs have nothing to do with this memory
controller setting. That said, MTRRs specify CPU's memory access type,
such as UC and WB.
Thanks,
-Toshi
_______________________________________________
Linux-nvdimm mailing list
Linux-nvdimm@lists.01.org
https://lists.01.org/mailman/listinfo/linux-nvdimm
WARNING: multiple messages have this Message-ID (diff)
From: toshi.kani@hpe.com (Kani, Toshi)
Subject: [PATCH v2 00/10] Copy Offload in NVMe Fabrics with P2P PCI Memory
Date: Fri, 2 Mar 2018 17:38:58 +0000 [thread overview]
Message-ID: <1520015040.2693.38.camel@hpe.com> (raw)
In-Reply-To: <CA+55aFztf2D4NwEkRxnJkD6kK62CWKxmERbALMGoMgFEGLEJZA@mail.gmail.com>
On Fri, 2018-03-02@08:57 -0800, Linus Torvalds wrote:
> On Fri, Mar 2, 2018@8:22 AM, Kani, Toshi <toshi.kani@hpe.com> wrote:
> >
> > FWIW, this thing is called MTRRs on x86, which are initialized by BIOS.
>
> No.
>
> Or rather, that's simply just another (small) part of it all - and an
> architected and documented one at that.
>
> Like the page table caching entries, the memory type range registers
> are really just "secondary information". They don't actually select
> between PCIe and RAM, they just affect the behavior on top of that.
>
> The really nitty-gritty stuff is not architected, and generally not
> documented outside (possibly) the BIOS writer's guide that is not made
> public.
>
> Those magical registers contain details like how the DRAM is
> interleaved (if it is), what the timings are, where which memory
> controller handles which memory range, and what are goes to PCIe etc.
>
> Basically all the actual *steering* information is very much hidden
> away from the kernel (and often from the BIOS too). The parts we see
> at a higher level are just tuning and tweaks.
>
> Note: the details differ _enormously_ between different chips. The
> setup can be very different, with things like Knights Landing having
> the external cache that can also act as local memory that isn't a
> cache but maps at a different physical address instead etc. That's the
> kind of steering I'm talking about - at a low level how physical
> addresses get mapped to different cache partitions, memory
> controllers, or to the IO system etc.
Right, MRC code is not documented publicly, and it is very much CPU
dependent. It programs address decoders and maps DRAMs to physical
address as you described. MTRRs have nothing to do with this memory
controller setting. That said, MTRRs specify CPU's memory access type,
such as UC and WB.
Thanks,
-Toshi
WARNING: multiple messages have this Message-ID (diff)
From: "Kani, Toshi" <toshi.kani-ZPxbGqLxI0U@public.gmane.org>
To: "torvalds-de/tnXTf+JLsfHDXvbKv3WD2FQJk+8+b@public.gmane.org"
<torvalds-de/tnXTf+JLsfHDXvbKv3WD2FQJk+8+b@public.gmane.org>
Cc: "axboe-tSWWG44O7X1aa/9Udqfwiw@public.gmane.org"
<axboe-tSWWG44O7X1aa/9Udqfwiw@public.gmane.org>,
"keith.busch-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org"
<keith.busch-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>,
"oliveroh-8fk3Idey6ehBDgjK7y7TUQ@public.gmane.org"
<oliveroh-8fk3Idey6ehBDgjK7y7TUQ@public.gmane.org>,
"linux-nvdimm-hn68Rpc1hR1g9hUCZPvPmw@public.gmane.org"
<linux-nvdimm-hn68Rpc1hR1g9hUCZPvPmw@public.gmane.org>,
"linux-rdma-u79uwXL29TY76Z2rM5mHXA@public.gmane.org"
<linux-rdma-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>,
"linux-pci-u79uwXL29TY76Z2rM5mHXA@public.gmane.org"
<linux-pci-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>,
"linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org"
<linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>,
"linux-nvme-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org"
<linux-nvme-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org>,
"linux-block-u79uwXL29TY76Z2rM5mHXA@public.gmane.org"
<linux-block-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>,
"jgg-uk2M96/98Pc@public.gmane.org"
<jgg-uk2M96/98Pc@public.gmane.org>,
"alex.williamson-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org"
<alex.williamson-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>,
"jglisse-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org"
<jglisse-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>,
"benh-XVmvHMARGAS8U2dJNN8I7kB+6BGkLq7r@public.gmane.org"
<benh-XVmvHMARGAS8U2dJNN8I7kB+6BGkLq7r@public.gmane.org>,
"bhelgaas-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org"
<bhelgaas-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org>,
"maxg-VPRAkNaXOzVWk0Htik3J/w@public.gmane.org"
<maxg-VPRAkNaXOzVWk0Htik3J/w@public.gmane.org>,
"hch-jcswGhMUV9g@public.gmane.org"
<hch-jcswGhMUV9g@public.gmane.org>
Subject: Re: [PATCH v2 00/10] Copy Offload in NVMe Fabrics with P2P PCI Memory
Date: Fri, 2 Mar 2018 17:38:58 +0000 [thread overview]
Message-ID: <1520015040.2693.38.camel@hpe.com> (raw)
In-Reply-To: <CA+55aFztf2D4NwEkRxnJkD6kK62CWKxmERbALMGoMgFEGLEJZA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
On Fri, 2018-03-02 at 08:57 -0800, Linus Torvalds wrote:
> On Fri, Mar 2, 2018 at 8:22 AM, Kani, Toshi <toshi.kani-ZPxbGqLxI0U@public.gmane.org> wrote:
> >
> > FWIW, this thing is called MTRRs on x86, which are initialized by BIOS.
>
> No.
>
> Or rather, that's simply just another (small) part of it all - and an
> architected and documented one at that.
>
> Like the page table caching entries, the memory type range registers
> are really just "secondary information". They don't actually select
> between PCIe and RAM, they just affect the behavior on top of that.
>
> The really nitty-gritty stuff is not architected, and generally not
> documented outside (possibly) the BIOS writer's guide that is not made
> public.
>
> Those magical registers contain details like how the DRAM is
> interleaved (if it is), what the timings are, where which memory
> controller handles which memory range, and what are goes to PCIe etc.
>
> Basically all the actual *steering* information is very much hidden
> away from the kernel (and often from the BIOS too). The parts we see
> at a higher level are just tuning and tweaks.
>
> Note: the details differ _enormously_ between different chips. The
> setup can be very different, with things like Knights Landing having
> the external cache that can also act as local memory that isn't a
> cache but maps at a different physical address instead etc. That's the
> kind of steering I'm talking about - at a low level how physical
> addresses get mapped to different cache partitions, memory
> controllers, or to the IO system etc.
Right, MRC code is not documented publicly, and it is very much CPU
dependent. It programs address decoders and maps DRAMs to physical
address as you described. MTRRs have nothing to do with this memory
controller setting. That said, MTRRs specify CPU's memory access type,
such as UC and WB.
Thanks,
-Toshi
WARNING: multiple messages have this Message-ID (diff)
From: "Kani, Toshi" <toshi.kani@hpe.com>
To: "torvalds@linux-foundation.org" <torvalds@linux-foundation.org>
Cc: "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"alex.williamson@redhat.com" <alex.williamson@redhat.com>,
"linux-block@vger.kernel.org" <linux-block@vger.kernel.org>,
"linux-rdma@vger.kernel.org" <linux-rdma@vger.kernel.org>,
"bhelgaas@google.com" <bhelgaas@google.com>,
"hch@lst.de" <hch@lst.de>, "axboe@kernel.dk" <axboe@kernel.dk>,
"linux-nvdimm@lists.01.org" <linux-nvdimm@lists.01.org>,
"jglisse@redhat.com" <jglisse@redhat.com>,
"linux-nvme@lists.infradead.org" <linux-nvme@lists.infradead.org>,
"maxg@mellanox.com" <maxg@mellanox.com>,
"linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
"keith.busch@intel.com" <keith.busch@intel.com>,
"benh@kernel.crashing.org" <benh@kernel.crashing.org>,
"jgg@ziepe.ca" <jgg@ziepe.ca>,
"oliveroh@au1.ibm.com" <oliveroh@au1.ibm.com>
Subject: Re: [PATCH v2 00/10] Copy Offload in NVMe Fabrics with P2P PCI Memory
Date: Fri, 2 Mar 2018 17:38:58 +0000 [thread overview]
Message-ID: <1520015040.2693.38.camel@hpe.com> (raw)
In-Reply-To: <CA+55aFztf2D4NwEkRxnJkD6kK62CWKxmERbALMGoMgFEGLEJZA@mail.gmail.com>
On Fri, 2018-03-02 at 08:57 -0800, Linus Torvalds wrote:
> On Fri, Mar 2, 2018 at 8:22 AM, Kani, Toshi <toshi.kani@hpe.com> wrote:
> >
> > FWIW, this thing is called MTRRs on x86, which are initialized by BIOS.
>
> No.
>
> Or rather, that's simply just another (small) part of it all - and an
> architected and documented one at that.
>
> Like the page table caching entries, the memory type range registers
> are really just "secondary information". They don't actually select
> between PCIe and RAM, they just affect the behavior on top of that.
>
> The really nitty-gritty stuff is not architected, and generally not
> documented outside (possibly) the BIOS writer's guide that is not made
> public.
>
> Those magical registers contain details like how the DRAM is
> interleaved (if it is), what the timings are, where which memory
> controller handles which memory range, and what are goes to PCIe etc.
>
> Basically all the actual *steering* information is very much hidden
> away from the kernel (and often from the BIOS too). The parts we see
> at a higher level are just tuning and tweaks.
>
> Note: the details differ _enormously_ between different chips. The
> setup can be very different, with things like Knights Landing having
> the external cache that can also act as local memory that isn't a
> cache but maps at a different physical address instead etc. That's the
> kind of steering I'm talking about - at a low level how physical
> addresses get mapped to different cache partitions, memory
> controllers, or to the IO system etc.
Right, MRC code is not documented publicly, and it is very much CPU
dependent. It programs address decoders and maps DRAMs to physical
address as you described. MTRRs have nothing to do with this memory
controller setting. That said, MTRRs specify CPU's memory access type,
such as UC and WB.
Thanks,
-Toshi
next prev parent reply other threads:[~2018-03-02 17:38 UTC|newest]
Thread overview: 504+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-02-28 23:39 [PATCH v2 00/10] Copy Offload in NVMe Fabrics with P2P PCI Memory Logan Gunthorpe
2018-02-28 23:39 ` Logan Gunthorpe
2018-02-28 23:39 ` Logan Gunthorpe
2018-02-28 23:39 ` Logan Gunthorpe
2018-02-28 23:39 ` [PATCH v2 01/10] PCI/P2PDMA: Support peer to peer memory Logan Gunthorpe
2018-02-28 23:39 ` Logan Gunthorpe
2018-02-28 23:39 ` Logan Gunthorpe
2018-03-01 17:37 ` Bjorn Helgaas
2018-03-01 17:37 ` Bjorn Helgaas
2018-03-01 17:37 ` Bjorn Helgaas
2018-03-01 17:37 ` Bjorn Helgaas
2018-03-01 18:55 ` Logan Gunthorpe
2018-03-01 18:55 ` Logan Gunthorpe
2018-03-01 18:55 ` Logan Gunthorpe
2018-03-01 18:55 ` Logan Gunthorpe
2018-03-01 23:00 ` Bjorn Helgaas
2018-03-01 23:00 ` Bjorn Helgaas
2018-03-01 23:00 ` Bjorn Helgaas
2018-03-01 23:00 ` Bjorn Helgaas
2018-03-01 23:06 ` Logan Gunthorpe
2018-03-01 23:06 ` Logan Gunthorpe
2018-03-01 23:06 ` Logan Gunthorpe
2018-03-01 23:06 ` Logan Gunthorpe
2018-03-01 23:14 ` Stephen Bates
2018-03-01 23:14 ` Stephen Bates
2018-03-01 23:14 ` Stephen Bates
2018-03-01 23:14 ` Stephen Bates
2018-03-01 23:14 ` Stephen Bates
2018-03-01 23:45 ` Bjorn Helgaas
2018-03-01 23:45 ` Bjorn Helgaas
2018-03-01 23:45 ` Bjorn Helgaas
2018-03-01 23:45 ` Bjorn Helgaas
2018-02-28 23:39 ` [PATCH v2 02/10] PCI/P2PDMA: Add sysfs group to display p2pmem stats Logan Gunthorpe
2018-02-28 23:39 ` Logan Gunthorpe
2018-02-28 23:39 ` Logan Gunthorpe
2018-02-28 23:39 ` Logan Gunthorpe
2018-03-01 17:44 ` Bjorn Helgaas
2018-03-01 17:44 ` Bjorn Helgaas
2018-03-01 17:44 ` Bjorn Helgaas
2018-03-01 17:44 ` Bjorn Helgaas
2018-03-02 0:15 ` Logan Gunthorpe
2018-03-02 0:15 ` Logan Gunthorpe
2018-03-02 0:15 ` Logan Gunthorpe
2018-03-02 0:15 ` Logan Gunthorpe
2018-03-02 0:36 ` Dan Williams
2018-03-02 0:36 ` Dan Williams
2018-03-02 0:36 ` Dan Williams
2018-03-02 0:36 ` Dan Williams
2018-03-02 0:37 ` Logan Gunthorpe
2018-03-02 0:37 ` Logan Gunthorpe
2018-03-02 0:37 ` Logan Gunthorpe
2018-03-02 0:37 ` Logan Gunthorpe
2018-02-28 23:39 ` [PATCH v2 03/10] PCI/P2PDMA: Add PCI p2pmem dma mappings to adjust the bus offset Logan Gunthorpe
2018-02-28 23:39 ` Logan Gunthorpe
2018-02-28 23:39 ` Logan Gunthorpe
2018-03-01 17:49 ` Bjorn Helgaas
2018-03-01 17:49 ` Bjorn Helgaas
2018-03-01 17:49 ` Bjorn Helgaas
2018-03-01 17:49 ` Bjorn Helgaas
2018-03-01 19:36 ` Logan Gunthorpe
2018-03-01 19:36 ` Logan Gunthorpe
2018-03-01 19:36 ` Logan Gunthorpe
2018-03-01 19:36 ` Logan Gunthorpe
2018-02-28 23:40 ` [PATCH v2 04/10] PCI/P2PDMA: Clear ACS P2P flags for all devices behind switches Logan Gunthorpe
2018-02-28 23:40 ` Logan Gunthorpe
2018-02-28 23:40 ` Logan Gunthorpe
2018-02-28 23:40 ` Logan Gunthorpe
2018-03-01 18:02 ` Bjorn Helgaas
2018-03-01 18:02 ` Bjorn Helgaas
2018-03-01 18:02 ` Bjorn Helgaas
2018-03-01 18:02 ` Bjorn Helgaas
2018-03-01 18:54 ` Stephen Bates
2018-03-01 18:54 ` Stephen Bates
2018-03-01 18:54 ` Stephen Bates
2018-03-01 18:54 ` Stephen Bates
2018-03-01 18:54 ` Stephen Bates
2018-03-01 21:21 ` Alex Williamson
2018-03-01 21:21 ` Alex Williamson
2018-03-01 21:21 ` Alex Williamson
2018-03-01 21:21 ` Alex Williamson
2018-03-01 21:26 ` Logan Gunthorpe
2018-03-01 21:26 ` Logan Gunthorpe
2018-03-01 21:26 ` Logan Gunthorpe
2018-03-01 21:26 ` Logan Gunthorpe
2018-03-01 21:32 ` Stephen Bates
2018-03-01 21:32 ` Stephen Bates
2018-03-01 21:32 ` Stephen Bates
2018-03-01 21:32 ` Stephen Bates
2018-03-01 21:32 ` Stephen Bates
2018-03-01 21:35 ` Jerome Glisse
2018-03-01 21:35 ` Jerome Glisse
2018-03-01 21:35 ` Jerome Glisse
2018-03-01 21:35 ` Jerome Glisse
2018-03-01 21:35 ` Jerome Glisse
2018-03-01 21:37 ` Logan Gunthorpe
2018-03-01 21:37 ` Logan Gunthorpe
2018-03-01 21:37 ` Logan Gunthorpe
2018-03-01 21:37 ` Logan Gunthorpe
2018-03-01 23:15 ` Bjorn Helgaas
2018-03-01 23:15 ` Bjorn Helgaas
2018-03-01 23:15 ` Bjorn Helgaas
2018-03-01 23:15 ` Bjorn Helgaas
2018-03-01 23:59 ` Logan Gunthorpe
2018-03-01 23:59 ` Logan Gunthorpe
2018-03-01 23:59 ` Logan Gunthorpe
2018-03-01 23:59 ` Logan Gunthorpe
2018-03-01 19:13 ` Logan Gunthorpe
2018-03-01 19:13 ` Logan Gunthorpe
2018-03-01 19:13 ` Logan Gunthorpe
2018-03-01 19:13 ` Logan Gunthorpe
2018-03-05 22:28 ` Bjorn Helgaas
2018-03-05 22:28 ` Bjorn Helgaas
2018-03-05 22:28 ` Bjorn Helgaas
2018-03-05 22:28 ` Bjorn Helgaas
2018-03-05 23:01 ` Logan Gunthorpe
2018-03-05 23:01 ` Logan Gunthorpe
2018-03-05 23:01 ` Logan Gunthorpe
2018-03-05 23:01 ` Logan Gunthorpe
2018-02-28 23:40 ` [PATCH v2 05/10] block: Introduce PCI P2P flags for request and request queue Logan Gunthorpe
2018-02-28 23:40 ` Logan Gunthorpe
2018-02-28 23:40 ` Logan Gunthorpe
2018-02-28 23:40 ` Logan Gunthorpe
2018-03-01 11:08 ` Sagi Grimberg
2018-03-01 11:08 ` Sagi Grimberg
2018-03-01 11:08 ` Sagi Grimberg
2018-03-01 11:08 ` Sagi Grimberg
2018-02-28 23:40 ` [PATCH v2 06/10] IB/core: Add optional PCI P2P flag to rdma_rw_ctx_[init|destroy]() Logan Gunthorpe
2018-02-28 23:40 ` Logan Gunthorpe
2018-02-28 23:40 ` Logan Gunthorpe
2018-02-28 23:40 ` Logan Gunthorpe
2018-03-01 10:32 ` Sagi Grimberg
2018-03-01 10:32 ` Sagi Grimberg
2018-03-01 10:32 ` Sagi Grimberg
2018-03-01 10:32 ` Sagi Grimberg
2018-03-01 17:16 ` Logan Gunthorpe
2018-03-01 17:16 ` Logan Gunthorpe
2018-03-01 17:16 ` Logan Gunthorpe
2018-03-01 17:16 ` Logan Gunthorpe
2018-02-28 23:40 ` [PATCH v2 07/10] nvme-pci: Use PCI p2pmem subsystem to manage the CMB Logan Gunthorpe
2018-02-28 23:40 ` Logan Gunthorpe
2018-02-28 23:40 ` Logan Gunthorpe
2018-02-28 23:40 ` Logan Gunthorpe
2018-03-05 1:33 ` Oliver
2018-03-05 1:33 ` Oliver
2018-03-05 1:33 ` Oliver
2018-03-05 1:33 ` Oliver
2018-03-05 16:00 ` Keith Busch
2018-03-05 16:00 ` Keith Busch
2018-03-05 16:00 ` Keith Busch
2018-03-05 16:00 ` Keith Busch
2018-03-05 17:10 ` Logan Gunthorpe
2018-03-05 17:10 ` Logan Gunthorpe
2018-03-05 17:10 ` Logan Gunthorpe
2018-03-05 17:10 ` Logan Gunthorpe
2018-03-05 18:02 ` Sinan Kaya
2018-03-05 18:02 ` Sinan Kaya
2018-03-05 18:02 ` Sinan Kaya
2018-03-05 18:09 ` Logan Gunthorpe
2018-03-05 18:09 ` Logan Gunthorpe
2018-03-05 18:09 ` Logan Gunthorpe
2018-03-06 0:49 ` Oliver
2018-03-06 0:49 ` Oliver
2018-03-06 0:49 ` Oliver
2018-03-06 0:49 ` Oliver
2018-03-06 1:14 ` Logan Gunthorpe
2018-03-06 1:14 ` Logan Gunthorpe
2018-03-06 1:14 ` Logan Gunthorpe
2018-03-06 1:14 ` Logan Gunthorpe
2018-03-06 10:40 ` Oliver
2018-03-06 10:40 ` Oliver
2018-03-06 10:40 ` Oliver
2018-03-06 10:40 ` Oliver
2018-03-05 19:57 ` Sagi Grimberg
2018-03-05 19:57 ` Sagi Grimberg
2018-03-05 19:57 ` Sagi Grimberg
2018-03-05 19:57 ` Sagi Grimberg
2018-03-05 20:10 ` Jason Gunthorpe
2018-03-05 20:10 ` Jason Gunthorpe
2018-03-05 20:10 ` Jason Gunthorpe
2018-03-05 20:10 ` Jason Gunthorpe
2018-03-05 20:16 ` Logan Gunthorpe
2018-03-05 20:16 ` Logan Gunthorpe
2018-03-05 20:16 ` Logan Gunthorpe
2018-03-05 20:42 ` Keith Busch
2018-03-05 20:42 ` Keith Busch
2018-03-05 20:42 ` Keith Busch
2018-03-05 20:42 ` Keith Busch
2018-03-05 20:50 ` Jason Gunthorpe
2018-03-05 20:50 ` Jason Gunthorpe
2018-03-05 20:50 ` Jason Gunthorpe
2018-03-05 20:13 ` Logan Gunthorpe
2018-03-05 20:13 ` Logan Gunthorpe
2018-03-05 20:13 ` Logan Gunthorpe
2018-03-05 20:13 ` Logan Gunthorpe
2018-02-28 23:40 ` [PATCH v2 08/10] nvme-pci: Add support for P2P memory in requests Logan Gunthorpe
2018-02-28 23:40 ` Logan Gunthorpe
2018-02-28 23:40 ` Logan Gunthorpe
2018-02-28 23:40 ` Logan Gunthorpe
2018-03-01 11:07 ` Sagi Grimberg
2018-03-01 11:07 ` Sagi Grimberg
2018-03-01 11:07 ` Sagi Grimberg
2018-03-01 11:07 ` Sagi Grimberg
2018-03-01 15:58 ` Stephen Bates
2018-03-01 15:58 ` Stephen Bates
2018-03-01 15:58 ` Stephen Bates
2018-03-01 15:58 ` Stephen Bates
2018-03-01 15:58 ` Stephen Bates
2018-03-09 5:08 ` Bart Van Assche
2018-03-09 5:08 ` Bart Van Assche
2018-03-09 5:08 ` Bart Van Assche
2018-03-09 5:08 ` Bart Van Assche
2018-03-09 5:08 ` Bart Van Assche
2018-02-28 23:40 ` [PATCH v2 09/10] nvme-pci: Add a quirk for a pseudo CMB Logan Gunthorpe
2018-02-28 23:40 ` Logan Gunthorpe
2018-02-28 23:40 ` Logan Gunthorpe
2018-02-28 23:40 ` Logan Gunthorpe
2018-03-01 11:03 ` Sagi Grimberg
2018-03-01 11:03 ` Sagi Grimberg
2018-03-01 11:03 ` Sagi Grimberg
2018-03-01 11:03 ` Sagi Grimberg
2018-02-28 23:40 ` [PATCH v2 10/10] nvmet: Optionally use PCI P2P memory Logan Gunthorpe
2018-02-28 23:40 ` Logan Gunthorpe
2018-02-28 23:40 ` Logan Gunthorpe
2018-02-28 23:40 ` Logan Gunthorpe
2018-03-01 11:03 ` Sagi Grimberg
2018-03-01 11:03 ` Sagi Grimberg
2018-03-01 11:03 ` Sagi Grimberg
2018-03-01 11:03 ` Sagi Grimberg
2018-03-01 16:15 ` Stephen Bates
2018-03-01 16:15 ` Stephen Bates
2018-03-01 16:15 ` Stephen Bates
2018-03-01 16:15 ` Stephen Bates
2018-03-01 16:15 ` Stephen Bates
2018-03-01 17:40 ` Logan Gunthorpe
2018-03-01 17:40 ` Logan Gunthorpe
2018-03-01 17:40 ` Logan Gunthorpe
2018-03-01 17:40 ` Logan Gunthorpe
2018-03-01 18:35 ` Sagi Grimberg
2018-03-01 18:35 ` Sagi Grimberg
2018-03-01 18:35 ` Sagi Grimberg
2018-03-01 18:35 ` Sagi Grimberg
2018-03-01 18:42 ` Jason Gunthorpe
2018-03-01 18:42 ` Jason Gunthorpe
2018-03-01 19:01 ` Stephen Bates
2018-03-01 19:01 ` Stephen Bates
2018-03-01 19:01 ` Stephen Bates
2018-03-01 19:01 ` Stephen Bates
2018-03-01 19:01 ` Stephen Bates
2018-03-01 19:27 ` Logan Gunthorpe
2018-03-01 19:27 ` Logan Gunthorpe
2018-03-01 19:27 ` Logan Gunthorpe
2018-03-01 19:27 ` Logan Gunthorpe
2018-03-01 22:45 ` Jason Gunthorpe
2018-03-01 22:45 ` Jason Gunthorpe
2018-03-01 22:56 ` Logan Gunthorpe
2018-03-01 22:56 ` Logan Gunthorpe
2018-03-01 22:56 ` Logan Gunthorpe
2018-03-01 22:56 ` Logan Gunthorpe
2018-03-01 23:00 ` Stephen Bates
2018-03-01 23:00 ` Stephen Bates
2018-03-01 23:00 ` Stephen Bates
2018-03-01 23:00 ` Stephen Bates
2018-03-01 23:00 ` Stephen Bates
2018-03-01 23:20 ` Jason Gunthorpe
2018-03-01 23:20 ` Jason Gunthorpe
2018-03-01 23:20 ` Jason Gunthorpe
2018-03-01 23:29 ` Logan Gunthorpe
2018-03-01 23:29 ` Logan Gunthorpe
2018-03-01 23:29 ` Logan Gunthorpe
2018-03-01 23:29 ` Logan Gunthorpe
2018-03-01 23:32 ` Stephen Bates
2018-03-01 23:32 ` Stephen Bates
2018-03-01 23:32 ` Stephen Bates
2018-03-01 23:32 ` Stephen Bates
2018-03-01 23:32 ` Stephen Bates
2018-03-01 23:49 ` Keith Busch
2018-03-01 23:49 ` Keith Busch
2018-03-01 23:49 ` Keith Busch
2018-03-01 23:49 ` Keith Busch
2018-03-01 23:52 ` Logan Gunthorpe
2018-03-01 23:52 ` Logan Gunthorpe
2018-03-01 23:52 ` Logan Gunthorpe
2018-03-01 23:52 ` Logan Gunthorpe
2018-03-01 23:53 ` Stephen Bates
2018-03-01 23:53 ` Stephen Bates
2018-03-01 23:53 ` Stephen Bates
2018-03-01 23:53 ` Stephen Bates
2018-03-01 23:53 ` Stephen Bates
2018-03-02 15:53 ` Christoph Hellwig
2018-03-02 15:53 ` Christoph Hellwig
2018-03-02 15:53 ` Christoph Hellwig
2018-03-02 15:53 ` Christoph Hellwig
2018-03-02 20:51 ` Stephen Bates
2018-03-02 20:51 ` Stephen Bates
2018-03-02 20:51 ` Stephen Bates
2018-03-02 20:51 ` Stephen Bates
2018-03-01 23:57 ` Stephen Bates
2018-03-01 23:57 ` Stephen Bates
2018-03-01 23:57 ` Stephen Bates
2018-03-01 23:57 ` Stephen Bates
2018-03-01 23:57 ` Stephen Bates
2018-03-02 0:03 ` Logan Gunthorpe
2018-03-02 0:03 ` Logan Gunthorpe
2018-03-02 0:03 ` Logan Gunthorpe
2018-03-02 0:03 ` Logan Gunthorpe
2018-03-02 16:18 ` Jason Gunthorpe
2018-03-02 16:18 ` Jason Gunthorpe
2018-03-02 16:18 ` Jason Gunthorpe
2018-03-02 17:10 ` Logan Gunthorpe
2018-03-02 17:10 ` Logan Gunthorpe
2018-03-02 17:10 ` Logan Gunthorpe
2018-03-02 17:10 ` Logan Gunthorpe
2018-03-01 19:10 ` Logan Gunthorpe
2018-03-01 19:10 ` Logan Gunthorpe
2018-03-01 19:10 ` Logan Gunthorpe
2018-03-01 19:10 ` Logan Gunthorpe
2018-03-01 3:54 ` [PATCH v2 00/10] Copy Offload in NVMe Fabrics with P2P PCI Memory Benjamin Herrenschmidt
2018-03-01 3:54 ` Benjamin Herrenschmidt
2018-03-01 3:54 ` Benjamin Herrenschmidt
2018-03-01 3:54 ` Benjamin Herrenschmidt
2018-03-01 3:56 ` Benjamin Herrenschmidt
2018-03-01 3:56 ` Benjamin Herrenschmidt
2018-03-01 3:56 ` Benjamin Herrenschmidt
2018-03-01 3:56 ` Benjamin Herrenschmidt
2018-03-01 18:04 ` Logan Gunthorpe
2018-03-01 18:04 ` Logan Gunthorpe
2018-03-01 18:04 ` Logan Gunthorpe
2018-03-01 18:04 ` Logan Gunthorpe
2018-03-01 20:29 ` Benjamin Herrenschmidt
2018-03-01 20:29 ` Benjamin Herrenschmidt
2018-03-01 20:29 ` Benjamin Herrenschmidt
2018-03-01 20:29 ` Benjamin Herrenschmidt
2018-03-01 20:55 ` Jerome Glisse
2018-03-01 20:55 ` Jerome Glisse
2018-03-01 20:55 ` Jerome Glisse
2018-03-01 20:55 ` Jerome Glisse
2018-03-01 20:55 ` Jerome Glisse
2018-03-01 21:03 ` Logan Gunthorpe
2018-03-01 21:03 ` Logan Gunthorpe
2018-03-01 21:03 ` Logan Gunthorpe
2018-03-01 21:03 ` Logan Gunthorpe
2018-03-01 21:10 ` Jerome Glisse
2018-03-01 21:10 ` Jerome Glisse
2018-03-01 21:10 ` Jerome Glisse
2018-03-01 21:10 ` Jerome Glisse
2018-03-01 21:10 ` Jerome Glisse
2018-03-01 21:15 ` Logan Gunthorpe
2018-03-01 21:15 ` Logan Gunthorpe
2018-03-01 21:15 ` Logan Gunthorpe
2018-03-01 21:15 ` Logan Gunthorpe
2018-03-01 21:25 ` Jerome Glisse
2018-03-01 21:25 ` Jerome Glisse
2018-03-01 21:25 ` Jerome Glisse
2018-03-01 21:25 ` Jerome Glisse
2018-03-01 21:25 ` Jerome Glisse
2018-03-01 21:37 ` Stephen Bates
2018-03-01 21:37 ` Stephen Bates
2018-03-01 21:37 ` Stephen Bates
2018-03-01 21:37 ` Stephen Bates
2018-03-01 21:37 ` Stephen Bates
2018-03-02 21:38 ` Stephen Bates
2018-03-02 21:38 ` Stephen Bates
2018-03-02 21:38 ` Stephen Bates
2018-03-02 21:38 ` Stephen Bates
2018-03-02 21:38 ` Stephen Bates
2018-03-02 22:09 ` Jerome Glisse
2018-03-02 22:09 ` Jerome Glisse
2018-03-02 22:09 ` Jerome Glisse
2018-03-02 22:09 ` Jerome Glisse
2018-03-02 22:09 ` Jerome Glisse
2018-03-05 20:36 ` Stephen Bates
2018-03-05 20:36 ` Stephen Bates
2018-03-05 20:36 ` Stephen Bates
2018-03-05 20:36 ` Stephen Bates
2018-03-05 20:36 ` Stephen Bates
2018-03-01 20:55 ` Logan Gunthorpe
2018-03-01 20:55 ` Logan Gunthorpe
2018-03-01 20:55 ` Logan Gunthorpe
2018-03-01 20:55 ` Logan Gunthorpe
2018-03-01 18:09 ` Stephen Bates
2018-03-01 18:09 ` Stephen Bates
2018-03-01 18:09 ` Stephen Bates
2018-03-01 18:09 ` Stephen Bates
2018-03-01 18:09 ` Stephen Bates
2018-03-01 20:32 ` Benjamin Herrenschmidt
2018-03-01 20:32 ` Benjamin Herrenschmidt
2018-03-01 20:32 ` Benjamin Herrenschmidt
2018-03-01 20:32 ` Benjamin Herrenschmidt
2018-03-01 19:21 ` Dan Williams
2018-03-01 19:21 ` Dan Williams
2018-03-01 19:21 ` Dan Williams
2018-03-01 19:21 ` Dan Williams
2018-03-01 19:30 ` Logan Gunthorpe
2018-03-01 19:30 ` Logan Gunthorpe
2018-03-01 19:30 ` Logan Gunthorpe
2018-03-01 19:30 ` Logan Gunthorpe
2018-03-01 20:34 ` Benjamin Herrenschmidt
2018-03-01 20:34 ` Benjamin Herrenschmidt
2018-03-01 20:34 ` Benjamin Herrenschmidt
2018-03-01 20:34 ` Benjamin Herrenschmidt
2018-03-01 20:40 ` Benjamin Herrenschmidt
2018-03-01 20:40 ` Benjamin Herrenschmidt
2018-03-01 20:40 ` Benjamin Herrenschmidt
2018-03-01 20:40 ` Benjamin Herrenschmidt
2018-03-01 20:53 ` Jason Gunthorpe
2018-03-01 20:53 ` Jason Gunthorpe
2018-03-01 20:57 ` Logan Gunthorpe
2018-03-01 20:57 ` Logan Gunthorpe
2018-03-01 20:57 ` Logan Gunthorpe
2018-03-01 20:57 ` Logan Gunthorpe
2018-03-01 22:06 ` Benjamin Herrenschmidt
2018-03-01 22:06 ` Benjamin Herrenschmidt
2018-03-01 22:06 ` Benjamin Herrenschmidt
2018-03-01 22:06 ` Benjamin Herrenschmidt
2018-03-01 22:31 ` Linus Torvalds
2018-03-01 22:31 ` Linus Torvalds
2018-03-01 22:31 ` Linus Torvalds
2018-03-01 22:31 ` Linus Torvalds
2018-03-01 22:34 ` Benjamin Herrenschmidt
2018-03-01 22:34 ` Benjamin Herrenschmidt
2018-03-01 22:34 ` Benjamin Herrenschmidt
2018-03-01 22:34 ` Benjamin Herrenschmidt
2018-03-02 16:22 ` Kani, Toshi
2018-03-02 16:22 ` Kani, Toshi
2018-03-02 16:22 ` Kani, Toshi
2018-03-02 16:22 ` Kani, Toshi
2018-03-02 16:22 ` Kani, Toshi
2018-03-02 16:57 ` Linus Torvalds
2018-03-02 16:57 ` Linus Torvalds
2018-03-02 16:57 ` Linus Torvalds
2018-03-02 16:57 ` Linus Torvalds
2018-03-02 17:34 ` Linus Torvalds
2018-03-02 17:34 ` Linus Torvalds
2018-03-02 17:34 ` Linus Torvalds
2018-03-02 17:34 ` Linus Torvalds
2018-03-02 17:38 ` Kani, Toshi [this message]
2018-03-02 17:38 ` Kani, Toshi
2018-03-02 17:38 ` Kani, Toshi
2018-03-02 17:38 ` Kani, Toshi
2018-03-02 17:38 ` Kani, Toshi
2018-03-01 21:37 ` Dan Williams
2018-03-01 21:37 ` Dan Williams
2018-03-01 21:37 ` Dan Williams
2018-03-01 21:37 ` Dan Williams
2018-03-01 21:45 ` Logan Gunthorpe
2018-03-01 21:45 ` Logan Gunthorpe
2018-03-01 21:45 ` Logan Gunthorpe
2018-03-01 21:57 ` Logan Gunthorpe
2018-03-01 21:57 ` Logan Gunthorpe
2018-03-01 21:57 ` Logan Gunthorpe
2018-03-01 21:57 ` Logan Gunthorpe
2018-03-01 23:00 ` Benjamin Herrenschmidt
2018-03-01 23:00 ` Benjamin Herrenschmidt
2018-03-01 23:00 ` Benjamin Herrenschmidt
2018-03-01 23:00 ` Benjamin Herrenschmidt
2018-03-01 23:19 ` Logan Gunthorpe
2018-03-01 23:19 ` Logan Gunthorpe
2018-03-01 23:19 ` Logan Gunthorpe
2018-03-01 23:19 ` Logan Gunthorpe
2018-03-01 23:25 ` Benjamin Herrenschmidt
2018-03-01 23:25 ` Benjamin Herrenschmidt
2018-03-01 23:25 ` Benjamin Herrenschmidt
2018-03-01 23:25 ` Benjamin Herrenschmidt
2018-03-02 21:44 ` Benjamin Herrenschmidt
2018-03-02 21:44 ` Benjamin Herrenschmidt
2018-03-02 21:44 ` Benjamin Herrenschmidt
2018-03-02 21:44 ` Benjamin Herrenschmidt
2018-03-02 22:24 ` Logan Gunthorpe
2018-03-02 22:24 ` Logan Gunthorpe
2018-03-02 22:24 ` Logan Gunthorpe
2018-03-02 22:24 ` Logan Gunthorpe
2018-03-01 23:26 ` Benjamin Herrenschmidt
2018-03-01 23:26 ` Benjamin Herrenschmidt
2018-03-01 23:26 ` Benjamin Herrenschmidt
2018-03-01 23:26 ` Benjamin Herrenschmidt
2018-03-01 23:54 ` Logan Gunthorpe
2018-03-01 23:54 ` Logan Gunthorpe
2018-03-01 23:54 ` Logan Gunthorpe
2018-03-01 23:54 ` Logan Gunthorpe
2018-03-01 21:03 ` Benjamin Herrenschmidt
2018-03-01 21:03 ` Benjamin Herrenschmidt
2018-03-01 21:03 ` Benjamin Herrenschmidt
2018-03-01 21:03 ` Benjamin Herrenschmidt
2018-03-01 21:11 ` Logan Gunthorpe
2018-03-01 21:11 ` Logan Gunthorpe
2018-03-01 21:11 ` Logan Gunthorpe
2018-03-01 21:11 ` Logan Gunthorpe
2018-03-01 21:18 ` Jerome Glisse
2018-03-01 21:18 ` Jerome Glisse
2018-03-01 21:18 ` Jerome Glisse
2018-03-01 21:18 ` Jerome Glisse
2018-03-01 21:18 ` Jerome Glisse
2018-03-01 21:22 ` Logan Gunthorpe
2018-03-01 21:22 ` Logan Gunthorpe
2018-03-01 21:22 ` Logan Gunthorpe
2018-03-01 21:22 ` Logan Gunthorpe
2018-03-01 10:31 ` Sagi Grimberg
2018-03-01 10:31 ` Sagi Grimberg
2018-03-01 10:31 ` Sagi Grimberg
2018-03-01 10:31 ` Sagi Grimberg
2018-03-01 19:33 ` Logan Gunthorpe
2018-03-01 19:33 ` Logan Gunthorpe
2018-03-01 19:33 ` Logan Gunthorpe
2018-03-01 19:33 ` Logan Gunthorpe
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