[PATCH V3 02/10] MIPS: Loongson64: Define and use some CP0 registers

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From: Huacai Chen <chenhc@lemote.com>
To: Ralf Baechle <ralf@linux-mips.org>
Cc: James Hogan <james.hogan@mips.com>,
	linux-mips@linux-mips.org, Fuxin Zhang <zhangfx@lemote.com>,
	Zhangjin Wu <wuzhangjin@gmail.com>,
	Huacai Chen <chenhuacai@gmail.com>,
	Huacai Chen <chenhc@lemote.com>
Subject: [PATCH V3 02/10] MIPS: Loongson64: Define and use some CP0 registers
Date: Sat, 28 Apr 2018 11:21:26 +0800	[thread overview]
Message-ID: <1524885694-18132-3-git-send-email-chenhc@lemote.com> (raw)
In-Reply-To: <1524885694-18132-1-git-send-email-chenhc@lemote.com>

Defines CP0_CONFIG3, CP0_CONFIG6, CP0_PAGEGRAIN and use them in
kernel-entry-init.h for Loongson64.

Signed-off-by: Huacai Chen <chenhc@lemote.com>
---
 .../asm/mach-loongson64/kernel-entry-init.h        | 24 +++++++++++-----------
 arch/mips/include/asm/mipsregs.h                   |  2 ++
 2 files changed, 14 insertions(+), 12 deletions(-)

diff --git a/arch/mips/include/asm/mach-loongson64/kernel-entry-init.h b/arch/mips/include/asm/mach-loongson64/kernel-entry-init.h
index 8393bc54..3127391 100644
--- a/arch/mips/include/asm/mach-loongson64/kernel-entry-init.h
+++ b/arch/mips/include/asm/mach-loongson64/kernel-entry-init.h
@@ -19,18 +19,18 @@
 	.set	push
 	.set	mips64
 	/* Set LPA on LOONGSON3 config3 */
-	mfc0	t0, $16, 3
+	mfc0	t0, CP0_CONFIG3
 	or	t0, (0x1 << 7)
-	mtc0	t0, $16, 3
+	mtc0	t0, CP0_CONFIG3
 	/* Set ELPA on LOONGSON3 pagegrain */
-	mfc0	t0, $5, 1
+	mfc0	t0, CP0_PAGEGRAIN
 	or	t0, (0x1 << 29)
-	mtc0	t0, $5, 1
+	mtc0	t0, CP0_PAGEGRAIN
 #ifdef CONFIG_LOONGSON3_ENHANCEMENT
 	/* Enable STFill Buffer */
-	mfc0	t0, $16, 6
+	mfc0	t0, CP0_CONFIG6
 	or	t0, 0x100
-	mtc0	t0, $16, 6
+	mtc0	t0, CP0_CONFIG6
 #endif
 	_ehb
 	.set	pop
@@ -45,18 +45,18 @@
 	.set	push
 	.set	mips64
 	/* Set LPA on LOONGSON3 config3 */
-	mfc0	t0, $16, 3
+	mfc0	t0, CP0_CONFIG3
 	or	t0, (0x1 << 7)
-	mtc0	t0, $16, 3
+	mtc0	t0, CP0_CONFIG3
 	/* Set ELPA on LOONGSON3 pagegrain */
-	mfc0	t0, $5, 1
+	mfc0	t0, CP0_PAGEGRAIN
 	or	t0, (0x1 << 29)
-	mtc0	t0, $5, 1
+	mtc0	t0, CP0_PAGEGRAIN
 #ifdef CONFIG_LOONGSON3_ENHANCEMENT
 	/* Enable STFill Buffer */
-	mfc0	t0, $16, 6
+	mfc0	t0, CP0_CONFIG6
 	or	t0, 0x100
-	mtc0	t0, $16, 6
+	mtc0	t0, CP0_CONFIG6
 #endif
 	_ehb
 	.set	pop
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index f658597..38779b8 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -51,6 +51,7 @@
 #define CP0_GLOBALNUMBER $3, 1
 #define CP0_CONTEXT $4
 #define CP0_PAGEMASK $5
+#define CP0_PAGEGRAIN $5, 1
 #define CP0_SEGCTL0 $5, 2
 #define CP0_SEGCTL1 $5, 3
 #define CP0_SEGCTL2 $5, 4
@@ -77,6 +78,7 @@
 #define CP0_CONFIG $16
 #define CP0_CONFIG3 $16, 3
 #define CP0_CONFIG5 $16, 5
+#define CP0_CONFIG6 $16, 6
 #define CP0_LLADDR $17
 #define CP0_WATCHLO $18
 #define CP0_WATCHHI $19
-- 
2.7.0

next prev parent reply	other threads:[~2018-04-28  3:20 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-04-28  3:21 [PATCH V3 00/10] MIPS: Loongson: new features and improvements Huacai Chen
2018-04-28  3:21 ` [PATCH V3 01/10] MIPS: Loongson: Add Loongson-3A R3.1 basic support Huacai Chen
2018-07-24  1:35   ` Paul Burton
2018-04-28  3:21 ` Huacai Chen [this message]
2018-07-24  1:36   ` [PATCH V3 02/10] MIPS: Loongson64: Define and use some CP0 registers Paul Burton
2018-04-28  3:21 ` [PATCH V3 03/10] MIPS: Loongson-3: Enable Store Fill Buffer at runtime Huacai Chen
2018-06-18 21:05   ` Paul Burton
2018-06-18 21:05     ` Paul Burton
     [not found]     ` <tencent_3C127D3D5620B83833D77E8A@qq.com>
2018-07-24  1:21       ` [PATCH V3 03/10] MIPS: Loongson-3: Enable Store Fill Buffer atruntime Paul Burton
2018-07-25  2:08         ` Huacai Chen
2018-07-25  2:21           ` Paul Burton
2018-04-28  3:21 ` [PATCH V3 04/10] MIPS: c-r4k: Add r4k_blast_scache_node for Loongson-3 Huacai Chen
2018-04-28  3:21 ` [PATCH V3 05/10] MIPS: Ensure pmd_present() returns false after pmd_mknotpresent() Huacai Chen
2018-04-28  3:21 ` [PATCH V3 06/10] MIPS: Add __cpu_full_name[] to make CPU names more human-readable Huacai Chen
2018-04-28  3:21 ` [PATCH V3 07/10] MIPS: Align kernel load address to 64KB Huacai Chen
2018-04-28  3:21 ` [PATCH V3 08/10] MIPS: Loongson64: Add kexec/kdump support Huacai Chen
2018-04-28  3:21 ` [PATCH V3 09/10] MIPS: Loongson-3: Fix CPU UART irq delivery problem Huacai Chen
2018-04-28  3:21 ` [PATCH V3 10/10] MIPS: Loongson: Introduce and use WAR_LLSC_MB Huacai Chen

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