From: Huacai Chen <chenhc@lemote.com>
To: Ralf Baechle <ralf@linux-mips.org>
Cc: James Hogan <james.hogan@mips.com>,
linux-mips@linux-mips.org, Fuxin Zhang <zhangfx@lemote.com>,
Zhangjin Wu <wuzhangjin@gmail.com>,
Huacai Chen <chenhuacai@gmail.com>,
Huacai Chen <chenhc@lemote.com>,
"# 2 . 6 . 36+" <stable@vger.kernel.org>
Subject: [PATCH V3 07/10] MIPS: Align kernel load address to 64KB
Date: Sat, 28 Apr 2018 11:21:31 +0800 [thread overview]
Message-ID: <1524885694-18132-8-git-send-email-chenhc@lemote.com> (raw)
In-Reply-To: <1524885694-18132-1-git-send-email-chenhc@lemote.com>
KEXEC needs the new kernel's load address to be aligned on a page
boundary (see sanity_check_segment_list()), but on MIPS the default
vmlinuz load address is only explicitly aligned to 16 bytes.
Since the largest PAGE_SIZE supported by MIPS kernels is 64KB, increase
the alignment calculated by calc_vmlinuz_load_addr to 64KB.
Cc: <stable@vger.kernel.org> # 2.6.36+
Signed-off-by: Huacai Chen <chenhc@lemote.com>
---
arch/mips/boot/compressed/calc_vmlinuz_load_addr.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/arch/mips/boot/compressed/calc_vmlinuz_load_addr.c b/arch/mips/boot/compressed/calc_vmlinuz_load_addr.c
index 37fe58c..542c3ed 100644
--- a/arch/mips/boot/compressed/calc_vmlinuz_load_addr.c
+++ b/arch/mips/boot/compressed/calc_vmlinuz_load_addr.c
@@ -13,6 +13,7 @@
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
+#include "../../../../include/linux/sizes.h"
int main(int argc, char *argv[])
{
@@ -45,11 +46,11 @@ int main(int argc, char *argv[])
vmlinuz_load_addr = vmlinux_load_addr + vmlinux_size;
/*
- * Align with 16 bytes: "greater than that used for any standard data
- * types by a MIPS compiler." -- See MIPS Run Linux (Second Edition).
+ * Align with 64KB: KEXEC needs load sections to be aligned to PAGE_SIZE,
+ * which may be as large as 64KB depending on the kernel configuration.
*/
- vmlinuz_load_addr += (16 - vmlinux_size % 16);
+ vmlinuz_load_addr += (SZ_64K - vmlinux_size % SZ_64K);
printf("0x%llx\n", vmlinuz_load_addr);
--
2.7.0
next prev parent reply other threads:[~2018-04-28 3:23 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-04-28 3:21 [PATCH V3 00/10] MIPS: Loongson: new features and improvements Huacai Chen
2018-04-28 3:21 ` [PATCH V3 01/10] MIPS: Loongson: Add Loongson-3A R3.1 basic support Huacai Chen
2018-07-24 1:35 ` Paul Burton
2018-04-28 3:21 ` [PATCH V3 02/10] MIPS: Loongson64: Define and use some CP0 registers Huacai Chen
2018-07-24 1:36 ` Paul Burton
2018-04-28 3:21 ` [PATCH V3 03/10] MIPS: Loongson-3: Enable Store Fill Buffer at runtime Huacai Chen
2018-06-18 21:05 ` Paul Burton
2018-06-18 21:05 ` Paul Burton
[not found] ` <tencent_3C127D3D5620B83833D77E8A@qq.com>
2018-07-24 1:21 ` [PATCH V3 03/10] MIPS: Loongson-3: Enable Store Fill Buffer atruntime Paul Burton
2018-07-25 2:08 ` Huacai Chen
2018-07-25 2:21 ` Paul Burton
2018-04-28 3:21 ` [PATCH V3 04/10] MIPS: c-r4k: Add r4k_blast_scache_node for Loongson-3 Huacai Chen
2018-04-28 3:21 ` [PATCH V3 05/10] MIPS: Ensure pmd_present() returns false after pmd_mknotpresent() Huacai Chen
2018-04-28 3:21 ` [PATCH V3 06/10] MIPS: Add __cpu_full_name[] to make CPU names more human-readable Huacai Chen
2018-04-28 3:21 ` Huacai Chen [this message]
2018-04-28 3:21 ` [PATCH V3 08/10] MIPS: Loongson64: Add kexec/kdump support Huacai Chen
2018-04-28 3:21 ` [PATCH V3 09/10] MIPS: Loongson-3: Fix CPU UART irq delivery problem Huacai Chen
2018-04-28 3:21 ` [PATCH V3 10/10] MIPS: Loongson: Introduce and use WAR_LLSC_MB Huacai Chen
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