All of lore.kernel.org
 help / color / mirror / Atom feed
* [PATCH] drm/i915: configure the transcoder clocks before touching pipeconf on HSW+
@ 2018-04-27 23:12 Paulo Zanoni
  2018-04-30 11:28 ` ✓ Fi.CI.BAT: success for " Patchwork
                   ` (11 more replies)
  0 siblings, 12 replies; 17+ messages in thread
From: Paulo Zanoni @ 2018-04-27 23:12 UTC (permalink / raw)
  To: intel-gfx; +Cc: Arthur J Runyan, Paulo Zanoni

For all platforms that run haswell_crtc_enable, our spec tells us to
configure the transcoder clocks before it tells us to set pipeconf and
the other pipe/transcoder/plane registers.

For some reason we've been able to get away with doing what we were
doing until now, but starting from Icelake, we get machine hangs if we
try to touch the pipe/transcoder registers without having the clocks
configured.

So this patch changes all the relevant platforms to call
intel_ddi_enable_pipe_clock at the point we're supposed to, according
to the spec.

It seems there is a way to work around this problem on ICL with some
chicken bit, but I still couldn't find which one it is, and it's
better if we just do the right thing here.

Cc: Arthur J Runyan <arthur.j.runyan@intel.com>
Cc: James Ausmus <james.ausmus@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

Luckily our CI system should be in a spot where it is able to tell us
whether this patch is good with high confidence. I haven't tested it
on every affected platform.

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 48576ea2d36c..c93aed2ec16d 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5578,8 +5578,11 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
 				     &intel_crtc->config->fdi_m_n, NULL);
 	}
 
-	if (!transcoder_is_dsi(cpu_transcoder))
+	if (!transcoder_is_dsi(cpu_transcoder)) {
+		intel_ddi_enable_pipe_clock(pipe_config);
+
 		haswell_set_pipeconf(crtc);
+	}
 
 	haswell_set_pipemisc(crtc);
 
@@ -5589,9 +5592,6 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
 
 	intel_encoders_pre_enable(crtc, pipe_config, old_state);
 
-	if (!transcoder_is_dsi(cpu_transcoder))
-		intel_ddi_enable_pipe_clock(pipe_config);
-
 	/* Display WA #1180: WaDisableScalarClockGating: glk, cnl */
 	psl_clkgate_wa = (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) &&
 			 intel_crtc->config->pch_pfit.enabled;
-- 
2.14.3

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 17+ messages in thread
end of thread, other threads:[~2018-05-08  0:57 UTC | newest]

Thread overview: 17+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2018-04-27 23:12 [PATCH] drm/i915: configure the transcoder clocks before touching pipeconf on HSW+ Paulo Zanoni
2018-04-30 11:28 ` ✓ Fi.CI.BAT: success for " Patchwork
2018-04-30 12:17 ` Patchwork
2018-04-30 12:40 ` Patchwork
2018-04-30 14:20 ` ✓ Fi.CI.IGT: " Patchwork
2018-04-30 15:36 ` Patchwork
2018-04-30 16:18 ` Patchwork
2018-04-30 18:12 ` [PATCH] " Ville Syrjälä
2018-05-02 21:06   ` Paulo Zanoni
2018-05-02 21:58 ` [PATCH] drm/i915: enable the pipe/transcoder/planes later " Paulo Zanoni
2018-05-02 22:07   ` Rodrigo Vivi
2018-05-02 22:19   ` Manasi Navare
2018-05-02 22:23 ` ✗ Fi.CI.BAT: failure for drm/i915: configure the transcoder clocks before touching pipeconf on HSW+ (rev2) Patchwork
2018-05-04 19:56   ` Paulo Zanoni
2018-05-02 23:47 ` Patchwork
2018-05-08  0:10 ` ✓ Fi.CI.BAT: success " Patchwork
2018-05-08  0:57 ` ✗ Fi.CI.IGT: failure " Patchwork

This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.