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From: Paulo Zanoni <paulo.r.zanoni@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Jani Nikula <jani.nikula@intel.com>,
	"Vivi, Rodrigo" <rodrigo.vivi@intel.com>
Subject: Re: ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,1/2] drm/i915/icl: Add allowed DP rates for Icelake
Date: Mon, 11 Jun 2018 17:20:52 -0700	[thread overview]
Message-ID: <1528762852.2604.15.camel@intel.com> (raw)
In-Reply-To: <20180611223533.25081.80634@emeril.freedesktop.org>

Em Seg, 2018-06-11 às 22:35 +0000, Patchwork escreveu:
> == Series Details ==
> 
> Series: series starting with [CI,1/2] drm/i915/icl: Add allowed DP
> rates for Icelake
> URL   : https://patchwork.freedesktop.org/series/44595/
> State : warning
> 
> == Summary ==
> 
> $ dim checkpatch origin/drm-tip
> e6e6b2f7af58 drm/i915/icl: Add allowed DP rates for Icelake
> 3fe43cb729fe drm/i915/dp: Add support for HBR3 and TPS4 during link
> training
> -:26: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
> #26: FILE: drivers/gpu/drm/i915/i915_reg.h:8694:
> +#define  DP_TP_CTL_LINK_TRAIN_PAT4		(5<<8)

Dear maintainers,

I get this type of error way too often. What's the most desirable thing
here?

1 - Make it "(5 << 8)" so checkpatch doesn't complain, which will leave
the coding style inconsistent with the surrounding lines.

2 - Drive-by fix all the bits around it so everybody in the same
definition has nice spaces, 2.a: in the same patch, 2.b: in a separate
patch.

3 - Just ignore the checkpatch message, push code as-is.

4 - Blacklist this check from checkpatch.

5 - Submit a separate patch fixing all the spacing errors on i915_reg.h
once and for all. Live happily ever after.

6 - Submit a separate patch converting everything to BIT() on
i915_reg.h.


Thanks,
Paulo

>                                    		  ^
> 
> total: 0 errors, 0 warnings, 1 checks, 127 lines checked
> 
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  reply	other threads:[~2018-06-12  0:21 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-06-11 22:26 [CI 1/2] drm/i915/icl: Add allowed DP rates for Icelake Paulo Zanoni
2018-06-11 22:26 ` [CI 2/2] drm/i915/dp: Add support for HBR3 and TPS4 during link training Paulo Zanoni
2018-06-11 22:35 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,1/2] drm/i915/icl: Add allowed DP rates for Icelake Patchwork
2018-06-12  0:20   ` Paulo Zanoni [this message]
2018-06-12  8:46     ` Jani Nikula
2018-06-12 21:52       ` Rodrigo Vivi
2018-06-13  8:07         ` Jani Nikula
2018-06-13 16:59           ` Paulo Zanoni
2018-06-11 22:55 ` ✓ Fi.CI.BAT: success " Patchwork
2018-06-12  4:50 ` ✓ Fi.CI.IGT: " Patchwork
2018-06-12 12:15 ` [CI 1/2] " Ville Syrjälä
2018-06-12 18:37   ` Manasi Navare
2018-06-13 19:42     ` Paulo Zanoni
2018-06-13 20:15       ` Manasi Navare
2018-06-13 20:31         ` Paulo Zanoni

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