Re: ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,1/2] drm/i915/icl: Add allowed DP rates for Icelake

From: Paulo Zanoni <paulo.r.zanoni@intel.com>
To: Jani Nikula <jani.nikula@intel.com>,
	Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,1/2] drm/i915/icl: Add allowed DP rates for Icelake
Date: Wed, 13 Jun 2018 09:59:10 -0700	[thread overview]
Message-ID: <1528909150.2597.5.camel@intel.com> (raw)
In-Reply-To: <87h8m71543.fsf@intel.com>

Em Qua, 2018-06-13 às 11:07 +0300, Jani Nikula escreveu:
> On Tue, 12 Jun 2018, Rodrigo Vivi <rodrigo.vivi@intel.com> wrote:
> > Do we really want BIT everywhere?!
> 
> I think I'd go for everywhere except part of a register field value:
> 

While I completely agree with your reasoning, this means we'll kinda
always want to blacklist the BIT_MACRO checkpath type because
checkpatch won't know about these exceptions, which means we won't
actually need to convert everything to BIT() since no false negative
emails anyway.

Anyway, I submitted a patch to fix the spacing issues, I'd love to have
some comments from the maintainers on it.

Thanks,
Paulo

> #define SINGLE_BIT_OKAY		BIT(25)
> #define FIELD_SHIFT		20
> #define FIELD_MASK		(0xf << 20)
> #define FIELD_FOO_PLEASE_NO	BIT(20)		/* Don't do
> this */
> #define FIELD_FOO		(1 << 20)	/* This is
> consistent */
> #define FIELD_BAR		(2 << 20)
> #define FIELD_BAZ		(3 << 20)
> 
> 
> BR,
> Jani.
> 
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