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From: Jani Nikula <jani.nikula@intel.com>
To: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: intel-gfx@lists.freedesktop.org, Paulo Zanoni <paulo.r.zanoni@intel.com>
Subject: Re: ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,1/2] drm/i915/icl: Add allowed DP rates for Icelake
Date: Wed, 13 Jun 2018 11:07:56 +0300	[thread overview]
Message-ID: <87h8m71543.fsf@intel.com> (raw)
In-Reply-To: <20180612215244.GT2228@intel.com>

On Tue, 12 Jun 2018, Rodrigo Vivi <rodrigo.vivi@intel.com> wrote:
> Do we really want BIT everywhere?!

I think I'd go for everywhere except part of a register field value:

#define SINGLE_BIT_OKAY		BIT(25)
#define FIELD_SHIFT		20
#define FIELD_MASK		(0xf << 20)
#define FIELD_FOO_PLEASE_NO	BIT(20)		/* Don't do this */
#define FIELD_FOO		(1 << 20)	/* This is consistent */
#define FIELD_BAR		(2 << 20)
#define FIELD_BAZ		(3 << 20)


BR,
Jani.

-- 
Jani Nikula, Intel Open Source Graphics Center
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Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
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  reply	other threads:[~2018-06-13  8:08 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-06-11 22:26 [CI 1/2] drm/i915/icl: Add allowed DP rates for Icelake Paulo Zanoni
2018-06-11 22:26 ` [CI 2/2] drm/i915/dp: Add support for HBR3 and TPS4 during link training Paulo Zanoni
2018-06-11 22:35 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,1/2] drm/i915/icl: Add allowed DP rates for Icelake Patchwork
2018-06-12  0:20   ` Paulo Zanoni
2018-06-12  8:46     ` Jani Nikula
2018-06-12 21:52       ` Rodrigo Vivi
2018-06-13  8:07         ` Jani Nikula [this message]
2018-06-13 16:59           ` Paulo Zanoni
2018-06-11 22:55 ` ✓ Fi.CI.BAT: success " Patchwork
2018-06-12  4:50 ` ✓ Fi.CI.IGT: " Patchwork
2018-06-12 12:15 ` [CI 1/2] " Ville Syrjälä
2018-06-12 18:37   ` Manasi Navare
2018-06-13 19:42     ` Paulo Zanoni
2018-06-13 20:15       ` Manasi Navare
2018-06-13 20:31         ` Paulo Zanoni

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