[Qemu-arm] [PATCH v5 12/13] target/arm: Mark PMINTENSET accesses as possibly doing IO

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From: Aaron Lindsay <alindsay@codeaurora.org>
To: qemu-arm@nongnu.org, Peter Maydell <peter.maydell@linaro.org>,
	Alistair Francis <alistair.francis@xilinx.com>,
	Wei Huang <wei@redhat.com>,
	Peter Crosthwaite <crosthwaite.peter@gmail.com>
Cc: Aaron Lindsay <alindsay@codeaurora.org>,
	Aaron Lindsay <aclindsa@gmail.com>,
	Michael Spradling <mspradli@codeaurora.org>,
	qemu-devel@nongnu.org, Digant Desai <digantd@codeaurora.org>
Subject: [Qemu-arm] [PATCH v5 12/13] target/arm: Mark PMINTENSET accesses as possibly doing IO
Date: Fri, 22 Jun 2018 16:32:26 -0400	[thread overview]
Message-ID: <1529699547-17044-13-git-send-email-alindsay@codeaurora.org> (raw)
In-Reply-To: <1529699547-17044-1-git-send-email-alindsay@codeaurora.org>

This makes it match its AArch64 equivalent, PMINTENSET_EL1

Signed-off-by: Aaron Lindsay <alindsay@codeaurora.org>
---
 target/arm/helper.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index 96667e6..38fb6a2 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -1763,7 +1763,7 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
       .writefn = pmuserenr_write, .raw_writefn = raw_write },
     { .name = "PMINTENSET", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 1,
       .access = PL1_RW, .accessfn = access_tpm,
-      .type = ARM_CP_ALIAS,
+      .type = ARM_CP_ALIAS | ARM_CP_IO,
       .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pminten),
       .resetvalue = 0,
       .writefn = pmintenset_write, .raw_writefn = raw_write },
-- 
Qualcomm Datacenter Technologies as an affiliate of Qualcomm Technologies, Inc.
Qualcomm Technologies, Inc. is a member of the
Code Aurora Forum, a Linux Foundation Collaborative Project.

WARNING: multiple messages have this Message-ID (diff)

From: Aaron Lindsay <alindsay@codeaurora.org>
To: qemu-arm@nongnu.org, Peter Maydell <peter.maydell@linaro.org>,
	Alistair Francis <alistair.francis@xilinx.com>,
	Wei Huang <wei@redhat.com>,
	Peter Crosthwaite <crosthwaite.peter@gmail.com>
Cc: qemu-devel@nongnu.org,
	Michael Spradling <mspradli@codeaurora.org>,
	Digant Desai <digantd@codeaurora.org>,
	Aaron Lindsay <aclindsa@gmail.com>,
	Aaron Lindsay <alindsay@codeaurora.org>
Subject: [Qemu-devel] [PATCH v5 12/13] target/arm: Mark PMINTENSET accesses as possibly doing IO
Date: Fri, 22 Jun 2018 16:32:26 -0400	[thread overview]
Message-ID: <1529699547-17044-13-git-send-email-alindsay@codeaurora.org> (raw)
In-Reply-To: <1529699547-17044-1-git-send-email-alindsay@codeaurora.org>

This makes it match its AArch64 equivalent, PMINTENSET_EL1

Signed-off-by: Aaron Lindsay <alindsay@codeaurora.org>
---
 target/arm/helper.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index 96667e6..38fb6a2 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -1763,7 +1763,7 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
       .writefn = pmuserenr_write, .raw_writefn = raw_write },
     { .name = "PMINTENSET", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 1,
       .access = PL1_RW, .accessfn = access_tpm,
-      .type = ARM_CP_ALIAS,
+      .type = ARM_CP_ALIAS | ARM_CP_IO,
       .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pminten),
       .resetvalue = 0,
       .writefn = pmintenset_write, .raw_writefn = raw_write },
-- 
Qualcomm Datacenter Technologies as an affiliate of Qualcomm Technologies, Inc.
Qualcomm Technologies, Inc. is a member of the
Code Aurora Forum, a Linux Foundation Collaborative Project.

next prev parent reply	other threads:[~2018-06-22 20:36 UTC|newest]

Thread overview: 64+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-06-22 20:32 [Qemu-arm] [PATCH v5 00/13] More fully implement ARM PMUv3 Aaron Lindsay
2018-06-22 20:32 ` [Qemu-devel] " Aaron Lindsay
2018-06-22 20:32 ` [Qemu-arm] [PATCH v5 01/13] target/arm: Reorganize PMCCNTR accesses Aaron Lindsay
2018-06-22 20:32   ` [Qemu-devel] " Aaron Lindsay
2018-06-28 16:40   ` [Qemu-arm] " Peter Maydell
2018-06-28 16:40     ` [Qemu-devel] " Peter Maydell
2018-08-28 20:03     ` [Qemu-arm] " Aaron Lindsay
2018-08-28 20:03       ` [Qemu-devel] " Aaron Lindsay
2018-09-25 15:18       ` Peter Maydell
2018-09-26 15:22         ` [Qemu-arm] " Aaron Lindsay
2018-06-22 20:32 ` [Qemu-arm] [PATCH v5 02/13] target/arm: Filter cycle counter based on PMCCFILTR_EL0 Aaron Lindsay
2018-06-22 20:32   ` [Qemu-devel] " Aaron Lindsay
2018-07-17 15:49   ` [Qemu-arm] " Peter Maydell
2018-07-17 15:49     ` [Qemu-devel] " Peter Maydell
2018-06-22 20:32 ` [Qemu-arm] [PATCH v5 03/13] target/arm: Allow AArch32 access for PMCCFILTR Aaron Lindsay
2018-06-22 20:32   ` [Qemu-devel] " Aaron Lindsay
2018-06-28 16:30   ` [Qemu-arm] " Peter Maydell
2018-06-28 16:30     ` [Qemu-devel] " Peter Maydell
2018-06-22 20:32 ` [Qemu-arm] [PATCH v5 04/13] target/arm: Add ARM_FEATURE_V7VE for v7 Virtualization Extensions Aaron Lindsay
2018-06-22 20:32   ` [Qemu-devel] " Aaron Lindsay
2018-06-28 16:20   ` [Qemu-arm] " Peter Maydell
2018-06-28 16:20     ` [Qemu-devel] " Peter Maydell
2018-06-22 20:32 ` [Qemu-arm] [PATCH v5 05/13] target/arm: Remove redundant DIV detection for KVM Aaron Lindsay
2018-06-22 20:32   ` [Qemu-devel] " Aaron Lindsay
2018-06-28 16:21   ` [Qemu-arm] " Peter Maydell
2018-06-28 16:21     ` [Qemu-devel] " Peter Maydell
2018-06-22 20:32 ` [Qemu-arm] [PATCH v5 06/13] target/arm: Implement PMOVSSET Aaron Lindsay
2018-06-22 20:32   ` [Qemu-devel] " Aaron Lindsay
2018-06-28 16:23   ` [Qemu-arm] " Peter Maydell
2018-06-28 16:23     ` [Qemu-devel] " Peter Maydell
2018-08-28 20:29     ` Aaron Lindsay
2018-08-28 20:29       ` Aaron Lindsay
2018-06-22 20:32 ` [Qemu-devel] [PATCH v5 07/13] target/arm: Add array for supported PMU events, generate PMCEID[01] Aaron Lindsay
2018-06-22 20:32   ` Aaron Lindsay
2018-07-17 16:06   ` [Qemu-arm] " Peter Maydell
2018-07-17 16:06     ` [Qemu-devel] " Peter Maydell
2018-08-29 15:18     ` [Qemu-arm] " Aaron Lindsay
2018-08-29 15:18       ` [Qemu-devel] " Aaron Lindsay
2018-06-22 20:32 ` [Qemu-arm] [PATCH v5 08/13] target/arm: Finish implementation of PM[X]EVCNTR and PM[X]EVTYPER Aaron Lindsay
2018-06-22 20:32   ` [Qemu-devel] " Aaron Lindsay
2018-07-17 16:17   ` [Qemu-arm] " Peter Maydell
2018-07-17 16:17     ` [Qemu-devel] " Peter Maydell
2018-08-29 15:31     ` [Qemu-arm] " Aaron Lindsay
2018-08-29 15:31       ` [Qemu-devel] " Aaron Lindsay
2018-06-22 20:32 ` [Qemu-arm] [PATCH v5 09/13] target/arm: PMU: Add instruction and cycle events Aaron Lindsay
2018-06-22 20:32   ` [Qemu-devel] " Aaron Lindsay
2018-07-17 16:11   ` [Qemu-arm] " Peter Maydell
2018-07-17 16:11     ` [Qemu-devel] " Peter Maydell
2018-06-22 20:32 ` [Qemu-arm] [PATCH v5 10/13] target/arm: PMU: Set PMCR.N to 4 Aaron Lindsay
2018-06-22 20:32   ` [Qemu-devel] " Aaron Lindsay
2018-06-22 20:32 ` [Qemu-arm] [PATCH v5 11/13] target/arm: Implement PMSWINC Aaron Lindsay
2018-06-22 20:32   ` [Qemu-devel] " Aaron Lindsay
2018-06-22 20:32 ` Aaron Lindsay [this message]
2018-06-22 20:32   ` [Qemu-devel] [PATCH v5 12/13] target/arm: Mark PMINTENSET accesses as possibly doing IO Aaron Lindsay
2018-06-28 16:25   ` [Qemu-arm] " Peter Maydell
2018-06-28 16:25     ` [Qemu-devel] " Peter Maydell
2018-08-27 14:48     ` Aaron Lindsay
2018-08-27 14:48       ` Aaron Lindsay
2018-06-22 20:32 ` [Qemu-arm] [PATCH v5 13/13] target/arm: Send interrupts on PMU counter overflow Aaron Lindsay
2018-06-22 20:32   ` [Qemu-devel] " Aaron Lindsay
2018-07-17 16:28   ` [Qemu-arm] " Peter Maydell
2018-07-17 16:28     ` [Qemu-devel] " Peter Maydell
2018-06-28 16:42 ` [Qemu-arm] [PATCH v5 00/13] More fully implement ARM PMUv3 Peter Maydell
2018-06-28 16:42   ` [Qemu-devel] " Peter Maydell

find likely ancestor, descendant, or conflicting patches for this message:
( dfblob:96667e6 dfblob:38fb6a2 dfblob:96667e6 dfblob:38fb6a2 )
 OR (
bs:"[Qemu-devel] [PATCH v5 12/13] target/arm: Mark PMINTENSET accesses as possibly doing IO" )
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