From: jbrunet@baylibre.com (Jerome Brunet)
To: linus-amlogic@lists.infradead.org
Subject: [PATCH 2/3] clk: meson: clk-pll: remove od parameters
Date: Thu, 19 Jul 2018 10:45:37 +0200 [thread overview]
Message-ID: <1531989937.26720.22.camel@baylibre.com> (raw)
In-Reply-To: <fa95a61b-3fde-1401-e2bc-f3465e5f4417@baylibre.com>
On Thu, 2018-07-19 at 10:42 +0200, Neil Armstrong wrote:
> > +static struct clk_regmap gxl_hdmi_pll_od = {
> > + .data = &(struct clk_regmap_div_data){
> > + .offset = HHI_HDMI_PLL_CNTL + 8,
> > + .shift = 16,
> > + .width = 2,
> > + .flags = CLK_DIVIDER_POWER_OF_TWO,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "hdmi_pll_od",
> > + .ops = &clk_regmap_divider_ro_ops,
> > + .parent_names = (const char *[]){ "hdmi_pll_dco" },
> > + .num_parents = 1,
> > + .flags = CLK_GET_RATE_NOCACHE,
> > + },
> > +};
>
> In my code, the GXL OD1 is at bit 21
>
> > +
> > +static struct clk_regmap gxl_hdmi_pll_od2 = {
> > + .data = &(struct clk_regmap_div_data){
> > + .offset = HHI_HDMI_PLL_CNTL + 8,
> > + .shift = 22,
> > + .width = 2,
> > + .flags = CLK_DIVIDER_POWER_OF_TWO,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "hdmi_pll_od2",
> > + .ops = &clk_regmap_divider_ro_ops,
> > + .parent_names = (const char *[]){ "hdmi_pll_od" },
> > + .num_parents = 1,
> > + .flags = CLK_GET_RATE_NOCACHE,
> > + },
> > +};
>
>
> In my code, the GXL OD3 is at bit 23
>
> > +
> > static struct clk_regmap gxl_hdmi_pll = {
> > - .data = &(struct meson_clk_pll_data){
> > - .en = {
> > - .reg_off = HHI_HDMI_PLL_CNTL,
> > - .shift = 30,
> > - .width = 1,
> > - },
> > - .m = {
> > - .reg_off = HHI_HDMI_PLL_CNTL,
> > - .shift = 0,
> > - .width = 9,
> > - },
> > - .n = {
> > - .reg_off = HHI_HDMI_PLL_CNTL,
> > - .shift = 9,
> > - .width = 5,
> > - },
> > - .frac = {
> > - /*
> > - * On gxl, there is a register shift due to
> > - * HHI_HDMI_PLL_CNTL1 which does not exist on gxbb,
> > - * so we compute the register offset based on the PLL
> > - * base to get it right
> > - */
> > - .reg_off = HHI_HDMI_PLL_CNTL + 4,
> > - .shift = 0,
> > - .width = 12,
> > - },
> > - .od = {
> > - .reg_off = HHI_HDMI_PLL_CNTL + 8,
> > - .shift = 21,
> > - .width = 2,
> > - },
> > - .od2 = {
> > - .reg_off = HHI_HDMI_PLL_CNTL + 8,
> > - .shift = 23,
> > - .width = 2,
> > - },
> > - .od3 = {
> > - .reg_off = HHI_HDMI_PLL_CNTL + 8,
> > - .shift = 19,
> > - .width = 2,
> > - },
> > - .l = {
> > - .reg_off = HHI_HDMI_PLL_CNTL,
> > - .shift = 31,
> > - .width = 1,
> > - },
> > - .rst = {
> > - .reg_off = HHI_HDMI_PLL_CNTL,
> > - .shift = 29,
> > - .width = 1,
> > - },
> > + .data = &(struct clk_regmap_div_data){
> > + .offset = HHI_HDMI_PLL_CNTL + 8,
> > + .shift = 18,
> > + .width = 2,
> > + .flags = CLK_DIVIDER_POWER_OF_TWO,
>
>
> In my code, the GXL OD3 is at bit 19
>
> It's only a copy/paste error, the original code had the correct shifts.
Absolutely. Good catch.
WARNING: multiple messages have this Message-ID (diff)
From: Jerome Brunet <jbrunet@baylibre.com>
To: Neil Armstrong <narmstrong@baylibre.com>
Cc: linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org,
linux-kernel@vger.kernel.org, Kevin Hilman <khilman@baylibre.com>,
Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Subject: Re: [PATCH 2/3] clk: meson: clk-pll: remove od parameters
Date: Thu, 19 Jul 2018 10:45:37 +0200 [thread overview]
Message-ID: <1531989937.26720.22.camel@baylibre.com> (raw)
In-Reply-To: <fa95a61b-3fde-1401-e2bc-f3465e5f4417@baylibre.com>
On Thu, 2018-07-19 at 10:42 +0200, Neil Armstrong wrote:
> > +static struct clk_regmap gxl_hdmi_pll_od = {
> > + .data = &(struct clk_regmap_div_data){
> > + .offset = HHI_HDMI_PLL_CNTL + 8,
> > + .shift = 16,
> > + .width = 2,
> > + .flags = CLK_DIVIDER_POWER_OF_TWO,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "hdmi_pll_od",
> > + .ops = &clk_regmap_divider_ro_ops,
> > + .parent_names = (const char *[]){ "hdmi_pll_dco" },
> > + .num_parents = 1,
> > + .flags = CLK_GET_RATE_NOCACHE,
> > + },
> > +};
>
> In my code, the GXL OD1 is at bit 21
>
> > +
> > +static struct clk_regmap gxl_hdmi_pll_od2 = {
> > + .data = &(struct clk_regmap_div_data){
> > + .offset = HHI_HDMI_PLL_CNTL + 8,
> > + .shift = 22,
> > + .width = 2,
> > + .flags = CLK_DIVIDER_POWER_OF_TWO,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "hdmi_pll_od2",
> > + .ops = &clk_regmap_divider_ro_ops,
> > + .parent_names = (const char *[]){ "hdmi_pll_od" },
> > + .num_parents = 1,
> > + .flags = CLK_GET_RATE_NOCACHE,
> > + },
> > +};
>
>
> In my code, the GXL OD3 is at bit 23
>
> > +
> > static struct clk_regmap gxl_hdmi_pll = {
> > - .data = &(struct meson_clk_pll_data){
> > - .en = {
> > - .reg_off = HHI_HDMI_PLL_CNTL,
> > - .shift = 30,
> > - .width = 1,
> > - },
> > - .m = {
> > - .reg_off = HHI_HDMI_PLL_CNTL,
> > - .shift = 0,
> > - .width = 9,
> > - },
> > - .n = {
> > - .reg_off = HHI_HDMI_PLL_CNTL,
> > - .shift = 9,
> > - .width = 5,
> > - },
> > - .frac = {
> > - /*
> > - * On gxl, there is a register shift due to
> > - * HHI_HDMI_PLL_CNTL1 which does not exist on gxbb,
> > - * so we compute the register offset based on the PLL
> > - * base to get it right
> > - */
> > - .reg_off = HHI_HDMI_PLL_CNTL + 4,
> > - .shift = 0,
> > - .width = 12,
> > - },
> > - .od = {
> > - .reg_off = HHI_HDMI_PLL_CNTL + 8,
> > - .shift = 21,
> > - .width = 2,
> > - },
> > - .od2 = {
> > - .reg_off = HHI_HDMI_PLL_CNTL + 8,
> > - .shift = 23,
> > - .width = 2,
> > - },
> > - .od3 = {
> > - .reg_off = HHI_HDMI_PLL_CNTL + 8,
> > - .shift = 19,
> > - .width = 2,
> > - },
> > - .l = {
> > - .reg_off = HHI_HDMI_PLL_CNTL,
> > - .shift = 31,
> > - .width = 1,
> > - },
> > - .rst = {
> > - .reg_off = HHI_HDMI_PLL_CNTL,
> > - .shift = 29,
> > - .width = 1,
> > - },
> > + .data = &(struct clk_regmap_div_data){
> > + .offset = HHI_HDMI_PLL_CNTL + 8,
> > + .shift = 18,
> > + .width = 2,
> > + .flags = CLK_DIVIDER_POWER_OF_TWO,
>
>
> In my code, the GXL OD3 is at bit 19
>
> It's only a copy/paste error, the original code had the correct shifts.
Absolutely. Good catch.
next prev parent reply other threads:[~2018-07-19 8:45 UTC|newest]
Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-07-17 9:56 [PATCH 0/3] clk: meson: clk-pll driver update Jerome Brunet
2018-07-17 9:56 ` Jerome Brunet
2018-07-17 9:56 ` [PATCH 1/3] clk: meson: clk-pll: add enable bit Jerome Brunet
2018-07-17 9:56 ` Jerome Brunet
2018-07-17 9:56 ` Jerome Brunet
2018-07-19 8:33 ` Neil Armstrong
2018-07-19 8:33 ` Neil Armstrong
2018-07-21 19:48 ` Martin Blumenstingl
2018-07-21 19:48 ` Martin Blumenstingl
2018-07-21 20:26 ` Jerome Brunet
2018-07-21 20:26 ` Jerome Brunet
2018-07-17 9:56 ` [PATCH 2/3] clk: meson: clk-pll: remove od parameters Jerome Brunet
2018-07-17 9:56 ` Jerome Brunet
2018-07-19 8:42 ` Neil Armstrong
2018-07-19 8:42 ` Neil Armstrong
2018-07-19 8:45 ` Jerome Brunet [this message]
2018-07-19 8:45 ` Jerome Brunet
2018-07-21 20:01 ` Martin Blumenstingl
2018-07-21 20:01 ` Martin Blumenstingl
2018-07-21 20:42 ` Jerome Brunet
2018-07-21 20:42 ` Jerome Brunet
2018-07-21 21:37 ` Martin Blumenstingl
2018-07-21 21:37 ` Martin Blumenstingl
2018-07-17 9:56 ` [PATCH 3/3] clk: meson: clk-pll: drop hard-coded rates from pll tables Jerome Brunet
2018-07-17 9:56 ` Jerome Brunet
2018-07-19 8:44 ` Neil Armstrong
2018-07-19 8:44 ` Neil Armstrong
2018-07-19 8:59 ` Jerome Brunet
2018-07-19 8:59 ` Jerome Brunet
2018-07-21 20:16 ` Martin Blumenstingl
2018-07-21 20:16 ` Martin Blumenstingl
2018-07-21 20:46 ` Jerome Brunet
2018-07-21 20:46 ` Jerome Brunet
2018-07-21 21:34 ` Martin Blumenstingl
2018-07-21 21:34 ` Martin Blumenstingl
2018-07-26 8:48 ` jbrunet at baylibre.com
2018-07-26 8:48 ` jbrunet
2018-07-21 20:17 ` [PATCH 0/3] clk: meson: clk-pll driver update Martin Blumenstingl
2018-07-21 20:17 ` Martin Blumenstingl
2018-07-21 20:48 ` Jerome Brunet
2018-07-21 20:48 ` Jerome Brunet
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