From: jbrunet@baylibre.com (Jerome Brunet)
To: linus-amlogic@lists.infradead.org
Subject: [PATCH 3/3] clk: meson: clk-pll: drop hard-coded rates from pll tables
Date: Sat, 21 Jul 2018 22:46:50 +0200 [thread overview]
Message-ID: <1532206010.26720.84.camel@baylibre.com> (raw)
In-Reply-To: <CAFBinCBc_cFD2ACiSHVuRrXaqSyDnkJb2rem1_k2jwved=QXVw@mail.gmail.com>
On Sat, 2018-07-21 at 22:16 +0200, Martin Blumenstingl wrote:
> > We could even add ranges instead of table when we know the PLL supports a well-known continuous dividers range.
>
> I had a look at the sys_pll settings on Meson8b, here's what
> Meson8/Meson8b/Meson8m2 support for sys_pll:
> - 50..74
> - 76
> - 78
> - 80
> - 82
> - 84
> - 86
> - 88
> - 90
> - 92
> - 94
> - 96
> - 98
Are those values with the same predivider (n) value ?
I suspect the ability of the DCO to lock might depends on its input rate and an
m range
So if n change, it might possible that the m range will be different.
... at least, that's my guess :)
>
> (I'm providing this info because it may help finding a decision
> whether ranges are good or not. I have no preference)
WARNING: multiple messages have this Message-ID (diff)
From: Jerome Brunet <jbrunet@baylibre.com>
To: Martin Blumenstingl <martin.blumenstingl@googlemail.com>,
Neil Armstrong <narmstrong@baylibre.com>
Cc: linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org,
linux-kernel@vger.kernel.org, khilman@baylibre.com
Subject: Re: [PATCH 3/3] clk: meson: clk-pll: drop hard-coded rates from pll tables
Date: Sat, 21 Jul 2018 22:46:50 +0200 [thread overview]
Message-ID: <1532206010.26720.84.camel@baylibre.com> (raw)
In-Reply-To: <CAFBinCBc_cFD2ACiSHVuRrXaqSyDnkJb2rem1_k2jwved=QXVw@mail.gmail.com>
On Sat, 2018-07-21 at 22:16 +0200, Martin Blumenstingl wrote:
> > We could even add ranges instead of table when we know the PLL supports a well-known continuous dividers range.
>
> I had a look at the sys_pll settings on Meson8b, here's what
> Meson8/Meson8b/Meson8m2 support for sys_pll:
> - 50..74
> - 76
> - 78
> - 80
> - 82
> - 84
> - 86
> - 88
> - 90
> - 92
> - 94
> - 96
> - 98
Are those values with the same predivider (n) value ?
I suspect the ability of the DCO to lock might depends on its input rate and an
m range
So if n change, it might possible that the m range will be different.
... at least, that's my guess :)
>
> (I'm providing this info because it may help finding a decision
> whether ranges are good or not. I have no preference)
next prev parent reply other threads:[~2018-07-21 20:46 UTC|newest]
Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-07-17 9:56 [PATCH 0/3] clk: meson: clk-pll driver update Jerome Brunet
2018-07-17 9:56 ` Jerome Brunet
2018-07-17 9:56 ` [PATCH 1/3] clk: meson: clk-pll: add enable bit Jerome Brunet
2018-07-17 9:56 ` Jerome Brunet
2018-07-17 9:56 ` Jerome Brunet
2018-07-19 8:33 ` Neil Armstrong
2018-07-19 8:33 ` Neil Armstrong
2018-07-21 19:48 ` Martin Blumenstingl
2018-07-21 19:48 ` Martin Blumenstingl
2018-07-21 20:26 ` Jerome Brunet
2018-07-21 20:26 ` Jerome Brunet
2018-07-17 9:56 ` [PATCH 2/3] clk: meson: clk-pll: remove od parameters Jerome Brunet
2018-07-17 9:56 ` Jerome Brunet
2018-07-19 8:42 ` Neil Armstrong
2018-07-19 8:42 ` Neil Armstrong
2018-07-19 8:45 ` Jerome Brunet
2018-07-19 8:45 ` Jerome Brunet
2018-07-21 20:01 ` Martin Blumenstingl
2018-07-21 20:01 ` Martin Blumenstingl
2018-07-21 20:42 ` Jerome Brunet
2018-07-21 20:42 ` Jerome Brunet
2018-07-21 21:37 ` Martin Blumenstingl
2018-07-21 21:37 ` Martin Blumenstingl
2018-07-17 9:56 ` [PATCH 3/3] clk: meson: clk-pll: drop hard-coded rates from pll tables Jerome Brunet
2018-07-17 9:56 ` Jerome Brunet
2018-07-19 8:44 ` Neil Armstrong
2018-07-19 8:44 ` Neil Armstrong
2018-07-19 8:59 ` Jerome Brunet
2018-07-19 8:59 ` Jerome Brunet
2018-07-21 20:16 ` Martin Blumenstingl
2018-07-21 20:16 ` Martin Blumenstingl
2018-07-21 20:46 ` Jerome Brunet [this message]
2018-07-21 20:46 ` Jerome Brunet
2018-07-21 21:34 ` Martin Blumenstingl
2018-07-21 21:34 ` Martin Blumenstingl
2018-07-26 8:48 ` jbrunet at baylibre.com
2018-07-26 8:48 ` jbrunet
2018-07-21 20:17 ` [PATCH 0/3] clk: meson: clk-pll driver update Martin Blumenstingl
2018-07-21 20:17 ` Martin Blumenstingl
2018-07-21 20:48 ` Jerome Brunet
2018-07-21 20:48 ` Jerome Brunet
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