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From: Prasad Sodagudi <psodagud@codeaurora.org>
To: will.deacon@arm.com, mingo@redhat.com, catalin.marinas@arm.com,
	linux-arm-kernel@lists.infradead.org, peterz@infradead.org
Cc: psodagud@codeaurora.org, linux-kernel@vger.kernel.org
Subject: [PATCH] perf: Change PMCR write to read-modify-write
Date: Wed, 20 Mar 2019 19:07:46 -0700	[thread overview]
Message-ID: <1553134066-20272-1-git-send-email-psodagud@codeaurora.org> (raw)

Preserves the bitfields of PMCR_EL0(AArch64) during PMU reset.
Reset routine should write a 1 to PMCR.C and PMCR.P fields only
to reset the counters. Other fields should not be changed
as they could be set before PMU initialization and their
value must be preserved even after reset.

Signed-off-by: Prasad Sodagudi <psodagud@codeaurora.org>
---
 arch/arm64/kernel/perf_event.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c
index 4addb38..0c1afdd 100644
--- a/arch/arm64/kernel/perf_event.c
+++ b/arch/arm64/kernel/perf_event.c
@@ -868,8 +868,8 @@ static void armv8pmu_reset(void *info)
 	 * Initialize & Reset PMNC. Request overflow interrupt for
 	 * 64 bit cycle counter but cheat in armv8pmu_write_counter().
 	 */
-	armv8pmu_pmcr_write(ARMV8_PMU_PMCR_P | ARMV8_PMU_PMCR_C |
-			    ARMV8_PMU_PMCR_LC);
+	armv8pmu_pmcr_write(armv8pmu_pmcr_read() | ARMV8_PMU_PMCR_P |
+			ARMV8_PMU_PMCR_C | ARMV8_PMU_PMCR_LC);
 }
 
 static int __armv8_pmuv3_map_event(struct perf_event *event,
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,\na Linux Foundation Collaborative Project


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WARNING: multiple messages have this Message-ID (diff)
From: Prasad Sodagudi <psodagud@codeaurora.org>
To: will.deacon@arm.com, mingo@redhat.com, catalin.marinas@arm.com,
	linux-arm-kernel@lists.infradead.org, peterz@infradead.org
Cc: linux-kernel@vger.kernel.org, psodagud@codeaurora.org
Subject: [PATCH] perf: Change PMCR write to read-modify-write
Date: Wed, 20 Mar 2019 19:07:46 -0700	[thread overview]
Message-ID: <1553134066-20272-1-git-send-email-psodagud@codeaurora.org> (raw)

Preserves the bitfields of PMCR_EL0(AArch64) during PMU reset.
Reset routine should write a 1 to PMCR.C and PMCR.P fields only
to reset the counters. Other fields should not be changed
as they could be set before PMU initialization and their
value must be preserved even after reset.

Signed-off-by: Prasad Sodagudi <psodagud@codeaurora.org>
---
 arch/arm64/kernel/perf_event.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c
index 4addb38..0c1afdd 100644
--- a/arch/arm64/kernel/perf_event.c
+++ b/arch/arm64/kernel/perf_event.c
@@ -868,8 +868,8 @@ static void armv8pmu_reset(void *info)
 	 * Initialize & Reset PMNC. Request overflow interrupt for
 	 * 64 bit cycle counter but cheat in armv8pmu_write_counter().
 	 */
-	armv8pmu_pmcr_write(ARMV8_PMU_PMCR_P | ARMV8_PMU_PMCR_C |
-			    ARMV8_PMU_PMCR_LC);
+	armv8pmu_pmcr_write(armv8pmu_pmcr_read() | ARMV8_PMU_PMCR_P |
+			ARMV8_PMU_PMCR_C | ARMV8_PMU_PMCR_LC);
 }
 
 static int __armv8_pmuv3_map_event(struct perf_event *event,
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,\na Linux Foundation Collaborative Project


             reply	other threads:[~2019-03-21  2:08 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-03-21  2:07 Prasad Sodagudi [this message]
2019-03-21  2:07 ` [PATCH] perf: Change PMCR write to read-modify-write Prasad Sodagudi
2019-03-21 13:34 ` Julien Thierry
2019-03-21 13:34   ` Julien Thierry
2019-03-21 20:02   ` Sodagudi Prasad
2019-03-21 20:02     ` Sodagudi Prasad
2019-03-22  8:31     ` Julien Thierry
2019-03-22  8:31       ` Julien Thierry
2019-04-01  8:17     ` Mark Rutland
2019-04-01  8:17       ` Mark Rutland
2019-04-02 16:50 ` Will Deacon
2019-04-02 16:50   ` Will Deacon

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