All of lore.kernel.org
 help / color / mirror / Atom feed
From: Julien Thierry <julien.thierry@arm.com>
To: Prasad Sodagudi <psodagud@codeaurora.org>,
	will.deacon@arm.com, mingo@redhat.com, catalin.marinas@arm.com,
	linux-arm-kernel@lists.infradead.org, peterz@infradead.org
Cc: linux-kernel@vger.kernel.org
Subject: Re: [PATCH] perf: Change PMCR write to read-modify-write
Date: Thu, 21 Mar 2019 13:34:55 +0000	[thread overview]
Message-ID: <bb4ece56-ac42-05f2-8475-38c49539999d@arm.com> (raw)
In-Reply-To: <1553134066-20272-1-git-send-email-psodagud@codeaurora.org>

Hi Prasad,

On 21/03/2019 02:07, Prasad Sodagudi wrote:
> Preserves the bitfields of PMCR_EL0(AArch64) during PMU reset.
> Reset routine should write a 1 to PMCR.C and PMCR.P fields only
> to reset the counters. Other fields should not be changed
> as they could be set before PMU initialization and their
> value must be preserved even after reset.
> 

Are there any particular bit you are concerned about? Apart from the RO
ones and the Res0 ones (to which we are already writing 0), I see:

DP -> irrelevant for non-secure
X -> This one is the only potentially interesting, however it resets to
an architecturally unknown value, so unless we know for a fact it was
set before hand, we probably want to clear it
D -> ignored when we have LC set (and we do)
E -> Since this is the function we use to reset the PMU on the current
CPU, we probably want to set this bit to 0 regardless of its previous value

So, is there any issue this patch is solving?

Thanks,

> Signed-off-by: Prasad Sodagudi <psodagud@codeaurora.org>
> ---
>  arch/arm64/kernel/perf_event.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c
> index 4addb38..0c1afdd 100644
> --- a/arch/arm64/kernel/perf_event.c
> +++ b/arch/arm64/kernel/perf_event.c
> @@ -868,8 +868,8 @@ static void armv8pmu_reset(void *info)
>  	 * Initialize & Reset PMNC. Request overflow interrupt for
>  	 * 64 bit cycle counter but cheat in armv8pmu_write_counter().
>  	 */
> -	armv8pmu_pmcr_write(ARMV8_PMU_PMCR_P | ARMV8_PMU_PMCR_C |
> -			    ARMV8_PMU_PMCR_LC);
> +	armv8pmu_pmcr_write(armv8pmu_pmcr_read() | ARMV8_PMU_PMCR_P |
> +			ARMV8_PMU_PMCR_C | ARMV8_PMU_PMCR_LC);
>  }
>  
>  static int __armv8_pmuv3_map_event(struct perf_event *event,
> 

-- 
Julien Thierry

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

WARNING: multiple messages have this Message-ID (diff)
From: Julien Thierry <julien.thierry@arm.com>
To: Prasad Sodagudi <psodagud@codeaurora.org>,
	will.deacon@arm.com, mingo@redhat.com, catalin.marinas@arm.com,
	linux-arm-kernel@lists.infradead.org, peterz@infradead.org
Cc: linux-kernel@vger.kernel.org
Subject: Re: [PATCH] perf: Change PMCR write to read-modify-write
Date: Thu, 21 Mar 2019 13:34:55 +0000	[thread overview]
Message-ID: <bb4ece56-ac42-05f2-8475-38c49539999d@arm.com> (raw)
In-Reply-To: <1553134066-20272-1-git-send-email-psodagud@codeaurora.org>

Hi Prasad,

On 21/03/2019 02:07, Prasad Sodagudi wrote:
> Preserves the bitfields of PMCR_EL0(AArch64) during PMU reset.
> Reset routine should write a 1 to PMCR.C and PMCR.P fields only
> to reset the counters. Other fields should not be changed
> as they could be set before PMU initialization and their
> value must be preserved even after reset.
> 

Are there any particular bit you are concerned about? Apart from the RO
ones and the Res0 ones (to which we are already writing 0), I see:

DP -> irrelevant for non-secure
X -> This one is the only potentially interesting, however it resets to
an architecturally unknown value, so unless we know for a fact it was
set before hand, we probably want to clear it
D -> ignored when we have LC set (and we do)
E -> Since this is the function we use to reset the PMU on the current
CPU, we probably want to set this bit to 0 regardless of its previous value

So, is there any issue this patch is solving?

Thanks,

> Signed-off-by: Prasad Sodagudi <psodagud@codeaurora.org>
> ---
>  arch/arm64/kernel/perf_event.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c
> index 4addb38..0c1afdd 100644
> --- a/arch/arm64/kernel/perf_event.c
> +++ b/arch/arm64/kernel/perf_event.c
> @@ -868,8 +868,8 @@ static void armv8pmu_reset(void *info)
>  	 * Initialize & Reset PMNC. Request overflow interrupt for
>  	 * 64 bit cycle counter but cheat in armv8pmu_write_counter().
>  	 */
> -	armv8pmu_pmcr_write(ARMV8_PMU_PMCR_P | ARMV8_PMU_PMCR_C |
> -			    ARMV8_PMU_PMCR_LC);
> +	armv8pmu_pmcr_write(armv8pmu_pmcr_read() | ARMV8_PMU_PMCR_P |
> +			ARMV8_PMU_PMCR_C | ARMV8_PMU_PMCR_LC);
>  }
>  
>  static int __armv8_pmuv3_map_event(struct perf_event *event,
> 

-- 
Julien Thierry

  reply	other threads:[~2019-03-21 13:35 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-03-21  2:07 [PATCH] perf: Change PMCR write to read-modify-write Prasad Sodagudi
2019-03-21  2:07 ` Prasad Sodagudi
2019-03-21 13:34 ` Julien Thierry [this message]
2019-03-21 13:34   ` Julien Thierry
2019-03-21 20:02   ` Sodagudi Prasad
2019-03-21 20:02     ` Sodagudi Prasad
2019-03-22  8:31     ` Julien Thierry
2019-03-22  8:31       ` Julien Thierry
2019-04-01  8:17     ` Mark Rutland
2019-04-01  8:17       ` Mark Rutland
2019-04-02 16:50 ` Will Deacon
2019-04-02 16:50   ` Will Deacon

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=bb4ece56-ac42-05f2-8475-38c49539999d@arm.com \
    --to=julien.thierry@arm.com \
    --cc=catalin.marinas@arm.com \
    --cc=linux-arm-kernel@lists.infradead.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=mingo@redhat.com \
    --cc=peterz@infradead.org \
    --cc=psodagud@codeaurora.org \
    --cc=will.deacon@arm.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.