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From: Jacob Pan <jacob.jun.pan@linux.intel.com>
To: iommu@lists.linux-foundation.org,
	LKML <linux-kernel@vger.kernel.org>,
	"Lu Baolu" <baolu.lu@linux.intel.com>,
	Joerg Roedel <joro@8bytes.org>,
	David Woodhouse <dwmw2@infradead.org>
Cc: "Tian, Kevin" <kevin.tian@intel.com>, Raj Ashok <ashok.raj@intel.com>
Subject: [PATCH v4 1/7] iommu/vt-d: Enforce PASID devTLB field mask
Date: Mon,  6 Jul 2020 17:12:48 -0700	[thread overview]
Message-ID: <1594080774-33413-2-git-send-email-jacob.jun.pan@linux.intel.com> (raw)
In-Reply-To: <1594080774-33413-1-git-send-email-jacob.jun.pan@linux.intel.com>

From: Liu Yi L <yi.l.liu@intel.com>

Set proper masks to avoid invalid input spillover to reserved bits.

Acked-by: Lu Baolu <baolu.lu@linux.intel.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Liu Yi L <yi.l.liu@intel.com>
Signed-off-by: Jacob Pan <jacob.jun.pan@linux.intel.com>
---
 include/linux/intel-iommu.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/include/linux/intel-iommu.h b/include/linux/intel-iommu.h
index 4100bd224f5c..729386ca8122 100644
--- a/include/linux/intel-iommu.h
+++ b/include/linux/intel-iommu.h
@@ -380,8 +380,8 @@ enum {
 
 #define QI_DEV_EIOTLB_ADDR(a)	((u64)(a) & VTD_PAGE_MASK)
 #define QI_DEV_EIOTLB_SIZE	(((u64)1) << 11)
-#define QI_DEV_EIOTLB_GLOB(g)	((u64)g)
-#define QI_DEV_EIOTLB_PASID(p)	(((u64)p) << 32)
+#define QI_DEV_EIOTLB_GLOB(g)	((u64)(g) & 0x1)
+#define QI_DEV_EIOTLB_PASID(p)	((u64)((p) & 0xfffff) << 32)
 #define QI_DEV_EIOTLB_SID(sid)	((u64)((sid) & 0xffff) << 16)
 #define QI_DEV_EIOTLB_QDEP(qd)	((u64)((qd) & 0x1f) << 4)
 #define QI_DEV_EIOTLB_PFSID(pfsid) (((u64)(pfsid & 0xf) << 12) | \
-- 
2.7.4

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WARNING: multiple messages have this Message-ID (diff)
From: Jacob Pan <jacob.jun.pan@linux.intel.com>
To: iommu@lists.linux-foundation.org,
	LKML <linux-kernel@vger.kernel.org>,
	"Lu Baolu" <baolu.lu@linux.intel.com>,
	Joerg Roedel <joro@8bytes.org>,
	David Woodhouse <dwmw2@infradead.org>
Cc: Yi Liu <yi.l.liu@intel.com>, "Tian, Kevin" <kevin.tian@intel.com>,
	Raj Ashok <ashok.raj@intel.com>,
	Eric Auger <eric.auger@redhat.com>,
	Jacob Pan <jacob.jun.pan@linux.intel.com>
Subject: [PATCH v4 1/7] iommu/vt-d: Enforce PASID devTLB field mask
Date: Mon,  6 Jul 2020 17:12:48 -0700	[thread overview]
Message-ID: <1594080774-33413-2-git-send-email-jacob.jun.pan@linux.intel.com> (raw)
In-Reply-To: <1594080774-33413-1-git-send-email-jacob.jun.pan@linux.intel.com>

From: Liu Yi L <yi.l.liu@intel.com>

Set proper masks to avoid invalid input spillover to reserved bits.

Acked-by: Lu Baolu <baolu.lu@linux.intel.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Liu Yi L <yi.l.liu@intel.com>
Signed-off-by: Jacob Pan <jacob.jun.pan@linux.intel.com>
---
 include/linux/intel-iommu.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/include/linux/intel-iommu.h b/include/linux/intel-iommu.h
index 4100bd224f5c..729386ca8122 100644
--- a/include/linux/intel-iommu.h
+++ b/include/linux/intel-iommu.h
@@ -380,8 +380,8 @@ enum {
 
 #define QI_DEV_EIOTLB_ADDR(a)	((u64)(a) & VTD_PAGE_MASK)
 #define QI_DEV_EIOTLB_SIZE	(((u64)1) << 11)
-#define QI_DEV_EIOTLB_GLOB(g)	((u64)g)
-#define QI_DEV_EIOTLB_PASID(p)	(((u64)p) << 32)
+#define QI_DEV_EIOTLB_GLOB(g)	((u64)(g) & 0x1)
+#define QI_DEV_EIOTLB_PASID(p)	((u64)((p) & 0xfffff) << 32)
 #define QI_DEV_EIOTLB_SID(sid)	((u64)((sid) & 0xffff) << 16)
 #define QI_DEV_EIOTLB_QDEP(qd)	((u64)((qd) & 0x1f) << 4)
 #define QI_DEV_EIOTLB_PFSID(pfsid) (((u64)(pfsid & 0xf) << 12) | \
-- 
2.7.4


  reply	other threads:[~2020-07-07  0:06 UTC|newest]

Thread overview: 34+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-07-07  0:12 [PATCH v4 0/7] iommu/vt-d: Misc tweaks and fixes for vSVA Jacob Pan
2020-07-07  0:12 ` Jacob Pan
2020-07-07  0:12 ` Jacob Pan [this message]
2020-07-07  0:12   ` [PATCH v4 1/7] iommu/vt-d: Enforce PASID devTLB field mask Jacob Pan
2020-07-07  0:12 ` [PATCH v4 2/7] iommu/vt-d: Remove global page support in devTLB flush Jacob Pan
2020-07-07  0:12   ` Jacob Pan
2020-07-07  0:12 ` [PATCH v4 3/7] iommu/vt-d: Fix PASID devTLB invalidation Jacob Pan
2020-07-07  0:12   ` Jacob Pan
2020-07-16  7:52   ` Auger Eric
2020-07-16  7:52     ` Auger Eric
2020-07-07  0:12 ` [PATCH v4 4/7] iommu/vt-d: Handle non-page aligned address Jacob Pan
2020-07-07  0:12   ` Jacob Pan
2020-07-07 13:32   ` kernel test robot
2020-07-07 13:32     ` kernel test robot
2020-07-07 13:32     ` kernel test robot
2020-07-09  1:10     ` [kbuild-all] " Li, Philip
2020-07-09  1:10       ` Li, Philip
2020-07-09  1:10       ` Li, Philip
2020-07-16  7:51   ` Auger Eric
2020-07-16  7:51     ` Auger Eric
2020-07-21 16:50   ` Jacob Pan
2020-07-21 16:50     ` Jacob Pan
2020-07-22  1:01     ` Lu Baolu
2020-07-22  1:01       ` Lu Baolu
2020-07-22 18:20       ` Jacob Pan
2020-07-22 18:20         ` Jacob Pan
2020-07-07  0:12 ` [PATCH v4 5/7] iommu/vt-d: Fix devTLB flush for vSVA Jacob Pan
2020-07-07  0:12   ` Jacob Pan
2020-07-07  0:12 ` [PATCH v4 6/7] iommu/vt-d: Warn on out-of-range invalidation address Jacob Pan
2020-07-07  0:12   ` Jacob Pan
2020-07-16  8:40   ` Auger Eric
2020-07-16  8:40     ` Auger Eric
2020-07-07  0:12 ` [PATCH v4 7/7] iommu/vt-d: Disable multiple GPASID-dev bind Jacob Pan
2020-07-07  0:12   ` Jacob Pan

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