* [PATCH v3 0/5] drm/i915/bw: Split bandwidth params into platform- and display-IP-specific structs
@ 2026-05-14 19:19 Gustavo Sousa
2026-05-14 19:19 ` [PATCH v3 1/5] drm/i915/bw: Don't call intel_dram_info() too early Gustavo Sousa
` (8 more replies)
0 siblings, 9 replies; 15+ messages in thread
From: Gustavo Sousa @ 2026-05-14 19:19 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: Gustavo Sousa, Jani Nikula, Matt Roper, Rodrigo Vivi
Some of the parameters of used in display bandwidth calculations are
tied to the platform and are orthogonal to the display IP. After talking
with the hardware team, we now have the information (and Bspec has been
updated) that the members deprogbwlimit and derating of struct
intel_sa_info are such platform-specific ones.
With that, we are now able to make the driver code more aligned with the
hardware by splitting structs intel_sa_info into two different structs:
one that is platform-specific and another that is display-IP-specific.
That change also allows us to simplify how we select the parameters for
the calculation.
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
Changes in v3:
- Incorporated review feedback; see each individual patch for details.
- Link to v2: https://patch.msgid.link/20260511-separate-platform-from-diplay-ip-specific-bw-params-v2-0-e762cb8662da@intel.com
Changes in v2:
- Incorporated review feedback; see each individual patch for details.
- Link to v1: https://patch.msgid.link/20260408-separate-platform-from-diplay-ip-specific-bw-params-v1-0-23c53afa7db0@intel.com
---
Gustavo Sousa (5):
drm/i915/bw: Don't call intel_dram_info() too early
drm/i915/bw: Extract platform-specific parameters
drm/i915/bw: Deduplicate intel_sa_info instances
drm/i915/bw: Rename struct intel_sa_info to intel_display_bw_params
drm/i915/bw: Extract get_display_bw_params()
drivers/gpu/drm/i915/display/intel_bw.c | 218 +++++++++++++++++++++-----------
1 file changed, 141 insertions(+), 77 deletions(-)
---
base-commit: dee34cfbffbfe2196a9332f966b006cd2e54e976
change-id: 20260408-separate-platform-from-diplay-ip-specific-bw-params-65bfba0603be
Best regards,
--
Gustavo Sousa <gustavo.sousa@intel.com>
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v3 1/5] drm/i915/bw: Don't call intel_dram_info() too early
2026-05-14 19:19 [PATCH v3 0/5] drm/i915/bw: Split bandwidth params into platform- and display-IP-specific structs Gustavo Sousa
@ 2026-05-14 19:19 ` Gustavo Sousa
2026-05-15 8:26 ` Jani Nikula
2026-05-14 19:19 ` [PATCH v3 2/5] drm/i915/bw: Extract platform-specific parameters Gustavo Sousa
` (7 subsequent siblings)
8 siblings, 1 reply; 15+ messages in thread
From: Gustavo Sousa @ 2026-05-14 19:19 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: Gustavo Sousa, Jani Nikula
If we end-up bailing early from intel_bw_init_hw() due to
!HAS_DISPLAY(display), the call to intel_dram_info() to initialize
dram_info will be meaningless. Move the call to be done after that
check.
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
drivers/gpu/drm/i915/display/intel_bw.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index 9c3a9bbb49f6..7eef693b51ad 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -791,11 +791,13 @@ static unsigned int icl_qgv_bw(struct intel_display *display,
void intel_bw_init_hw(struct intel_display *display)
{
- const struct dram_info *dram_info = intel_dram_info(display);
+ const struct dram_info *dram_info;
if (!HAS_DISPLAY(display))
return;
+ dram_info = intel_dram_info(display);
+
/*
* Starting with Xe3p_LPD, the hardware tells us whether memory has ECC
* enabled that would impact display bandwidth. However, so far there
--
2.53.0
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v3 2/5] drm/i915/bw: Extract platform-specific parameters
2026-05-14 19:19 [PATCH v3 0/5] drm/i915/bw: Split bandwidth params into platform- and display-IP-specific structs Gustavo Sousa
2026-05-14 19:19 ` [PATCH v3 1/5] drm/i915/bw: Don't call intel_dram_info() too early Gustavo Sousa
@ 2026-05-14 19:19 ` Gustavo Sousa
2026-05-15 15:41 ` Gustavo Sousa
2026-05-14 19:19 ` [PATCH v3 3/5] drm/i915/bw: Deduplicate intel_sa_info instances Gustavo Sousa
` (6 subsequent siblings)
8 siblings, 1 reply; 15+ messages in thread
From: Gustavo Sousa @ 2026-05-14 19:19 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: Gustavo Sousa, Jani Nikula, Matt Roper, Rodrigo Vivi
We got confirmation from the hardware team that the bandwidth parameters
deprogbwlimit and derating are platform-specific and not tied to the
display IP. As such, let's make sure that we use platform checks for
those.
The rest of the members of struct intel_sa_info are tied to the display
IP and we will deal with them as a follow-up.
v2:
- Use good old if-ladder instead of weird-looking pattern "assign ret,
check platform, then return ret". (Jani, Matt)
- Have a single call site for get_platform_bw_params() and pass the
result as parameter to the *_get_bw_info() functions. (Jani)
- Avoid using "plat" as abbreviation for "platform". (Jani)
- s/_plat_bw_params/_bw_params/, since all of the instances are
prefixed with platform names. (Jani)
- s/struct intel_platform_bw_params/struct intel_soc_bw_params/.
(Matt)
- Do not return a default value; prefer to return NULL and
intentionally cause a NULL pointer dereference if a platform is
missing. (Gustavo)
v3:
- Call get_soc_bw_params() only after the check on
HAS_DISPLAY(display). (Jani)
- Combine if-ladder branches for adl_s_bw_params into a single one.
(Matt)
- Flatten if-ladder by checking for WCL before PTL (as opposed to
checking for WCL inside the brace for PTL). (Matt)
- Bail out of intel_bw_init_hw() if display version is below 11.
(Gustavo)
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
drivers/gpu/drm/i915/display/intel_bw.c | 162 ++++++++++++++++++++++----------
1 file changed, 114 insertions(+), 48 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index 7eef693b51ad..351ecf741b54 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -372,81 +372,144 @@ static int icl_sagv_max_dclk(const struct intel_qgv_info *qi)
return dclk;
}
+struct intel_soc_bw_params {
+ u8 deprogbwlimit;
+ u8 derating;
+};
+
+static const struct intel_soc_bw_params icl_bw_params = {
+ .deprogbwlimit = 25,
+ .derating = 10,
+};
+
+static const struct intel_soc_bw_params tgl_bw_params = {
+ .deprogbwlimit = 34,
+ .derating = 10,
+};
+
+static const struct intel_soc_bw_params rkl_bw_params = {
+ .deprogbwlimit = 20,
+ .derating = 10,
+};
+
+static const struct intel_soc_bw_params adl_s_bw_params = {
+ .deprogbwlimit = 38,
+ .derating = 10,
+};
+
+static const struct intel_soc_bw_params adl_p_bw_params = {
+ .deprogbwlimit = 38,
+ .derating = 20,
+};
+
+static const struct intel_soc_bw_params bmg_bw_params = {
+ .deprogbwlimit = 53,
+ .derating = 30,
+};
+
+static const struct intel_soc_bw_params bmg_ecc_bw_params = {
+ .deprogbwlimit = 53,
+ .derating = 45,
+};
+
+static const struct intel_soc_bw_params ptl_bw_params = {
+ .deprogbwlimit = 65,
+ .derating = 10,
+};
+
+static const struct intel_soc_bw_params wcl_bw_params = {
+ .deprogbwlimit = 22,
+ .derating = 10,
+};
+
+static const struct intel_soc_bw_params *get_soc_bw_params(struct intel_display *display)
+{
+ if (display->platform.dgfx) {
+ if (display->platform.dg1) {
+ return &tgl_bw_params;
+ } else if (display->platform.battlemage) {
+ const struct dram_info *dram_info = intel_dram_info(display);
+
+ if (dram_info->type == INTEL_DRAM_GDDR_ECC)
+ return &bmg_ecc_bw_params;
+ else
+ return &bmg_bw_params;
+ }
+ } else {
+ if (display->platform.icelake ||
+ display->platform.jasperlake ||
+ display->platform.elkhartlake)
+ return &icl_bw_params;
+ else if (display->platform.tigerlake)
+ return &tgl_bw_params;
+ else if (display->platform.rocketlake)
+ return &rkl_bw_params;
+ else if (display->platform.alderlake_s ||
+ display->platform.meteorlake ||
+ display->platform.lunarlake)
+ return &adl_s_bw_params;
+ else if (display->platform.alderlake_p)
+ return &adl_p_bw_params;
+ else if (display->platform.pantherlake_wildcatlake)
+ return &wcl_bw_params;
+ else if (display->platform.pantherlake ||
+ display->platform.novalake)
+ return &ptl_bw_params;
+ }
+
+ drm_WARN(display->drm, 1, "Platform-specific bandwidth parameters not found!\n");
+
+ return NULL;
+}
+
struct intel_sa_info {
u16 displayrtids;
- u8 deburst, deprogbwlimit, derating;
+ u8 deburst;
};
static const struct intel_sa_info icl_sa_info = {
.deburst = 8,
- .deprogbwlimit = 25, /* GB/s */
.displayrtids = 128,
- .derating = 10,
};
static const struct intel_sa_info tgl_sa_info = {
.deburst = 16,
- .deprogbwlimit = 34, /* GB/s */
.displayrtids = 256,
- .derating = 10,
};
static const struct intel_sa_info rkl_sa_info = {
.deburst = 8,
- .deprogbwlimit = 20, /* GB/s */
.displayrtids = 128,
- .derating = 10,
};
static const struct intel_sa_info adls_sa_info = {
.deburst = 16,
- .deprogbwlimit = 38, /* GB/s */
.displayrtids = 256,
- .derating = 10,
};
static const struct intel_sa_info adlp_sa_info = {
.deburst = 16,
- .deprogbwlimit = 38, /* GB/s */
.displayrtids = 256,
- .derating = 20,
};
static const struct intel_sa_info mtl_sa_info = {
.deburst = 32,
- .deprogbwlimit = 38, /* GB/s */
.displayrtids = 256,
- .derating = 10,
-};
-
-static const struct intel_sa_info xe2_hpd_sa_info = {
- .derating = 30,
- .deprogbwlimit = 53,
- /* Other values not used by simplified algorithm */
-};
-
-static const struct intel_sa_info xe2_hpd_ecc_sa_info = {
- .derating = 45,
- .deprogbwlimit = 53,
- /* Other values not used by simplified algorithm */
};
static const struct intel_sa_info xe3lpd_sa_info = {
.deburst = 32,
- .deprogbwlimit = 65, /* GB/s */
.displayrtids = 256,
- .derating = 10,
};
static const struct intel_sa_info xe3lpd_3002_sa_info = {
.deburst = 32,
- .deprogbwlimit = 22, /* GB/s */
.displayrtids = 256,
- .derating = 10,
};
static int icl_get_bw_info(struct intel_display *display,
const struct dram_info *dram_info,
+ const struct intel_soc_bw_params *soc_bw_params,
const struct intel_sa_info *sa)
{
struct intel_qgv_info qi = {};
@@ -466,7 +529,7 @@ static int icl_get_bw_info(struct intel_display *display,
}
dclk_max = icl_sagv_max_dclk(&qi);
- maxdebw = min(sa->deprogbwlimit * 1000, dclk_max * 16 * 6 / 10);
+ maxdebw = min(soc_bw_params->deprogbwlimit * 1000, dclk_max * 16 * 6 / 10);
ipqdepth = min(ipqdepthpch, sa->displayrtids / num_channels);
qi.deinterleave = DIV_ROUND_UP(num_channels, is_y_tile ? 4 : 2);
@@ -496,7 +559,7 @@ static int icl_get_bw_info(struct intel_display *display,
bw = DIV_ROUND_UP(sp->dclk * clpchgroup * 32 * num_channels, ct);
bi->deratedbw[j] = min(maxdebw,
- bw * (100 - sa->derating) / 100);
+ bw * (100 - soc_bw_params->derating) / 100);
drm_dbg_kms(display->drm,
"BW%d / QGV %d: num_planes=%d deratedbw=%u\n",
@@ -518,6 +581,7 @@ static int icl_get_bw_info(struct intel_display *display,
static int tgl_get_bw_info(struct intel_display *display,
const struct dram_info *dram_info,
+ const struct intel_soc_bw_params *soc_bw_params,
const struct intel_sa_info *sa)
{
struct intel_qgv_info qi = {};
@@ -554,7 +618,7 @@ static int tgl_get_bw_info(struct intel_display *display,
dclk_max = icl_sagv_max_dclk(&qi);
peakbw = num_channels * DIV_ROUND_UP(qi.channel_width, 8) * dclk_max;
- maxdebw = min(sa->deprogbwlimit * 1000, peakbw * DEPROGBWPCLIMIT / 100);
+ maxdebw = min(soc_bw_params->deprogbwlimit * 1000, peakbw * DEPROGBWPCLIMIT / 100);
ipqdepth = min(ipqdepthpch, sa->displayrtids / num_channels);
/*
@@ -599,7 +663,7 @@ static int tgl_get_bw_info(struct intel_display *display,
bw = DIV_ROUND_UP(sp->dclk * clpchgroup * 32 * num_channels, ct);
bi->deratedbw[j] = min(maxdebw,
- bw * (100 - sa->derating) / 100);
+ bw * (100 - soc_bw_params->derating) / 100);
bi->peakbw[j] = DIV_ROUND_CLOSEST(sp->dclk *
num_channels *
qi.channel_width, 8);
@@ -661,7 +725,7 @@ static void dg2_get_bw_info(struct intel_display *display)
static int xe2_hpd_get_bw_info(struct intel_display *display,
const struct dram_info *dram_info,
- const struct intel_sa_info *sa)
+ const struct intel_soc_bw_params *soc_bw_params)
{
struct intel_qgv_info qi = {};
int num_channels = dram_info->num_channels;
@@ -676,14 +740,14 @@ static int xe2_hpd_get_bw_info(struct intel_display *display,
}
peakbw = num_channels * qi.channel_width / 8 * icl_sagv_max_dclk(&qi);
- maxdebw = min(sa->deprogbwlimit * 1000, peakbw * DEPROGBWPCLIMIT / 10);
+ maxdebw = min(soc_bw_params->deprogbwlimit * 1000, peakbw * DEPROGBWPCLIMIT / 10);
for (i = 0; i < qi.num_points; i++) {
const struct intel_qgv_point *point = &qi.points[i];
int bw = num_channels * (qi.channel_width / 8) * point->dclk;
display->bw.max[0].deratedbw[i] =
- min(maxdebw, (100 - sa->derating) * bw / 100);
+ min(maxdebw, (100 - soc_bw_params->derating) * bw / 100);
display->bw.max[0].peakbw[i] = bw;
drm_dbg_kms(display->drm, "QGV %d: deratedbw=%u peakbw: %u\n",
@@ -792,11 +856,16 @@ static unsigned int icl_qgv_bw(struct intel_display *display,
void intel_bw_init_hw(struct intel_display *display)
{
const struct dram_info *dram_info;
+ const struct intel_soc_bw_params *soc_bw_params;
if (!HAS_DISPLAY(display))
return;
+ if (DISPLAY_VER(display) < 11)
+ return;
+
dram_info = intel_dram_info(display);
+ soc_bw_params = get_soc_bw_params(display);
/*
* Starting with Xe3p_LPD, the hardware tells us whether memory has ECC
@@ -809,28 +878,25 @@ void intel_bw_init_hw(struct intel_display *display)
if (DISPLAY_VER(display) >= 30) {
if (DISPLAY_VERx100(display) == 3002)
- tgl_get_bw_info(display, dram_info, &xe3lpd_3002_sa_info);
+ tgl_get_bw_info(display, dram_info, soc_bw_params, &xe3lpd_3002_sa_info);
else
- tgl_get_bw_info(display, dram_info, &xe3lpd_sa_info);
+ tgl_get_bw_info(display, dram_info, soc_bw_params, &xe3lpd_sa_info);
} else if (DISPLAY_VERx100(display) >= 1401 && display->platform.dgfx) {
- if (dram_info->type == INTEL_DRAM_GDDR_ECC)
- xe2_hpd_get_bw_info(display, dram_info, &xe2_hpd_ecc_sa_info);
- else
- xe2_hpd_get_bw_info(display, dram_info, &xe2_hpd_sa_info);
+ xe2_hpd_get_bw_info(display, dram_info, soc_bw_params);
} else if (DISPLAY_VER(display) >= 14) {
- tgl_get_bw_info(display, dram_info, &mtl_sa_info);
+ tgl_get_bw_info(display, dram_info, soc_bw_params, &mtl_sa_info);
} else if (display->platform.dg2) {
dg2_get_bw_info(display);
} else if (display->platform.alderlake_p) {
- tgl_get_bw_info(display, dram_info, &adlp_sa_info);
+ tgl_get_bw_info(display, dram_info, soc_bw_params, &adlp_sa_info);
} else if (display->platform.alderlake_s) {
- tgl_get_bw_info(display, dram_info, &adls_sa_info);
+ tgl_get_bw_info(display, dram_info, soc_bw_params, &adls_sa_info);
} else if (display->platform.rocketlake) {
- tgl_get_bw_info(display, dram_info, &rkl_sa_info);
+ tgl_get_bw_info(display, dram_info, soc_bw_params, &rkl_sa_info);
} else if (DISPLAY_VER(display) == 12) {
- tgl_get_bw_info(display, dram_info, &tgl_sa_info);
+ tgl_get_bw_info(display, dram_info, soc_bw_params, &tgl_sa_info);
} else if (DISPLAY_VER(display) == 11) {
- icl_get_bw_info(display, dram_info, &icl_sa_info);
+ icl_get_bw_info(display, dram_info, soc_bw_params, &icl_sa_info);
}
}
--
2.53.0
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v3 3/5] drm/i915/bw: Deduplicate intel_sa_info instances
2026-05-14 19:19 [PATCH v3 0/5] drm/i915/bw: Split bandwidth params into platform- and display-IP-specific structs Gustavo Sousa
2026-05-14 19:19 ` [PATCH v3 1/5] drm/i915/bw: Don't call intel_dram_info() too early Gustavo Sousa
2026-05-14 19:19 ` [PATCH v3 2/5] drm/i915/bw: Extract platform-specific parameters Gustavo Sousa
@ 2026-05-14 19:19 ` Gustavo Sousa
2026-05-14 19:19 ` [PATCH v3 4/5] drm/i915/bw: Rename struct intel_sa_info to intel_display_bw_params Gustavo Sousa
` (5 subsequent siblings)
8 siblings, 0 replies; 15+ messages in thread
From: Gustavo Sousa @ 2026-05-14 19:19 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: Gustavo Sousa, Matt Roper
Now that intel_sa_info contains bandwidth parameters specific to the
display IP, we can drop many duplicates and reuse from previous
releases.
Let's do that and also simplify intel_bw_init_hw() while at it.
v2:
- Drop rkl_sa_info and reuse icl_sa_info. (Matt)
- Add comment explaining RKL's display's peculiarity on using ICL's
parameters. (Matt)
- Don't rename xelpdp_sa_info to mtl_sa_info. Renaming of instances
to use IP names will be done in upcoming changes.
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
drivers/gpu/drm/i915/display/intel_bw.c | 51 ++++++++-------------------------
1 file changed, 12 insertions(+), 39 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index 351ecf741b54..a956b09028f3 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -477,36 +477,11 @@ static const struct intel_sa_info tgl_sa_info = {
.displayrtids = 256,
};
-static const struct intel_sa_info rkl_sa_info = {
- .deburst = 8,
- .displayrtids = 128,
-};
-
-static const struct intel_sa_info adls_sa_info = {
- .deburst = 16,
- .displayrtids = 256,
-};
-
-static const struct intel_sa_info adlp_sa_info = {
- .deburst = 16,
- .displayrtids = 256,
-};
-
static const struct intel_sa_info mtl_sa_info = {
.deburst = 32,
.displayrtids = 256,
};
-static const struct intel_sa_info xe3lpd_sa_info = {
- .deburst = 32,
- .displayrtids = 256,
-};
-
-static const struct intel_sa_info xe3lpd_3002_sa_info = {
- .deburst = 32,
- .displayrtids = 256,
-};
-
static int icl_get_bw_info(struct intel_display *display,
const struct dram_info *dram_info,
const struct intel_soc_bw_params *soc_bw_params,
@@ -876,25 +851,23 @@ void intel_bw_init_hw(struct intel_display *display)
if (DISPLAY_VER(display) >= 35)
drm_WARN_ON(display->drm, dram_info->ecc_impacting_de_bw);
- if (DISPLAY_VER(display) >= 30) {
- if (DISPLAY_VERx100(display) == 3002)
- tgl_get_bw_info(display, dram_info, soc_bw_params, &xe3lpd_3002_sa_info);
- else
- tgl_get_bw_info(display, dram_info, soc_bw_params, &xe3lpd_sa_info);
- } else if (DISPLAY_VERx100(display) >= 1401 && display->platform.dgfx) {
+ if (DISPLAY_VERx100(display) >= 1401 && display->platform.dgfx) {
xe2_hpd_get_bw_info(display, dram_info, soc_bw_params);
} else if (DISPLAY_VER(display) >= 14) {
tgl_get_bw_info(display, dram_info, soc_bw_params, &mtl_sa_info);
} else if (display->platform.dg2) {
dg2_get_bw_info(display);
- } else if (display->platform.alderlake_p) {
- tgl_get_bw_info(display, dram_info, soc_bw_params, &adlp_sa_info);
- } else if (display->platform.alderlake_s) {
- tgl_get_bw_info(display, dram_info, soc_bw_params, &adls_sa_info);
- } else if (display->platform.rocketlake) {
- tgl_get_bw_info(display, dram_info, soc_bw_params, &rkl_sa_info);
- } else if (DISPLAY_VER(display) == 12) {
- tgl_get_bw_info(display, dram_info, soc_bw_params, &tgl_sa_info);
+ } else if (DISPLAY_VER(display) >= 12) {
+ /*
+ * RKL's SoC was based on ICL and the display, even though being
+ * gen12, had changes to the memory interface to match gen11's,
+ * consequently inheriting gen11's display-specific bandwidth
+ * parameters.
+ */
+ if (display->platform.rocketlake)
+ tgl_get_bw_info(display, dram_info, soc_bw_params, &icl_sa_info);
+ else
+ tgl_get_bw_info(display, dram_info, soc_bw_params, &tgl_sa_info);
} else if (DISPLAY_VER(display) == 11) {
icl_get_bw_info(display, dram_info, soc_bw_params, &icl_sa_info);
}
--
2.53.0
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v3 4/5] drm/i915/bw: Rename struct intel_sa_info to intel_display_bw_params
2026-05-14 19:19 [PATCH v3 0/5] drm/i915/bw: Split bandwidth params into platform- and display-IP-specific structs Gustavo Sousa
` (2 preceding siblings ...)
2026-05-14 19:19 ` [PATCH v3 3/5] drm/i915/bw: Deduplicate intel_sa_info instances Gustavo Sousa
@ 2026-05-14 19:19 ` Gustavo Sousa
2026-05-14 19:19 ` [PATCH v3 5/5] drm/i915/bw: Extract get_display_bw_params() Gustavo Sousa
` (4 subsequent siblings)
8 siblings, 0 replies; 15+ messages in thread
From: Gustavo Sousa @ 2026-05-14 19:19 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: Gustavo Sousa, Jani Nikula, Matt Roper
To align with struct intel_platform_bw_params, rename struct
intel_sa_info to intel_display_bw_params. Also add comments to contrast
their purposes.
v2:
- Use gen11 and gen12 as prefixes for ICL's and TGL's display-specific
parameters variables. (Matt)
- Prefer to use "display" instead of "disp" in variable names. (Jani)
- Drop the redundant "disp" from the variable names.
Cc: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
drivers/gpu/drm/i915/display/intel_bw.c | 36 ++++++++++++++++++++-------------
1 file changed, 22 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index a956b09028f3..5821397dc27f 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -372,6 +372,10 @@ static int icl_sagv_max_dclk(const struct intel_qgv_info *qi)
return dclk;
}
+/*
+ * Bandwidth parameters that are tied to the SoC (as opposed to struct
+ * intel_display_bw_params).
+ */
struct intel_soc_bw_params {
u8 deprogbwlimit;
u8 derating;
@@ -462,22 +466,26 @@ static const struct intel_soc_bw_params *get_soc_bw_params(struct intel_display
return NULL;
}
-struct intel_sa_info {
+/*
+ * Bandwidth parameters that are tied to the display IP (as opposed to struct
+ * intel_soc_bw_params).
+ */
+struct intel_display_bw_params {
u16 displayrtids;
u8 deburst;
};
-static const struct intel_sa_info icl_sa_info = {
+static const struct intel_display_bw_params gen11_bw_params = {
.deburst = 8,
.displayrtids = 128,
};
-static const struct intel_sa_info tgl_sa_info = {
+static const struct intel_display_bw_params gen12_bw_params = {
.deburst = 16,
.displayrtids = 256,
};
-static const struct intel_sa_info mtl_sa_info = {
+static const struct intel_display_bw_params xelpdp_bw_params = {
.deburst = 32,
.displayrtids = 256,
};
@@ -485,7 +493,7 @@ static const struct intel_sa_info mtl_sa_info = {
static int icl_get_bw_info(struct intel_display *display,
const struct dram_info *dram_info,
const struct intel_soc_bw_params *soc_bw_params,
- const struct intel_sa_info *sa)
+ const struct intel_display_bw_params *display_bw_params)
{
struct intel_qgv_info qi = {};
bool is_y_tile = true; /* assume y tile may be used */
@@ -505,7 +513,7 @@ static int icl_get_bw_info(struct intel_display *display,
dclk_max = icl_sagv_max_dclk(&qi);
maxdebw = min(soc_bw_params->deprogbwlimit * 1000, dclk_max * 16 * 6 / 10);
- ipqdepth = min(ipqdepthpch, sa->displayrtids / num_channels);
+ ipqdepth = min(ipqdepthpch, display_bw_params->displayrtids / num_channels);
qi.deinterleave = DIV_ROUND_UP(num_channels, is_y_tile ? 4 : 2);
for (i = 0; i < num_groups; i++) {
@@ -513,7 +521,7 @@ static int icl_get_bw_info(struct intel_display *display,
int clpchgroup;
int j;
- clpchgroup = (sa->deburst * qi.deinterleave / num_channels) << i;
+ clpchgroup = (display_bw_params->deburst * qi.deinterleave / num_channels) << i;
bi->num_planes = (ipqdepth - clpchgroup) / clpchgroup + 1;
bi->num_qgv_points = qi.num_points;
@@ -557,7 +565,7 @@ static int icl_get_bw_info(struct intel_display *display,
static int tgl_get_bw_info(struct intel_display *display,
const struct dram_info *dram_info,
const struct intel_soc_bw_params *soc_bw_params,
- const struct intel_sa_info *sa)
+ const struct intel_display_bw_params *display_bw_params)
{
struct intel_qgv_info qi = {};
bool is_y_tile = true; /* assume y tile may be used */
@@ -595,7 +603,7 @@ static int tgl_get_bw_info(struct intel_display *display,
peakbw = num_channels * DIV_ROUND_UP(qi.channel_width, 8) * dclk_max;
maxdebw = min(soc_bw_params->deprogbwlimit * 1000, peakbw * DEPROGBWPCLIMIT / 100);
- ipqdepth = min(ipqdepthpch, sa->displayrtids / num_channels);
+ ipqdepth = min(ipqdepthpch, display_bw_params->displayrtids / num_channels);
/*
* clperchgroup = 4kpagespermempage * clperchperblock,
* clperchperblock = 8 / num_channels * interleave
@@ -608,7 +616,7 @@ static int tgl_get_bw_info(struct intel_display *display,
int clpchgroup;
int j;
- clpchgroup = (sa->deburst * qi.deinterleave / num_channels) << i;
+ clpchgroup = (display_bw_params->deburst * qi.deinterleave / num_channels) << i;
if (i < num_groups - 1) {
bi_next = &display->bw.max[i + 1];
@@ -854,7 +862,7 @@ void intel_bw_init_hw(struct intel_display *display)
if (DISPLAY_VERx100(display) >= 1401 && display->platform.dgfx) {
xe2_hpd_get_bw_info(display, dram_info, soc_bw_params);
} else if (DISPLAY_VER(display) >= 14) {
- tgl_get_bw_info(display, dram_info, soc_bw_params, &mtl_sa_info);
+ tgl_get_bw_info(display, dram_info, soc_bw_params, &xelpdp_bw_params);
} else if (display->platform.dg2) {
dg2_get_bw_info(display);
} else if (DISPLAY_VER(display) >= 12) {
@@ -865,11 +873,11 @@ void intel_bw_init_hw(struct intel_display *display)
* parameters.
*/
if (display->platform.rocketlake)
- tgl_get_bw_info(display, dram_info, soc_bw_params, &icl_sa_info);
+ tgl_get_bw_info(display, dram_info, soc_bw_params, &gen11_bw_params);
else
- tgl_get_bw_info(display, dram_info, soc_bw_params, &tgl_sa_info);
+ tgl_get_bw_info(display, dram_info, soc_bw_params, &gen12_bw_params);
} else if (DISPLAY_VER(display) == 11) {
- icl_get_bw_info(display, dram_info, soc_bw_params, &icl_sa_info);
+ icl_get_bw_info(display, dram_info, soc_bw_params, &gen11_bw_params);
}
}
--
2.53.0
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v3 5/5] drm/i915/bw: Extract get_display_bw_params()
2026-05-14 19:19 [PATCH v3 0/5] drm/i915/bw: Split bandwidth params into platform- and display-IP-specific structs Gustavo Sousa
` (3 preceding siblings ...)
2026-05-14 19:19 ` [PATCH v3 4/5] drm/i915/bw: Rename struct intel_sa_info to intel_display_bw_params Gustavo Sousa
@ 2026-05-14 19:19 ` Gustavo Sousa
2026-05-14 20:16 ` ✓ CI.KUnit: success for drm/i915/bw: Split bandwidth params into platform- and display-IP-specific structs (rev2) Patchwork
` (3 subsequent siblings)
8 siblings, 0 replies; 15+ messages in thread
From: Gustavo Sousa @ 2026-05-14 19:19 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: Gustavo Sousa, Jani Nikula, Matt Roper
Just like it is done for the platform-specific bandwidth parameters, use
a separate function named get_display_bw_params() to return the display
IP-specific parameters. This simplifies intel_bw_init_hw() by having
just one call for each of the *_get_bw_info() functions.
v2:
- Prefer to call get_display_bw_params() only once in
intel_bw_init_hw() instead of having multiple calls in each of the
affected *_get_bw_info() functions. (Jani)
v3:
- Call get_display_bw_params() only after the check on
HAS_DISPLAY(display). (Jani)
- Return &gen11_bw_params only if display version is 11. (Matt)
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
drivers/gpu/drm/i915/display/intel_bw.c | 41 ++++++++++++++++++++++-----------
1 file changed, 28 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index 5821397dc27f..07407384e261 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -490,6 +490,30 @@ static const struct intel_display_bw_params xelpdp_bw_params = {
.displayrtids = 256,
};
+static const struct intel_display_bw_params *get_display_bw_params(struct intel_display *display)
+{
+ if (DISPLAY_VER(display) >= 14) {
+ return &xelpdp_bw_params;
+ } else if (DISPLAY_VER(display) >= 12) {
+ /*
+ * RKL's SoC was based on ICL and the display, even though being
+ * gen12, had changes to the memory interface to match gen11's,
+ * consequently inheriting gen11's display-specific bandwidth
+ * parameters.
+ */
+ if (display->platform.rocketlake)
+ return &gen11_bw_params;
+ else
+ return &gen12_bw_params;
+ } else if (DISPLAY_VER(display) == 11) {
+ return &gen11_bw_params;
+ }
+
+ drm_WARN(display->drm, 1, "Display-specific bandwidth parameters not found!\n");
+
+ return NULL;
+}
+
static int icl_get_bw_info(struct intel_display *display,
const struct dram_info *dram_info,
const struct intel_soc_bw_params *soc_bw_params,
@@ -840,6 +864,7 @@ void intel_bw_init_hw(struct intel_display *display)
{
const struct dram_info *dram_info;
const struct intel_soc_bw_params *soc_bw_params;
+ const struct intel_display_bw_params *display_bw_params;
if (!HAS_DISPLAY(display))
return;
@@ -849,6 +874,7 @@ void intel_bw_init_hw(struct intel_display *display)
dram_info = intel_dram_info(display);
soc_bw_params = get_soc_bw_params(display);
+ display_bw_params = get_display_bw_params(display);
/*
* Starting with Xe3p_LPD, the hardware tells us whether memory has ECC
@@ -861,23 +887,12 @@ void intel_bw_init_hw(struct intel_display *display)
if (DISPLAY_VERx100(display) >= 1401 && display->platform.dgfx) {
xe2_hpd_get_bw_info(display, dram_info, soc_bw_params);
- } else if (DISPLAY_VER(display) >= 14) {
- tgl_get_bw_info(display, dram_info, soc_bw_params, &xelpdp_bw_params);
} else if (display->platform.dg2) {
dg2_get_bw_info(display);
} else if (DISPLAY_VER(display) >= 12) {
- /*
- * RKL's SoC was based on ICL and the display, even though being
- * gen12, had changes to the memory interface to match gen11's,
- * consequently inheriting gen11's display-specific bandwidth
- * parameters.
- */
- if (display->platform.rocketlake)
- tgl_get_bw_info(display, dram_info, soc_bw_params, &gen11_bw_params);
- else
- tgl_get_bw_info(display, dram_info, soc_bw_params, &gen12_bw_params);
+ tgl_get_bw_info(display, dram_info, soc_bw_params, display_bw_params);
} else if (DISPLAY_VER(display) == 11) {
- icl_get_bw_info(display, dram_info, soc_bw_params, &gen11_bw_params);
+ icl_get_bw_info(display, dram_info, soc_bw_params, display_bw_params);
}
}
--
2.53.0
^ permalink raw reply related [flat|nested] 15+ messages in thread
* ✓ CI.KUnit: success for drm/i915/bw: Split bandwidth params into platform- and display-IP-specific structs (rev2)
2026-05-14 19:19 [PATCH v3 0/5] drm/i915/bw: Split bandwidth params into platform- and display-IP-specific structs Gustavo Sousa
` (4 preceding siblings ...)
2026-05-14 19:19 ` [PATCH v3 5/5] drm/i915/bw: Extract get_display_bw_params() Gustavo Sousa
@ 2026-05-14 20:16 ` Patchwork
2026-05-14 20:36 ` ✗ i915.CI.BAT: failure for drm/i915/bw: Split bandwidth params into platform- and display-IP-specific structs (rev3) Patchwork
` (2 subsequent siblings)
8 siblings, 0 replies; 15+ messages in thread
From: Patchwork @ 2026-05-14 20:16 UTC (permalink / raw)
To: Gustavo Sousa; +Cc: intel-xe
== Series Details ==
Series: drm/i915/bw: Split bandwidth params into platform- and display-IP-specific structs (rev2)
URL : https://patchwork.freedesktop.org/series/166340/
State : success
== Summary ==
+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[20:14:43] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[20:14:47] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[20:15:26] Starting KUnit Kernel (1/1)...
[20:15:26] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[20:15:27] ================== guc_buf (11 subtests) ===================
[20:15:27] [PASSED] test_smallest
[20:15:27] [PASSED] test_largest
[20:15:27] [PASSED] test_granular
[20:15:27] [PASSED] test_unique
[20:15:27] [PASSED] test_overlap
[20:15:27] [PASSED] test_reusable
[20:15:27] [PASSED] test_too_big
[20:15:27] [PASSED] test_flush
[20:15:27] [PASSED] test_lookup
[20:15:27] [PASSED] test_data
[20:15:27] [PASSED] test_class
[20:15:27] ===================== [PASSED] guc_buf =====================
[20:15:27] =================== guc_dbm (7 subtests) ===================
[20:15:27] [PASSED] test_empty
[20:15:27] [PASSED] test_default
[20:15:27] ======================== test_size ========================
[20:15:27] [PASSED] 4
[20:15:27] [PASSED] 8
[20:15:27] [PASSED] 32
[20:15:27] [PASSED] 256
[20:15:27] ==================== [PASSED] test_size ====================
[20:15:27] ======================= test_reuse ========================
[20:15:27] [PASSED] 4
[20:15:27] [PASSED] 8
[20:15:27] [PASSED] 32
[20:15:27] [PASSED] 256
[20:15:27] =================== [PASSED] test_reuse ====================
[20:15:27] =================== test_range_overlap ====================
[20:15:27] [PASSED] 4
[20:15:27] [PASSED] 8
[20:15:27] [PASSED] 32
[20:15:27] [PASSED] 256
[20:15:27] =============== [PASSED] test_range_overlap ================
[20:15:27] =================== test_range_compact ====================
[20:15:27] [PASSED] 4
[20:15:27] [PASSED] 8
[20:15:27] [PASSED] 32
[20:15:27] [PASSED] 256
[20:15:27] =============== [PASSED] test_range_compact ================
[20:15:27] ==================== test_range_spare =====================
[20:15:27] [PASSED] 4
[20:15:27] [PASSED] 8
[20:15:27] [PASSED] 32
[20:15:27] [PASSED] 256
[20:15:27] ================ [PASSED] test_range_spare =================
[20:15:27] ===================== [PASSED] guc_dbm =====================
[20:15:27] =================== guc_idm (6 subtests) ===================
[20:15:27] [PASSED] bad_init
[20:15:27] [PASSED] no_init
[20:15:27] [PASSED] init_fini
[20:15:27] [PASSED] check_used
[20:15:27] [PASSED] check_quota
[20:15:27] [PASSED] check_all
[20:15:27] ===================== [PASSED] guc_idm =====================
[20:15:27] ================== no_relay (3 subtests) ===================
[20:15:27] [PASSED] xe_drops_guc2pf_if_not_ready
[20:15:27] [PASSED] xe_drops_guc2vf_if_not_ready
[20:15:27] [PASSED] xe_rejects_send_if_not_ready
[20:15:27] ==================== [PASSED] no_relay =====================
[20:15:27] ================== pf_relay (14 subtests) ==================
[20:15:27] [PASSED] pf_rejects_guc2pf_too_short
[20:15:27] [PASSED] pf_rejects_guc2pf_too_long
[20:15:27] [PASSED] pf_rejects_guc2pf_no_payload
[20:15:27] [PASSED] pf_fails_no_payload
[20:15:27] [PASSED] pf_fails_bad_origin
[20:15:27] [PASSED] pf_fails_bad_type
[20:15:27] [PASSED] pf_txn_reports_error
[20:15:27] [PASSED] pf_txn_sends_pf2guc
[20:15:27] [PASSED] pf_sends_pf2guc
[20:15:27] [SKIPPED] pf_loopback_nop
[20:15:27] [SKIPPED] pf_loopback_echo
[20:15:27] [SKIPPED] pf_loopback_fail
[20:15:27] [SKIPPED] pf_loopback_busy
[20:15:27] [SKIPPED] pf_loopback_retry
[20:15:27] ==================== [PASSED] pf_relay =====================
[20:15:27] ================== vf_relay (3 subtests) ===================
[20:15:27] [PASSED] vf_rejects_guc2vf_too_short
[20:15:27] [PASSED] vf_rejects_guc2vf_too_long
[20:15:27] [PASSED] vf_rejects_guc2vf_no_payload
[20:15:27] ==================== [PASSED] vf_relay =====================
[20:15:27] ================ pf_gt_config (9 subtests) =================
[20:15:27] [PASSED] fair_contexts_1vf
[20:15:27] [PASSED] fair_doorbells_1vf
[20:15:27] [PASSED] fair_ggtt_1vf
[20:15:27] ====================== fair_vram_1vf ======================
[20:15:27] [PASSED] 3.50 GiB
[20:15:27] [PASSED] 11.5 GiB
[20:15:27] [PASSED] 15.5 GiB
[20:15:27] [PASSED] 31.5 GiB
[20:15:27] [PASSED] 63.5 GiB
[20:15:27] [PASSED] 1.91 GiB
[20:15:27] ================== [PASSED] fair_vram_1vf ==================
[20:15:27] ================ fair_vram_1vf_admin_only =================
[20:15:27] [PASSED] 3.50 GiB
[20:15:27] [PASSED] 11.5 GiB
[20:15:27] [PASSED] 15.5 GiB
[20:15:27] [PASSED] 31.5 GiB
[20:15:27] [PASSED] 63.5 GiB
[20:15:27] [PASSED] 1.91 GiB
[20:15:27] ============ [PASSED] fair_vram_1vf_admin_only =============
[20:15:27] ====================== fair_contexts ======================
[20:15:27] [PASSED] 1 VF
[20:15:27] [PASSED] 2 VFs
[20:15:27] [PASSED] 3 VFs
[20:15:27] [PASSED] 4 VFs
[20:15:27] [PASSED] 5 VFs
[20:15:27] [PASSED] 6 VFs
[20:15:27] [PASSED] 7 VFs
[20:15:27] [PASSED] 8 VFs
[20:15:27] [PASSED] 9 VFs
[20:15:27] [PASSED] 10 VFs
[20:15:27] [PASSED] 11 VFs
[20:15:27] [PASSED] 12 VFs
[20:15:27] [PASSED] 13 VFs
[20:15:27] [PASSED] 14 VFs
[20:15:27] [PASSED] 15 VFs
[20:15:27] [PASSED] 16 VFs
[20:15:27] [PASSED] 17 VFs
[20:15:27] [PASSED] 18 VFs
[20:15:27] [PASSED] 19 VFs
[20:15:27] [PASSED] 20 VFs
[20:15:27] [PASSED] 21 VFs
[20:15:27] [PASSED] 22 VFs
[20:15:27] [PASSED] 23 VFs
[20:15:27] [PASSED] 24 VFs
[20:15:27] [PASSED] 25 VFs
[20:15:27] [PASSED] 26 VFs
[20:15:27] [PASSED] 27 VFs
[20:15:27] [PASSED] 28 VFs
[20:15:27] [PASSED] 29 VFs
[20:15:27] [PASSED] 30 VFs
[20:15:27] [PASSED] 31 VFs
[20:15:27] [PASSED] 32 VFs
[20:15:27] [PASSED] 33 VFs
[20:15:27] [PASSED] 34 VFs
[20:15:27] [PASSED] 35 VFs
[20:15:27] [PASSED] 36 VFs
[20:15:27] [PASSED] 37 VFs
[20:15:27] [PASSED] 38 VFs
[20:15:27] [PASSED] 39 VFs
[20:15:27] [PASSED] 40 VFs
[20:15:27] [PASSED] 41 VFs
[20:15:27] [PASSED] 42 VFs
[20:15:27] [PASSED] 43 VFs
[20:15:27] [PASSED] 44 VFs
[20:15:27] [PASSED] 45 VFs
[20:15:27] [PASSED] 46 VFs
[20:15:27] [PASSED] 47 VFs
[20:15:27] [PASSED] 48 VFs
[20:15:27] [PASSED] 49 VFs
[20:15:27] [PASSED] 50 VFs
[20:15:27] [PASSED] 51 VFs
[20:15:27] [PASSED] 52 VFs
[20:15:27] [PASSED] 53 VFs
[20:15:27] [PASSED] 54 VFs
[20:15:27] [PASSED] 55 VFs
[20:15:27] [PASSED] 56 VFs
[20:15:27] [PASSED] 57 VFs
[20:15:27] [PASSED] 58 VFs
[20:15:27] [PASSED] 59 VFs
[20:15:27] [PASSED] 60 VFs
[20:15:27] [PASSED] 61 VFs
[20:15:27] [PASSED] 62 VFs
[20:15:27] [PASSED] 63 VFs
[20:15:27] ================== [PASSED] fair_contexts ==================
[20:15:27] ===================== fair_doorbells ======================
[20:15:27] [PASSED] 1 VF
[20:15:27] [PASSED] 2 VFs
[20:15:27] [PASSED] 3 VFs
[20:15:27] [PASSED] 4 VFs
[20:15:27] [PASSED] 5 VFs
[20:15:27] [PASSED] 6 VFs
[20:15:27] [PASSED] 7 VFs
[20:15:27] [PASSED] 8 VFs
[20:15:27] [PASSED] 9 VFs
[20:15:27] [PASSED] 10 VFs
[20:15:27] [PASSED] 11 VFs
[20:15:27] [PASSED] 12 VFs
[20:15:27] [PASSED] 13 VFs
[20:15:27] [PASSED] 14 VFs
[20:15:27] [PASSED] 15 VFs
[20:15:27] [PASSED] 16 VFs
[20:15:27] [PASSED] 17 VFs
[20:15:27] [PASSED] 18 VFs
[20:15:27] [PASSED] 19 VFs
[20:15:27] [PASSED] 20 VFs
[20:15:27] [PASSED] 21 VFs
[20:15:27] [PASSED] 22 VFs
[20:15:27] [PASSED] 23 VFs
[20:15:27] [PASSED] 24 VFs
[20:15:27] [PASSED] 25 VFs
[20:15:27] [PASSED] 26 VFs
[20:15:27] [PASSED] 27 VFs
[20:15:27] [PASSED] 28 VFs
[20:15:27] [PASSED] 29 VFs
[20:15:27] [PASSED] 30 VFs
[20:15:27] [PASSED] 31 VFs
[20:15:27] [PASSED] 32 VFs
[20:15:27] [PASSED] 33 VFs
[20:15:27] [PASSED] 34 VFs
[20:15:27] [PASSED] 35 VFs
[20:15:27] [PASSED] 36 VFs
[20:15:27] [PASSED] 37 VFs
[20:15:27] [PASSED] 38 VFs
[20:15:27] [PASSED] 39 VFs
[20:15:27] [PASSED] 40 VFs
[20:15:27] [PASSED] 41 VFs
[20:15:27] [PASSED] 42 VFs
[20:15:27] [PASSED] 43 VFs
[20:15:27] [PASSED] 44 VFs
[20:15:27] [PASSED] 45 VFs
[20:15:27] [PASSED] 46 VFs
[20:15:27] [PASSED] 47 VFs
[20:15:27] [PASSED] 48 VFs
[20:15:27] [PASSED] 49 VFs
[20:15:27] [PASSED] 50 VFs
[20:15:27] [PASSED] 51 VFs
[20:15:27] [PASSED] 52 VFs
[20:15:27] [PASSED] 53 VFs
[20:15:27] [PASSED] 54 VFs
[20:15:27] [PASSED] 55 VFs
[20:15:27] [PASSED] 56 VFs
[20:15:27] [PASSED] 57 VFs
[20:15:27] [PASSED] 58 VFs
[20:15:27] [PASSED] 59 VFs
[20:15:27] [PASSED] 60 VFs
[20:15:27] [PASSED] 61 VFs
[20:15:27] [PASSED] 62 VFs
[20:15:27] [PASSED] 63 VFs
[20:15:27] ================= [PASSED] fair_doorbells ==================
[20:15:27] ======================== fair_ggtt ========================
[20:15:27] [PASSED] 1 VF
[20:15:27] [PASSED] 2 VFs
[20:15:27] [PASSED] 3 VFs
[20:15:27] [PASSED] 4 VFs
[20:15:27] [PASSED] 5 VFs
[20:15:27] [PASSED] 6 VFs
[20:15:27] [PASSED] 7 VFs
[20:15:27] [PASSED] 8 VFs
[20:15:27] [PASSED] 9 VFs
[20:15:27] [PASSED] 10 VFs
[20:15:27] [PASSED] 11 VFs
[20:15:27] [PASSED] 12 VFs
[20:15:27] [PASSED] 13 VFs
[20:15:27] [PASSED] 14 VFs
[20:15:27] [PASSED] 15 VFs
[20:15:27] [PASSED] 16 VFs
[20:15:27] [PASSED] 17 VFs
[20:15:27] [PASSED] 18 VFs
[20:15:27] [PASSED] 19 VFs
[20:15:27] [PASSED] 20 VFs
[20:15:27] [PASSED] 21 VFs
[20:15:27] [PASSED] 22 VFs
[20:15:27] [PASSED] 23 VFs
[20:15:27] [PASSED] 24 VFs
[20:15:27] [PASSED] 25 VFs
[20:15:27] [PASSED] 26 VFs
[20:15:27] [PASSED] 27 VFs
[20:15:27] [PASSED] 28 VFs
[20:15:27] [PASSED] 29 VFs
[20:15:27] [PASSED] 30 VFs
[20:15:27] [PASSED] 31 VFs
[20:15:27] [PASSED] 32 VFs
[20:15:27] [PASSED] 33 VFs
[20:15:27] [PASSED] 34 VFs
[20:15:27] [PASSED] 35 VFs
[20:15:27] [PASSED] 36 VFs
[20:15:27] [PASSED] 37 VFs
[20:15:27] [PASSED] 38 VFs
[20:15:27] [PASSED] 39 VFs
[20:15:27] [PASSED] 40 VFs
[20:15:27] [PASSED] 41 VFs
[20:15:27] [PASSED] 42 VFs
[20:15:27] [PASSED] 43 VFs
[20:15:27] [PASSED] 44 VFs
[20:15:27] [PASSED] 45 VFs
[20:15:27] [PASSED] 46 VFs
[20:15:27] [PASSED] 47 VFs
[20:15:27] [PASSED] 48 VFs
[20:15:27] [PASSED] 49 VFs
[20:15:27] [PASSED] 50 VFs
[20:15:27] [PASSED] 51 VFs
[20:15:27] [PASSED] 52 VFs
[20:15:27] [PASSED] 53 VFs
[20:15:27] [PASSED] 54 VFs
[20:15:27] [PASSED] 55 VFs
[20:15:27] [PASSED] 56 VFs
[20:15:27] [PASSED] 57 VFs
[20:15:27] [PASSED] 58 VFs
[20:15:27] [PASSED] 59 VFs
[20:15:27] [PASSED] 60 VFs
[20:15:27] [PASSED] 61 VFs
[20:15:27] [PASSED] 62 VFs
[20:15:27] [PASSED] 63 VFs
[20:15:27] ==================== [PASSED] fair_ggtt ====================
[20:15:27] ======================== fair_vram ========================
[20:15:27] [PASSED] 1 VF
[20:15:27] [PASSED] 2 VFs
[20:15:27] [PASSED] 3 VFs
[20:15:27] [PASSED] 4 VFs
[20:15:27] [PASSED] 5 VFs
[20:15:27] [PASSED] 6 VFs
[20:15:27] [PASSED] 7 VFs
[20:15:27] [PASSED] 8 VFs
[20:15:27] [PASSED] 9 VFs
[20:15:27] [PASSED] 10 VFs
[20:15:27] [PASSED] 11 VFs
[20:15:27] [PASSED] 12 VFs
[20:15:27] [PASSED] 13 VFs
[20:15:27] [PASSED] 14 VFs
[20:15:27] [PASSED] 15 VFs
[20:15:27] [PASSED] 16 VFs
[20:15:27] [PASSED] 17 VFs
[20:15:27] [PASSED] 18 VFs
[20:15:27] [PASSED] 19 VFs
[20:15:27] [PASSED] 20 VFs
[20:15:27] [PASSED] 21 VFs
[20:15:27] [PASSED] 22 VFs
[20:15:27] [PASSED] 23 VFs
[20:15:27] [PASSED] 24 VFs
[20:15:27] [PASSED] 25 VFs
[20:15:27] [PASSED] 26 VFs
[20:15:27] [PASSED] 27 VFs
[20:15:27] [PASSED] 28 VFs
[20:15:27] [PASSED] 29 VFs
[20:15:27] [PASSED] 30 VFs
[20:15:27] [PASSED] 31 VFs
[20:15:27] [PASSED] 32 VFs
[20:15:27] [PASSED] 33 VFs
[20:15:27] [PASSED] 34 VFs
[20:15:27] [PASSED] 35 VFs
[20:15:27] [PASSED] 36 VFs
[20:15:27] [PASSED] 37 VFs
[20:15:27] [PASSED] 38 VFs
[20:15:27] [PASSED] 39 VFs
[20:15:27] [PASSED] 40 VFs
[20:15:27] [PASSED] 41 VFs
[20:15:27] [PASSED] 42 VFs
[20:15:27] [PASSED] 43 VFs
[20:15:27] [PASSED] 44 VFs
[20:15:27] [PASSED] 45 VFs
[20:15:27] [PASSED] 46 VFs
[20:15:27] [PASSED] 47 VFs
[20:15:27] [PASSED] 48 VFs
[20:15:27] [PASSED] 49 VFs
[20:15:27] [PASSED] 50 VFs
[20:15:27] [PASSED] 51 VFs
[20:15:27] [PASSED] 52 VFs
[20:15:27] [PASSED] 53 VFs
[20:15:27] [PASSED] 54 VFs
[20:15:27] [PASSED] 55 VFs
[20:15:27] [PASSED] 56 VFs
[20:15:27] [PASSED] 57 VFs
[20:15:27] [PASSED] 58 VFs
[20:15:27] [PASSED] 59 VFs
[20:15:27] [PASSED] 60 VFs
[20:15:27] [PASSED] 61 VFs
[20:15:27] [PASSED] 62 VFs
[20:15:27] [PASSED] 63 VFs
[20:15:27] ==================== [PASSED] fair_vram ====================
[20:15:27] ================== [PASSED] pf_gt_config ===================
[20:15:27] ===================== lmtt (1 subtest) =====================
[20:15:27] ======================== test_ops =========================
[20:15:27] [PASSED] 2-level
[20:15:27] [PASSED] multi-level
[20:15:27] ==================== [PASSED] test_ops =====================
[20:15:27] ====================== [PASSED] lmtt =======================
[20:15:27] ================= pf_service (11 subtests) =================
[20:15:27] [PASSED] pf_negotiate_any
[20:15:27] [PASSED] pf_negotiate_base_match
[20:15:27] [PASSED] pf_negotiate_base_newer
[20:15:27] [PASSED] pf_negotiate_base_next
[20:15:27] [SKIPPED] pf_negotiate_base_older
[20:15:27] [PASSED] pf_negotiate_base_prev
[20:15:27] [PASSED] pf_negotiate_latest_match
[20:15:27] [PASSED] pf_negotiate_latest_newer
[20:15:27] [PASSED] pf_negotiate_latest_next
[20:15:27] [SKIPPED] pf_negotiate_latest_older
[20:15:27] [SKIPPED] pf_negotiate_latest_prev
[20:15:27] =================== [PASSED] pf_service ====================
[20:15:27] ================= xe_guc_g2g (2 subtests) ==================
[20:15:27] ============== xe_live_guc_g2g_kunit_default ==============
[20:15:27] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[20:15:27] ============== xe_live_guc_g2g_kunit_allmem ===============
[20:15:27] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[20:15:27] =================== [SKIPPED] xe_guc_g2g ===================
[20:15:27] =================== xe_mocs (2 subtests) ===================
[20:15:27] ================ xe_live_mocs_kernel_kunit ================
[20:15:27] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[20:15:27] ================ xe_live_mocs_reset_kunit =================
[20:15:27] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[20:15:27] ==================== [SKIPPED] xe_mocs =====================
[20:15:27] ================= xe_migrate (2 subtests) ==================
[20:15:27] ================= xe_migrate_sanity_kunit =================
[20:15:27] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[20:15:27] ================== xe_validate_ccs_kunit ==================
[20:15:27] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[20:15:27] =================== [SKIPPED] xe_migrate ===================
[20:15:27] ================== xe_dma_buf (1 subtest) ==================
[20:15:27] ==================== xe_dma_buf_kunit =====================
[20:15:27] ================ [SKIPPED] xe_dma_buf_kunit ================
[20:15:27] =================== [SKIPPED] xe_dma_buf ===================
[20:15:27] ================= xe_bo_shrink (1 subtest) =================
[20:15:27] =================== xe_bo_shrink_kunit ====================
[20:15:27] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[20:15:27] ================== [SKIPPED] xe_bo_shrink ==================
[20:15:27] ==================== xe_bo (2 subtests) ====================
[20:15:27] ================== xe_ccs_migrate_kunit ===================
[20:15:27] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[20:15:27] ==================== xe_bo_evict_kunit ====================
[20:15:27] =============== [SKIPPED] xe_bo_evict_kunit ================
[20:15:27] ===================== [SKIPPED] xe_bo ======================
[20:15:27] ==================== args (13 subtests) ====================
[20:15:27] [PASSED] count_args_test
[20:15:27] [PASSED] call_args_example
[20:15:27] [PASSED] call_args_test
[20:15:27] [PASSED] drop_first_arg_example
[20:15:27] [PASSED] drop_first_arg_test
[20:15:27] [PASSED] first_arg_example
[20:15:27] [PASSED] first_arg_test
[20:15:27] [PASSED] last_arg_example
[20:15:27] [PASSED] last_arg_test
[20:15:27] [PASSED] pick_arg_example
[20:15:27] [PASSED] if_args_example
[20:15:27] [PASSED] if_args_test
[20:15:27] [PASSED] sep_comma_example
[20:15:27] ====================== [PASSED] args =======================
[20:15:27] =================== xe_pci (3 subtests) ====================
[20:15:27] ==================== check_graphics_ip ====================
[20:15:27] [PASSED] 12.00 Xe_LP
[20:15:27] [PASSED] 12.10 Xe_LP+
[20:15:27] [PASSED] 12.55 Xe_HPG
[20:15:27] [PASSED] 12.60 Xe_HPC
[20:15:27] [PASSED] 12.70 Xe_LPG
[20:15:27] [PASSED] 12.71 Xe_LPG
[20:15:27] [PASSED] 12.74 Xe_LPG+
[20:15:27] [PASSED] 20.01 Xe2_HPG
[20:15:27] [PASSED] 20.02 Xe2_HPG
[20:15:27] [PASSED] 20.04 Xe2_LPG
[20:15:27] [PASSED] 30.00 Xe3_LPG
[20:15:27] [PASSED] 30.01 Xe3_LPG
[20:15:27] [PASSED] 30.03 Xe3_LPG
[20:15:27] [PASSED] 30.04 Xe3_LPG
[20:15:27] [PASSED] 30.05 Xe3_LPG
[20:15:27] [PASSED] 35.10 Xe3p_LPG
[20:15:27] [PASSED] 35.11 Xe3p_XPC
[20:15:27] ================ [PASSED] check_graphics_ip ================
[20:15:27] ===================== check_media_ip ======================
[20:15:27] [PASSED] 12.00 Xe_M
[20:15:27] [PASSED] 12.55 Xe_HPM
[20:15:27] [PASSED] 13.00 Xe_LPM+
[20:15:27] [PASSED] 13.01 Xe2_HPM
[20:15:27] [PASSED] 20.00 Xe2_LPM
[20:15:27] [PASSED] 30.00 Xe3_LPM
[20:15:27] [PASSED] 30.02 Xe3_LPM
[20:15:27] [PASSED] 35.00 Xe3p_LPM
[20:15:27] [PASSED] 35.03 Xe3p_HPM
[20:15:27] ================= [PASSED] check_media_ip ==================
[20:15:27] =================== check_platform_desc ===================
[20:15:27] [PASSED] 0x9A60 (TIGERLAKE)
[20:15:27] [PASSED] 0x9A68 (TIGERLAKE)
[20:15:27] [PASSED] 0x9A70 (TIGERLAKE)
[20:15:27] [PASSED] 0x9A40 (TIGERLAKE)
[20:15:27] [PASSED] 0x9A49 (TIGERLAKE)
[20:15:27] [PASSED] 0x9A59 (TIGERLAKE)
[20:15:27] [PASSED] 0x9A78 (TIGERLAKE)
[20:15:27] [PASSED] 0x9AC0 (TIGERLAKE)
[20:15:27] [PASSED] 0x9AC9 (TIGERLAKE)
[20:15:27] [PASSED] 0x9AD9 (TIGERLAKE)
[20:15:27] [PASSED] 0x9AF8 (TIGERLAKE)
[20:15:27] [PASSED] 0x4C80 (ROCKETLAKE)
[20:15:27] [PASSED] 0x4C8A (ROCKETLAKE)
[20:15:27] [PASSED] 0x4C8B (ROCKETLAKE)
[20:15:27] [PASSED] 0x4C8C (ROCKETLAKE)
[20:15:27] [PASSED] 0x4C90 (ROCKETLAKE)
[20:15:27] [PASSED] 0x4C9A (ROCKETLAKE)
[20:15:27] [PASSED] 0x4680 (ALDERLAKE_S)
[20:15:27] [PASSED] 0x4682 (ALDERLAKE_S)
[20:15:27] [PASSED] 0x4688 (ALDERLAKE_S)
[20:15:27] [PASSED] 0x468A (ALDERLAKE_S)
[20:15:27] [PASSED] 0x468B (ALDERLAKE_S)
[20:15:27] [PASSED] 0x4690 (ALDERLAKE_S)
[20:15:27] [PASSED] 0x4692 (ALDERLAKE_S)
[20:15:27] [PASSED] 0x4693 (ALDERLAKE_S)
[20:15:27] [PASSED] 0x46A0 (ALDERLAKE_P)
[20:15:27] [PASSED] 0x46A1 (ALDERLAKE_P)
[20:15:27] [PASSED] 0x46A2 (ALDERLAKE_P)
[20:15:27] [PASSED] 0x46A3 (ALDERLAKE_P)
[20:15:27] [PASSED] 0x46A6 (ALDERLAKE_P)
[20:15:27] [PASSED] 0x46A8 (ALDERLAKE_P)
[20:15:27] [PASSED] 0x46AA (ALDERLAKE_P)
[20:15:27] [PASSED] 0x462A (ALDERLAKE_P)
[20:15:27] [PASSED] 0x4626 (ALDERLAKE_P)
[20:15:27] [PASSED] 0x4628 (ALDERLAKE_P)
[20:15:27] [PASSED] 0x46B0 (ALDERLAKE_P)
[20:15:27] [PASSED] 0x46B1 (ALDERLAKE_P)
[20:15:27] [PASSED] 0x46B2 (ALDERLAKE_P)
[20:15:27] [PASSED] 0x46B3 (ALDERLAKE_P)
[20:15:27] [PASSED] 0x46C0 (ALDERLAKE_P)
[20:15:27] [PASSED] 0x46C1 (ALDERLAKE_P)
[20:15:27] [PASSED] 0x46C2 (ALDERLAKE_P)
[20:15:27] [PASSED] 0x46C3 (ALDERLAKE_P)
[20:15:27] [PASSED] 0x46D0 (ALDERLAKE_N)
[20:15:27] [PASSED] 0x46D1 (ALDERLAKE_N)
[20:15:27] [PASSED] 0x46D2 (ALDERLAKE_N)
[20:15:27] [PASSED] 0x46D3 (ALDERLAKE_N)
[20:15:27] [PASSED] 0x46D4 (ALDERLAKE_N)
[20:15:27] [PASSED] 0xA721 (ALDERLAKE_P)
[20:15:27] [PASSED] 0xA7A1 (ALDERLAKE_P)
[20:15:27] [PASSED] 0xA7A9 (ALDERLAKE_P)
[20:15:27] [PASSED] 0xA7AC (ALDERLAKE_P)
[20:15:27] [PASSED] 0xA7AD (ALDERLAKE_P)
[20:15:27] [PASSED] 0xA720 (ALDERLAKE_P)
[20:15:27] [PASSED] 0xA7A0 (ALDERLAKE_P)
[20:15:27] [PASSED] 0xA7A8 (ALDERLAKE_P)
[20:15:27] [PASSED] 0xA7AA (ALDERLAKE_P)
[20:15:27] [PASSED] 0xA7AB (ALDERLAKE_P)
[20:15:27] [PASSED] 0xA780 (ALDERLAKE_S)
[20:15:27] [PASSED] 0xA781 (ALDERLAKE_S)
[20:15:27] [PASSED] 0xA782 (ALDERLAKE_S)
[20:15:27] [PASSED] 0xA783 (ALDERLAKE_S)
[20:15:27] [PASSED] 0xA788 (ALDERLAKE_S)
[20:15:27] [PASSED] 0xA789 (ALDERLAKE_S)
[20:15:27] [PASSED] 0xA78A (ALDERLAKE_S)
[20:15:27] [PASSED] 0xA78B (ALDERLAKE_S)
[20:15:27] [PASSED] 0x4905 (DG1)
[20:15:27] [PASSED] 0x4906 (DG1)
[20:15:27] [PASSED] 0x4907 (DG1)
[20:15:27] [PASSED] 0x4908 (DG1)
[20:15:27] [PASSED] 0x4909 (DG1)
[20:15:27] [PASSED] 0x56C0 (DG2)
[20:15:27] [PASSED] 0x56C2 (DG2)
[20:15:27] [PASSED] 0x56C1 (DG2)
[20:15:27] [PASSED] 0x7D51 (METEORLAKE)
[20:15:27] [PASSED] 0x7DD1 (METEORLAKE)
[20:15:27] [PASSED] 0x7D41 (METEORLAKE)
[20:15:27] [PASSED] 0x7D67 (METEORLAKE)
[20:15:27] [PASSED] 0xB640 (METEORLAKE)
[20:15:27] [PASSED] 0x56A0 (DG2)
[20:15:27] [PASSED] 0x56A1 (DG2)
[20:15:27] [PASSED] 0x56A2 (DG2)
[20:15:27] [PASSED] 0x56BE (DG2)
[20:15:27] [PASSED] 0x56BF (DG2)
[20:15:27] [PASSED] 0x5690 (DG2)
[20:15:27] [PASSED] 0x5691 (DG2)
[20:15:27] [PASSED] 0x5692 (DG2)
[20:15:27] [PASSED] 0x56A5 (DG2)
[20:15:27] [PASSED] 0x56A6 (DG2)
[20:15:27] [PASSED] 0x56B0 (DG2)
[20:15:27] [PASSED] 0x56B1 (DG2)
[20:15:27] [PASSED] 0x56BA (DG2)
[20:15:27] [PASSED] 0x56BB (DG2)
[20:15:27] [PASSED] 0x56BC (DG2)
[20:15:27] [PASSED] 0x56BD (DG2)
[20:15:27] [PASSED] 0x5693 (DG2)
[20:15:27] [PASSED] 0x5694 (DG2)
[20:15:27] [PASSED] 0x5695 (DG2)
[20:15:27] [PASSED] 0x56A3 (DG2)
[20:15:27] [PASSED] 0x56A4 (DG2)
[20:15:27] [PASSED] 0x56B2 (DG2)
[20:15:27] [PASSED] 0x56B3 (DG2)
[20:15:27] [PASSED] 0x5696 (DG2)
[20:15:27] [PASSED] 0x5697 (DG2)
[20:15:27] [PASSED] 0xB69 (PVC)
[20:15:27] [PASSED] 0xB6E (PVC)
[20:15:27] [PASSED] 0xBD4 (PVC)
[20:15:27] [PASSED] 0xBD5 (PVC)
[20:15:27] [PASSED] 0xBD6 (PVC)
[20:15:27] [PASSED] 0xBD7 (PVC)
[20:15:27] [PASSED] 0xBD8 (PVC)
[20:15:27] [PASSED] 0xBD9 (PVC)
[20:15:27] [PASSED] 0xBDA (PVC)
[20:15:27] [PASSED] 0xBDB (PVC)
[20:15:27] [PASSED] 0xBE0 (PVC)
[20:15:27] [PASSED] 0xBE1 (PVC)
[20:15:27] [PASSED] 0xBE5 (PVC)
[20:15:27] [PASSED] 0x7D40 (METEORLAKE)
[20:15:27] [PASSED] 0x7D45 (METEORLAKE)
[20:15:27] [PASSED] 0x7D55 (METEORLAKE)
[20:15:27] [PASSED] 0x7D60 (METEORLAKE)
[20:15:27] [PASSED] 0x7DD5 (METEORLAKE)
[20:15:27] [PASSED] 0x6420 (LUNARLAKE)
[20:15:27] [PASSED] 0x64A0 (LUNARLAKE)
[20:15:27] [PASSED] 0x64B0 (LUNARLAKE)
[20:15:27] [PASSED] 0xE202 (BATTLEMAGE)
[20:15:27] [PASSED] 0xE209 (BATTLEMAGE)
[20:15:27] [PASSED] 0xE20B (BATTLEMAGE)
[20:15:27] [PASSED] 0xE20C (BATTLEMAGE)
[20:15:27] [PASSED] 0xE20D (BATTLEMAGE)
[20:15:27] [PASSED] 0xE210 (BATTLEMAGE)
[20:15:27] [PASSED] 0xE211 (BATTLEMAGE)
[20:15:27] [PASSED] 0xE212 (BATTLEMAGE)
[20:15:27] [PASSED] 0xE216 (BATTLEMAGE)
[20:15:27] [PASSED] 0xE220 (BATTLEMAGE)
[20:15:27] [PASSED] 0xE221 (BATTLEMAGE)
[20:15:27] [PASSED] 0xE222 (BATTLEMAGE)
[20:15:27] [PASSED] 0xE223 (BATTLEMAGE)
[20:15:27] [PASSED] 0xB080 (PANTHERLAKE)
[20:15:27] [PASSED] 0xB081 (PANTHERLAKE)
[20:15:27] [PASSED] 0xB082 (PANTHERLAKE)
[20:15:27] [PASSED] 0xB083 (PANTHERLAKE)
[20:15:27] [PASSED] 0xB084 (PANTHERLAKE)
[20:15:27] [PASSED] 0xB085 (PANTHERLAKE)
[20:15:27] [PASSED] 0xB086 (PANTHERLAKE)
[20:15:27] [PASSED] 0xB087 (PANTHERLAKE)
[20:15:27] [PASSED] 0xB08F (PANTHERLAKE)
[20:15:27] [PASSED] 0xB090 (PANTHERLAKE)
[20:15:27] [PASSED] 0xB0A0 (PANTHERLAKE)
[20:15:27] [PASSED] 0xB0B0 (PANTHERLAKE)
[20:15:27] [PASSED] 0xFD80 (PANTHERLAKE)
[20:15:27] [PASSED] 0xFD81 (PANTHERLAKE)
[20:15:27] [PASSED] 0xD740 (NOVALAKE_S)
[20:15:27] [PASSED] 0xD741 (NOVALAKE_S)
[20:15:27] [PASSED] 0xD742 (NOVALAKE_S)
[20:15:27] [PASSED] 0xD743 (NOVALAKE_S)
[20:15:27] [PASSED] 0xD744 (NOVALAKE_S)
[20:15:27] [PASSED] 0xD745 (NOVALAKE_S)
[20:15:27] [PASSED] 0x674C (CRESCENTISLAND)
[20:15:27] [PASSED] 0x674D (CRESCENTISLAND)
[20:15:27] [PASSED] 0x674E (CRESCENTISLAND)
[20:15:27] [PASSED] 0x674F (CRESCENTISLAND)
[20:15:27] [PASSED] 0x6750 (CRESCENTISLAND)
[20:15:27] [PASSED] 0xD750 (NOVALAKE_P)
[20:15:27] [PASSED] 0xD751 (NOVALAKE_P)
[20:15:27] [PASSED] 0xD752 (NOVALAKE_P)
[20:15:27] [PASSED] 0xD753 (NOVALAKE_P)
[20:15:27] [PASSED] 0xD754 (NOVALAKE_P)
[20:15:27] [PASSED] 0xD755 (NOVALAKE_P)
[20:15:27] [PASSED] 0xD756 (NOVALAKE_P)
[20:15:27] [PASSED] 0xD757 (NOVALAKE_P)
[20:15:27] [PASSED] 0xD75F (NOVALAKE_P)
[20:15:27] =============== [PASSED] check_platform_desc ===============
[20:15:27] ===================== [PASSED] xe_pci ======================
[20:15:27] =================== xe_rtp (2 subtests) ====================
[20:15:27] =============== xe_rtp_process_to_sr_tests ================
[20:15:27] [PASSED] coalesce-same-reg
[20:15:27] [PASSED] no-match-no-add
[20:15:27] [PASSED] match-or
[20:15:27] [PASSED] match-or-xfail
[20:15:27] [PASSED] no-match-no-add-multiple-rules
[20:15:27] [PASSED] two-regs-two-entries
[20:15:27] [PASSED] clr-one-set-other
[20:15:27] [PASSED] set-field
[20:15:27] [PASSED] conflict-duplicate
[20:15:27] [PASSED] conflict-not-disjoint
[20:15:27] [PASSED] conflict-reg-type
[20:15:27] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[20:15:27] ================== xe_rtp_process_tests ===================
[20:15:27] [PASSED] active1
[20:15:27] [PASSED] active2
[20:15:27] [PASSED] active-inactive
[20:15:27] [PASSED] inactive-active
[20:15:27] [PASSED] inactive-1st_or_active-inactive
[20:15:27] [PASSED] inactive-2nd_or_active-inactive
[20:15:27] [PASSED] inactive-last_or_active-inactive
[20:15:27] [PASSED] inactive-no_or_active-inactive
[20:15:27] ============== [PASSED] xe_rtp_process_tests ===============
[20:15:27] ===================== [PASSED] xe_rtp ======================
[20:15:27] ==================== xe_wa (1 subtest) =====================
[20:15:27] ======================== xe_wa_gt =========================
[20:15:27] [PASSED] TIGERLAKE B0
[20:15:27] [PASSED] DG1 A0
[20:15:27] [PASSED] DG1 B0
[20:15:27] [PASSED] ALDERLAKE_S A0
[20:15:27] [PASSED] ALDERLAKE_S B0
[20:15:27] [PASSED] ALDERLAKE_S C0
[20:15:27] [PASSED] ALDERLAKE_S D0
[20:15:27] [PASSED] ALDERLAKE_P A0
[20:15:27] [PASSED] ALDERLAKE_P B0
[20:15:27] [PASSED] ALDERLAKE_P C0
[20:15:27] [PASSED] ALDERLAKE_S RPLS D0
[20:15:27] [PASSED] ALDERLAKE_P RPLU E0
[20:15:27] [PASSED] DG2 G10 C0
[20:15:27] [PASSED] DG2 G11 B1
[20:15:27] [PASSED] DG2 G12 A1
[20:15:27] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[20:15:27] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[20:15:27] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[20:15:27] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[20:15:27] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[20:15:27] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[20:15:27] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[20:15:27] ==================== [PASSED] xe_wa_gt =====================
[20:15:27] ====================== [PASSED] xe_wa ======================
[20:15:27] ============================================================
[20:15:27] Testing complete. Ran 601 tests: passed: 583, skipped: 18
[20:15:27] Elapsed time: 44.037s total, 4.344s configuring, 39.017s building, 0.655s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[20:15:27] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[20:15:29] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[20:15:54] Starting KUnit Kernel (1/1)...
[20:15:54] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[20:15:54] ============ drm_test_pick_cmdline (2 subtests) ============
[20:15:54] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[20:15:54] =============== drm_test_pick_cmdline_named ===============
[20:15:54] [PASSED] NTSC
[20:15:54] [PASSED] NTSC-J
[20:15:54] [PASSED] PAL
[20:15:54] [PASSED] PAL-M
[20:15:54] =========== [PASSED] drm_test_pick_cmdline_named ===========
[20:15:54] ============== [PASSED] drm_test_pick_cmdline ==============
[20:15:54] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[20:15:54] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[20:15:54] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[20:15:54] =========== drm_validate_clone_mode (2 subtests) ===========
[20:15:54] ============== drm_test_check_in_clone_mode ===============
[20:15:54] [PASSED] in_clone_mode
[20:15:54] [PASSED] not_in_clone_mode
[20:15:54] ========== [PASSED] drm_test_check_in_clone_mode ===========
[20:15:54] =============== drm_test_check_valid_clones ===============
[20:15:54] [PASSED] not_in_clone_mode
[20:15:54] [PASSED] valid_clone
[20:15:54] [PASSED] invalid_clone
[20:15:54] =========== [PASSED] drm_test_check_valid_clones ===========
[20:15:54] ============= [PASSED] drm_validate_clone_mode =============
[20:15:54] ============= drm_validate_modeset (1 subtest) =============
[20:15:54] [PASSED] drm_test_check_connector_changed_modeset
[20:15:54] ============== [PASSED] drm_validate_modeset ===============
[20:15:54] ====== drm_test_bridge_get_current_state (2 subtests) ======
[20:15:54] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[20:15:54] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[20:15:54] ======== [PASSED] drm_test_bridge_get_current_state ========
[20:15:54] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[20:15:54] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[20:15:54] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[20:15:54] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[20:15:54] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[20:15:54] ============== drm_bridge_alloc (2 subtests) ===============
[20:15:54] [PASSED] drm_test_drm_bridge_alloc_basic
[20:15:54] [PASSED] drm_test_drm_bridge_alloc_get_put
[20:15:54] ================ [PASSED] drm_bridge_alloc =================
[20:15:54] ============= drm_cmdline_parser (40 subtests) =============
[20:15:54] [PASSED] drm_test_cmdline_force_d_only
[20:15:54] [PASSED] drm_test_cmdline_force_D_only_dvi
[20:15:54] [PASSED] drm_test_cmdline_force_D_only_hdmi
[20:15:54] [PASSED] drm_test_cmdline_force_D_only_not_digital
[20:15:54] [PASSED] drm_test_cmdline_force_e_only
[20:15:54] [PASSED] drm_test_cmdline_res
[20:15:54] [PASSED] drm_test_cmdline_res_vesa
[20:15:54] [PASSED] drm_test_cmdline_res_vesa_rblank
[20:15:54] [PASSED] drm_test_cmdline_res_rblank
[20:15:54] [PASSED] drm_test_cmdline_res_bpp
[20:15:54] [PASSED] drm_test_cmdline_res_refresh
[20:15:54] [PASSED] drm_test_cmdline_res_bpp_refresh
[20:15:54] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[20:15:54] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[20:15:54] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[20:15:54] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[20:15:54] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[20:15:54] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[20:15:54] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[20:15:54] [PASSED] drm_test_cmdline_res_margins_force_on
[20:15:54] [PASSED] drm_test_cmdline_res_vesa_margins
[20:15:54] [PASSED] drm_test_cmdline_name
[20:15:54] [PASSED] drm_test_cmdline_name_bpp
[20:15:54] [PASSED] drm_test_cmdline_name_option
[20:15:54] [PASSED] drm_test_cmdline_name_bpp_option
[20:15:54] [PASSED] drm_test_cmdline_rotate_0
[20:15:54] [PASSED] drm_test_cmdline_rotate_90
[20:15:54] [PASSED] drm_test_cmdline_rotate_180
[20:15:54] [PASSED] drm_test_cmdline_rotate_270
[20:15:54] [PASSED] drm_test_cmdline_hmirror
[20:15:54] [PASSED] drm_test_cmdline_vmirror
[20:15:54] [PASSED] drm_test_cmdline_margin_options
[20:15:54] [PASSED] drm_test_cmdline_multiple_options
[20:15:54] [PASSED] drm_test_cmdline_bpp_extra_and_option
[20:15:54] [PASSED] drm_test_cmdline_extra_and_option
[20:15:54] [PASSED] drm_test_cmdline_freestanding_options
[20:15:54] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[20:15:54] [PASSED] drm_test_cmdline_panel_orientation
[20:15:54] ================ drm_test_cmdline_invalid =================
[20:15:54] [PASSED] margin_only
[20:15:54] [PASSED] interlace_only
[20:15:54] [PASSED] res_missing_x
[20:15:54] [PASSED] res_missing_y
[20:15:54] [PASSED] res_bad_y
[20:15:54] [PASSED] res_missing_y_bpp
[20:15:54] [PASSED] res_bad_bpp
[20:15:54] [PASSED] res_bad_refresh
[20:15:54] [PASSED] res_bpp_refresh_force_on_off
[20:15:54] [PASSED] res_invalid_mode
[20:15:54] [PASSED] res_bpp_wrong_place_mode
[20:15:54] [PASSED] name_bpp_refresh
[20:15:54] [PASSED] name_refresh
[20:15:54] [PASSED] name_refresh_wrong_mode
[20:15:54] [PASSED] name_refresh_invalid_mode
[20:15:54] [PASSED] rotate_multiple
[20:15:54] [PASSED] rotate_invalid_val
[20:15:54] [PASSED] rotate_truncated
[20:15:54] [PASSED] invalid_option
[20:15:54] [PASSED] invalid_tv_option
[20:15:54] [PASSED] truncated_tv_option
[20:15:54] ============ [PASSED] drm_test_cmdline_invalid =============
[20:15:54] =============== drm_test_cmdline_tv_options ===============
[20:15:54] [PASSED] NTSC
[20:15:54] [PASSED] NTSC_443
[20:15:54] [PASSED] NTSC_J
[20:15:54] [PASSED] PAL
[20:15:54] [PASSED] PAL_M
[20:15:54] [PASSED] PAL_N
[20:15:54] [PASSED] SECAM
[20:15:54] [PASSED] MONO_525
[20:15:54] [PASSED] MONO_625
[20:15:54] =========== [PASSED] drm_test_cmdline_tv_options ===========
[20:15:54] =============== [PASSED] drm_cmdline_parser ================
[20:15:54] ========== drmm_connector_hdmi_init (20 subtests) ==========
[20:15:54] [PASSED] drm_test_connector_hdmi_init_valid
[20:15:54] [PASSED] drm_test_connector_hdmi_init_bpc_8
[20:15:54] [PASSED] drm_test_connector_hdmi_init_bpc_10
[20:15:54] [PASSED] drm_test_connector_hdmi_init_bpc_12
[20:15:54] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[20:15:54] [PASSED] drm_test_connector_hdmi_init_bpc_null
[20:15:54] [PASSED] drm_test_connector_hdmi_init_formats_empty
[20:15:54] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[20:15:54] === drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[20:15:54] [PASSED] supported_formats=0x9 yuv420_allowed=1
[20:15:54] [PASSED] supported_formats=0x9 yuv420_allowed=0
[20:15:54] [PASSED] supported_formats=0x5 yuv420_allowed=1
[20:15:54] [PASSED] supported_formats=0x5 yuv420_allowed=0
[20:15:54] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[20:15:54] [PASSED] drm_test_connector_hdmi_init_null_ddc
[20:15:54] [PASSED] drm_test_connector_hdmi_init_null_product
[20:15:54] [PASSED] drm_test_connector_hdmi_init_null_vendor
[20:15:54] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[20:15:54] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[20:15:54] [PASSED] drm_test_connector_hdmi_init_product_valid
[20:15:54] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[20:15:54] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[20:15:54] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[20:15:54] ========= drm_test_connector_hdmi_init_type_valid =========
[20:15:54] [PASSED] HDMI-A
[20:15:54] [PASSED] HDMI-B
[20:15:54] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[20:15:54] ======== drm_test_connector_hdmi_init_type_invalid ========
[20:15:54] [PASSED] Unknown
[20:15:54] [PASSED] VGA
[20:15:54] [PASSED] DVI-I
[20:15:54] [PASSED] DVI-D
[20:15:54] [PASSED] DVI-A
[20:15:54] [PASSED] Composite
[20:15:54] [PASSED] SVIDEO
[20:15:54] [PASSED] LVDS
[20:15:54] [PASSED] Component
[20:15:54] [PASSED] DIN
[20:15:54] [PASSED] DP
[20:15:54] [PASSED] TV
[20:15:54] [PASSED] eDP
[20:15:54] [PASSED] Virtual
[20:15:54] [PASSED] DSI
[20:15:54] [PASSED] DPI
[20:15:54] [PASSED] Writeback
[20:15:54] [PASSED] SPI
[20:15:54] [PASSED] USB
[20:15:54] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[20:15:54] ============ [PASSED] drmm_connector_hdmi_init =============
[20:15:54] ============= drmm_connector_init (3 subtests) =============
[20:15:54] [PASSED] drm_test_drmm_connector_init
[20:15:54] [PASSED] drm_test_drmm_connector_init_null_ddc
[20:15:54] ========= drm_test_drmm_connector_init_type_valid =========
[20:15:54] [PASSED] Unknown
[20:15:54] [PASSED] VGA
[20:15:54] [PASSED] DVI-I
[20:15:54] [PASSED] DVI-D
[20:15:54] [PASSED] DVI-A
[20:15:54] [PASSED] Composite
[20:15:54] [PASSED] SVIDEO
[20:15:54] [PASSED] LVDS
[20:15:54] [PASSED] Component
[20:15:54] [PASSED] DIN
[20:15:54] [PASSED] DP
[20:15:54] [PASSED] HDMI-A
[20:15:54] [PASSED] HDMI-B
[20:15:54] [PASSED] TV
[20:15:54] [PASSED] eDP
[20:15:54] [PASSED] Virtual
[20:15:54] [PASSED] DSI
[20:15:54] [PASSED] DPI
[20:15:54] [PASSED] Writeback
[20:15:54] [PASSED] SPI
[20:15:54] [PASSED] USB
[20:15:54] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[20:15:54] =============== [PASSED] drmm_connector_init ===============
[20:15:54] ========= drm_connector_dynamic_init (6 subtests) ==========
[20:15:54] [PASSED] drm_test_drm_connector_dynamic_init
[20:15:54] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[20:15:54] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[20:15:54] [PASSED] drm_test_drm_connector_dynamic_init_properties
[20:15:54] ===== drm_test_drm_connector_dynamic_init_type_valid ======
[20:15:54] [PASSED] Unknown
[20:15:54] [PASSED] VGA
[20:15:54] [PASSED] DVI-I
[20:15:54] [PASSED] DVI-D
[20:15:54] [PASSED] DVI-A
[20:15:54] [PASSED] Composite
[20:15:54] [PASSED] SVIDEO
[20:15:54] [PASSED] LVDS
[20:15:54] [PASSED] Component
[20:15:54] [PASSED] DIN
[20:15:54] [PASSED] DP
[20:15:54] [PASSED] HDMI-A
[20:15:54] [PASSED] HDMI-B
[20:15:54] [PASSED] TV
[20:15:54] [PASSED] eDP
[20:15:54] [PASSED] Virtual
[20:15:54] [PASSED] DSI
[20:15:54] [PASSED] DPI
[20:15:54] [PASSED] Writeback
[20:15:54] [PASSED] SPI
[20:15:54] [PASSED] USB
[20:15:54] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[20:15:54] ======== drm_test_drm_connector_dynamic_init_name =========
[20:15:54] [PASSED] Unknown
[20:15:54] [PASSED] VGA
[20:15:54] [PASSED] DVI-I
[20:15:54] [PASSED] DVI-D
[20:15:54] [PASSED] DVI-A
[20:15:54] [PASSED] Composite
[20:15:54] [PASSED] SVIDEO
[20:15:54] [PASSED] LVDS
[20:15:54] [PASSED] Component
[20:15:54] [PASSED] DIN
[20:15:54] [PASSED] DP
[20:15:54] [PASSED] HDMI-A
[20:15:54] [PASSED] HDMI-B
[20:15:54] [PASSED] TV
[20:15:54] [PASSED] eDP
[20:15:54] [PASSED] Virtual
[20:15:54] [PASSED] DSI
[20:15:54] [PASSED] DPI
[20:15:54] [PASSED] Writeback
[20:15:54] [PASSED] SPI
[20:15:54] [PASSED] USB
[20:15:54] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[20:15:54] =========== [PASSED] drm_connector_dynamic_init ============
[20:15:54] ==== drm_connector_dynamic_register_early (4 subtests) =====
[20:15:54] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[20:15:54] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[20:15:54] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[20:15:54] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[20:15:54] ====== [PASSED] drm_connector_dynamic_register_early =======
[20:15:54] ======= drm_connector_dynamic_register (7 subtests) ========
[20:15:54] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[20:15:54] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[20:15:54] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[20:15:54] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[20:15:54] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[20:15:54] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[20:15:54] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[20:15:54] ========= [PASSED] drm_connector_dynamic_register ==========
[20:15:54] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[20:15:54] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[20:15:54] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[20:15:54] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[20:15:54] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[20:15:54] ========== drm_test_get_tv_mode_from_name_valid ===========
[20:15:54] [PASSED] NTSC
[20:15:54] [PASSED] NTSC-443
[20:15:54] [PASSED] NTSC-J
[20:15:54] [PASSED] PAL
[20:15:54] [PASSED] PAL-M
[20:15:54] [PASSED] PAL-N
[20:15:54] [PASSED] SECAM
[20:15:54] [PASSED] Mono
[20:15:54] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[20:15:54] [PASSED] drm_test_get_tv_mode_from_name_truncated
[20:15:54] ============ [PASSED] drm_get_tv_mode_from_name ============
[20:15:54] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[20:15:54] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[20:15:54] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[20:15:54] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[20:15:54] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[20:15:54] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[20:15:54] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[20:15:54] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid =
[20:15:54] [PASSED] VIC 96
[20:15:54] [PASSED] VIC 97
[20:15:54] [PASSED] VIC 101
[20:15:54] [PASSED] VIC 102
[20:15:54] [PASSED] VIC 106
[20:15:54] [PASSED] VIC 107
[20:15:54] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[20:15:54] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[20:15:54] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[20:15:54] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[20:15:54] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[20:15:54] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[20:15:54] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[20:15:54] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[20:15:54] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name ====
[20:15:54] [PASSED] Automatic
[20:15:54] [PASSED] Full
[20:15:54] [PASSED] Limited 16:235
[20:15:54] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[20:15:54] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[20:15:54] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[20:15:54] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[20:15:54] === drm_test_drm_hdmi_connector_get_output_format_name ====
[20:15:54] [PASSED] RGB
[20:15:54] [PASSED] YUV 4:2:0
[20:15:54] [PASSED] YUV 4:2:2
[20:15:54] [PASSED] YUV 4:4:4
[20:15:54] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[20:15:54] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[20:15:54] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[20:15:54] ============= drm_damage_helper (21 subtests) ==============
[20:15:54] [PASSED] drm_test_damage_iter_no_damage
[20:15:54] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[20:15:54] [PASSED] drm_test_damage_iter_no_damage_src_moved
[20:15:54] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[20:15:54] [PASSED] drm_test_damage_iter_no_damage_not_visible
[20:15:54] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[20:15:54] [PASSED] drm_test_damage_iter_no_damage_no_fb
[20:15:54] [PASSED] drm_test_damage_iter_simple_damage
[20:15:54] [PASSED] drm_test_damage_iter_single_damage
[20:15:54] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[20:15:54] [PASSED] drm_test_damage_iter_single_damage_outside_src
[20:15:54] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[20:15:54] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[20:15:54] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[20:15:54] [PASSED] drm_test_damage_iter_single_damage_src_moved
[20:15:54] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[20:15:54] [PASSED] drm_test_damage_iter_damage
[20:15:54] [PASSED] drm_test_damage_iter_damage_one_intersect
[20:15:54] [PASSED] drm_test_damage_iter_damage_one_outside
[20:15:54] [PASSED] drm_test_damage_iter_damage_src_moved
[20:15:54] [PASSED] drm_test_damage_iter_damage_not_visible
[20:15:54] ================ [PASSED] drm_damage_helper ================
[20:15:54] ============== drm_dp_mst_helper (3 subtests) ==============
[20:15:54] ============== drm_test_dp_mst_calc_pbn_mode ==============
[20:15:54] [PASSED] Clock 154000 BPP 30 DSC disabled
[20:15:54] [PASSED] Clock 234000 BPP 30 DSC disabled
[20:15:54] [PASSED] Clock 297000 BPP 24 DSC disabled
[20:15:54] [PASSED] Clock 332880 BPP 24 DSC enabled
[20:15:54] [PASSED] Clock 324540 BPP 24 DSC enabled
[20:15:54] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[20:15:54] ============== drm_test_dp_mst_calc_pbn_div ===============
[20:15:54] [PASSED] Link rate 2000000 lane count 4
[20:15:54] [PASSED] Link rate 2000000 lane count 2
[20:15:54] [PASSED] Link rate 2000000 lane count 1
[20:15:54] [PASSED] Link rate 1350000 lane count 4
[20:15:54] [PASSED] Link rate 1350000 lane count 2
[20:15:54] [PASSED] Link rate 1350000 lane count 1
[20:15:54] [PASSED] Link rate 1000000 lane count 4
[20:15:54] [PASSED] Link rate 1000000 lane count 2
[20:15:54] [PASSED] Link rate 1000000 lane count 1
[20:15:54] [PASSED] Link rate 810000 lane count 4
[20:15:54] [PASSED] Link rate 810000 lane count 2
[20:15:54] [PASSED] Link rate 810000 lane count 1
[20:15:54] [PASSED] Link rate 540000 lane count 4
[20:15:54] [PASSED] Link rate 540000 lane count 2
[20:15:54] [PASSED] Link rate 540000 lane count 1
[20:15:54] [PASSED] Link rate 270000 lane count 4
[20:15:54] [PASSED] Link rate 270000 lane count 2
[20:15:54] [PASSED] Link rate 270000 lane count 1
[20:15:54] [PASSED] Link rate 162000 lane count 4
[20:15:54] [PASSED] Link rate 162000 lane count 2
[20:15:54] [PASSED] Link rate 162000 lane count 1
[20:15:54] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[20:15:54] ========= drm_test_dp_mst_sideband_msg_req_decode =========
[20:15:54] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[20:15:54] [PASSED] DP_POWER_UP_PHY with port number
[20:15:54] [PASSED] DP_POWER_DOWN_PHY with port number
[20:15:54] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[20:15:54] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[20:15:54] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[20:15:54] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[20:15:54] [PASSED] DP_QUERY_PAYLOAD with port number
[20:15:54] [PASSED] DP_QUERY_PAYLOAD with VCPI
[20:15:54] [PASSED] DP_REMOTE_DPCD_READ with port number
[20:15:54] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[20:15:54] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[20:15:54] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[20:15:54] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[20:15:54] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[20:15:54] [PASSED] DP_REMOTE_I2C_READ with port number
[20:15:54] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[20:15:54] [PASSED] DP_REMOTE_I2C_READ with transactions array
[20:15:54] [PASSED] DP_REMOTE_I2C_WRITE with port number
[20:15:54] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[20:15:54] [PASSED] DP_REMOTE_I2C_WRITE with data array
[20:15:54] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[20:15:54] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[20:15:54] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[20:15:54] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[20:15:54] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[20:15:54] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[20:15:54] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[20:15:54] ================ [PASSED] drm_dp_mst_helper ================
[20:15:54] ================== drm_exec (7 subtests) ===================
[20:15:54] [PASSED] sanitycheck
[20:15:54] [PASSED] test_lock
[20:15:54] [PASSED] test_lock_unlock
[20:15:54] [PASSED] test_duplicates
[20:15:54] [PASSED] test_prepare
[20:15:54] [PASSED] test_prepare_array
[20:15:54] [PASSED] test_multiple_loops
[20:15:54] ==================== [PASSED] drm_exec =====================
[20:15:54] =========== drm_format_helper_test (17 subtests) ===========
[20:15:54] ============== drm_test_fb_xrgb8888_to_gray8 ==============
[20:15:54] [PASSED] single_pixel_source_buffer
[20:15:54] [PASSED] single_pixel_clip_rectangle
[20:15:54] [PASSED] well_known_colors
[20:15:54] [PASSED] destination_pitch
[20:15:54] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[20:15:54] ============= drm_test_fb_xrgb8888_to_rgb332 ==============
[20:15:54] [PASSED] single_pixel_source_buffer
[20:15:54] [PASSED] single_pixel_clip_rectangle
[20:15:54] [PASSED] well_known_colors
[20:15:54] [PASSED] destination_pitch
[20:15:54] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[20:15:54] ============= drm_test_fb_xrgb8888_to_rgb565 ==============
[20:15:54] [PASSED] single_pixel_source_buffer
[20:15:54] [PASSED] single_pixel_clip_rectangle
[20:15:54] [PASSED] well_known_colors
[20:15:54] [PASSED] destination_pitch
[20:15:54] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[20:15:54] ============ drm_test_fb_xrgb8888_to_xrgb1555 =============
[20:15:54] [PASSED] single_pixel_source_buffer
[20:15:54] [PASSED] single_pixel_clip_rectangle
[20:15:54] [PASSED] well_known_colors
[20:15:54] [PASSED] destination_pitch
[20:15:54] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[20:15:54] ============ drm_test_fb_xrgb8888_to_argb1555 =============
[20:15:54] [PASSED] single_pixel_source_buffer
[20:15:54] [PASSED] single_pixel_clip_rectangle
[20:15:54] [PASSED] well_known_colors
[20:15:54] [PASSED] destination_pitch
[20:15:54] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[20:15:54] ============ drm_test_fb_xrgb8888_to_rgba5551 =============
[20:15:54] [PASSED] single_pixel_source_buffer
[20:15:54] [PASSED] single_pixel_clip_rectangle
[20:15:54] [PASSED] well_known_colors
[20:15:54] [PASSED] destination_pitch
[20:15:54] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[20:15:54] ============= drm_test_fb_xrgb8888_to_rgb888 ==============
[20:15:54] [PASSED] single_pixel_source_buffer
[20:15:54] [PASSED] single_pixel_clip_rectangle
[20:15:54] [PASSED] well_known_colors
[20:15:54] [PASSED] destination_pitch
[20:15:54] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[20:15:54] ============= drm_test_fb_xrgb8888_to_bgr888 ==============
[20:15:54] [PASSED] single_pixel_source_buffer
[20:15:54] [PASSED] single_pixel_clip_rectangle
[20:15:54] [PASSED] well_known_colors
[20:15:54] [PASSED] destination_pitch
[20:15:54] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[20:15:54] ============ drm_test_fb_xrgb8888_to_argb8888 =============
[20:15:54] [PASSED] single_pixel_source_buffer
[20:15:54] [PASSED] single_pixel_clip_rectangle
[20:15:54] [PASSED] well_known_colors
[20:15:54] [PASSED] destination_pitch
[20:15:54] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[20:15:54] =========== drm_test_fb_xrgb8888_to_xrgb2101010 ===========
[20:15:54] [PASSED] single_pixel_source_buffer
[20:15:54] [PASSED] single_pixel_clip_rectangle
[20:15:54] [PASSED] well_known_colors
[20:15:54] [PASSED] destination_pitch
[20:15:54] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[20:15:54] =========== drm_test_fb_xrgb8888_to_argb2101010 ===========
[20:15:54] [PASSED] single_pixel_source_buffer
[20:15:54] [PASSED] single_pixel_clip_rectangle
[20:15:54] [PASSED] well_known_colors
[20:15:54] [PASSED] destination_pitch
[20:15:54] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[20:15:54] ============== drm_test_fb_xrgb8888_to_mono ===============
[20:15:54] [PASSED] single_pixel_source_buffer
[20:15:54] [PASSED] single_pixel_clip_rectangle
[20:15:54] [PASSED] well_known_colors
[20:15:54] [PASSED] destination_pitch
[20:15:54] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[20:15:54] ==================== drm_test_fb_swab =====================
[20:15:54] [PASSED] single_pixel_source_buffer
[20:15:54] [PASSED] single_pixel_clip_rectangle
[20:15:54] [PASSED] well_known_colors
[20:15:54] [PASSED] destination_pitch
[20:15:54] ================ [PASSED] drm_test_fb_swab =================
[20:15:54] ============ drm_test_fb_xrgb8888_to_xbgr8888 =============
[20:15:54] [PASSED] single_pixel_source_buffer
[20:15:54] [PASSED] single_pixel_clip_rectangle
[20:15:54] [PASSED] well_known_colors
[20:15:54] [PASSED] destination_pitch
[20:15:54] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[20:15:54] ============ drm_test_fb_xrgb8888_to_abgr8888 =============
[20:15:54] [PASSED] single_pixel_source_buffer
[20:15:54] [PASSED] single_pixel_clip_rectangle
[20:15:54] [PASSED] well_known_colors
[20:15:54] [PASSED] destination_pitch
[20:15:54] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[20:15:54] ================= drm_test_fb_clip_offset =================
[20:15:54] [PASSED] pass through
[20:15:54] [PASSED] horizontal offset
[20:15:54] [PASSED] vertical offset
[20:15:54] [PASSED] horizontal and vertical offset
[20:15:54] [PASSED] horizontal offset (custom pitch)
[20:15:54] [PASSED] vertical offset (custom pitch)
[20:15:54] [PASSED] horizontal and vertical offset (custom pitch)
[20:15:54] ============= [PASSED] drm_test_fb_clip_offset =============
[20:15:54] =================== drm_test_fb_memcpy ====================
[20:15:54] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[20:15:54] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[20:15:54] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[20:15:54] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[20:15:54] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[20:15:54] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[20:15:54] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[20:15:54] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[20:15:54] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[20:15:54] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[20:15:54] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[20:15:54] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[20:15:54] =============== [PASSED] drm_test_fb_memcpy ================
[20:15:54] ============= [PASSED] drm_format_helper_test ==============
[20:15:54] ================= drm_format (18 subtests) =================
[20:15:54] [PASSED] drm_test_format_block_width_invalid
[20:15:54] [PASSED] drm_test_format_block_width_one_plane
[20:15:54] [PASSED] drm_test_format_block_width_two_plane
[20:15:54] [PASSED] drm_test_format_block_width_three_plane
[20:15:54] [PASSED] drm_test_format_block_width_tiled
[20:15:54] [PASSED] drm_test_format_block_height_invalid
[20:15:54] [PASSED] drm_test_format_block_height_one_plane
[20:15:54] [PASSED] drm_test_format_block_height_two_plane
[20:15:54] [PASSED] drm_test_format_block_height_three_plane
[20:15:54] [PASSED] drm_test_format_block_height_tiled
[20:15:54] [PASSED] drm_test_format_min_pitch_invalid
[20:15:54] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[20:15:54] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[20:15:54] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[20:15:54] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[20:15:54] [PASSED] drm_test_format_min_pitch_two_plane
[20:15:54] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[20:15:54] [PASSED] drm_test_format_min_pitch_tiled
[20:15:54] =================== [PASSED] drm_format ====================
[20:15:54] ============== drm_framebuffer (10 subtests) ===============
[20:15:54] ========== drm_test_framebuffer_check_src_coords ==========
[20:15:54] [PASSED] Success: source fits into fb
[20:15:54] [PASSED] Fail: overflowing fb with x-axis coordinate
[20:15:54] [PASSED] Fail: overflowing fb with y-axis coordinate
[20:15:54] [PASSED] Fail: overflowing fb with source width
[20:15:54] [PASSED] Fail: overflowing fb with source height
[20:15:54] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[20:15:54] [PASSED] drm_test_framebuffer_cleanup
[20:15:54] =============== drm_test_framebuffer_create ===============
[20:15:54] [PASSED] ABGR8888 normal sizes
[20:15:54] [PASSED] ABGR8888 max sizes
[20:15:54] [PASSED] ABGR8888 pitch greater than min required
[20:15:54] [PASSED] ABGR8888 pitch less than min required
[20:15:54] [PASSED] ABGR8888 Invalid width
[20:15:54] [PASSED] ABGR8888 Invalid buffer handle
[20:15:54] [PASSED] No pixel format
[20:15:54] [PASSED] ABGR8888 Width 0
[20:15:54] [PASSED] ABGR8888 Height 0
[20:15:54] [PASSED] ABGR8888 Out of bound height * pitch combination
[20:15:54] [PASSED] ABGR8888 Large buffer offset
[20:15:54] [PASSED] ABGR8888 Buffer offset for inexistent plane
[20:15:54] [PASSED] ABGR8888 Invalid flag
[20:15:54] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[20:15:54] [PASSED] ABGR8888 Valid buffer modifier
[20:15:54] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[20:15:54] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[20:15:54] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[20:15:54] [PASSED] NV12 Normal sizes
[20:15:54] [PASSED] NV12 Max sizes
[20:15:54] [PASSED] NV12 Invalid pitch
[20:15:54] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[20:15:54] [PASSED] NV12 different modifier per-plane
[20:15:54] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[20:15:54] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[20:15:54] [PASSED] NV12 Modifier for inexistent plane
[20:15:54] [PASSED] NV12 Handle for inexistent plane
[20:15:54] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[20:15:54] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[20:15:54] [PASSED] YVU420 Normal sizes
[20:15:54] [PASSED] YVU420 Max sizes
[20:15:54] [PASSED] YVU420 Invalid pitch
[20:15:54] [PASSED] YVU420 Different pitches
[20:15:54] [PASSED] YVU420 Different buffer offsets/pitches
[20:15:54] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[20:15:54] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[20:15:54] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[20:15:54] [PASSED] YVU420 Valid modifier
[20:15:54] [PASSED] YVU420 Different modifiers per plane
[20:15:54] [PASSED] YVU420 Modifier for inexistent plane
[20:15:54] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[20:15:54] [PASSED] X0L2 Normal sizes
[20:15:54] [PASSED] X0L2 Max sizes
[20:15:54] [PASSED] X0L2 Invalid pitch
[20:15:54] [PASSED] X0L2 Pitch greater than minimum required
[20:15:54] [PASSED] X0L2 Handle for inexistent plane
[20:15:54] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[20:15:54] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[20:15:54] [PASSED] X0L2 Valid modifier
[20:15:54] [PASSED] X0L2 Modifier for inexistent plane
[20:15:54] =========== [PASSED] drm_test_framebuffer_create ===========
[20:15:54] [PASSED] drm_test_framebuffer_free
[20:15:54] [PASSED] drm_test_framebuffer_init
[20:15:54] [PASSED] drm_test_framebuffer_init_bad_format
[20:15:54] [PASSED] drm_test_framebuffer_init_dev_mismatch
[20:15:54] [PASSED] drm_test_framebuffer_lookup
[20:15:54] [PASSED] drm_test_framebuffer_lookup_inexistent
[20:15:54] [PASSED] drm_test_framebuffer_modifiers_not_supported
[20:15:54] ================= [PASSED] drm_framebuffer =================
[20:15:54] ================ drm_gem_shmem (8 subtests) ================
[20:15:54] [PASSED] drm_gem_shmem_test_obj_create
[20:15:54] [PASSED] drm_gem_shmem_test_obj_create_private
[20:15:54] [PASSED] drm_gem_shmem_test_pin_pages
[20:15:54] [PASSED] drm_gem_shmem_test_vmap
[20:15:54] [PASSED] drm_gem_shmem_test_get_sg_table
[20:15:54] [PASSED] drm_gem_shmem_test_get_pages_sgt
[20:15:54] [PASSED] drm_gem_shmem_test_madvise
[20:15:54] [PASSED] drm_gem_shmem_test_purge
[20:15:54] ================== [PASSED] drm_gem_shmem ==================
[20:15:54] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[20:15:54] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[20:15:54] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[20:15:54] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[20:15:54] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[20:15:54] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[20:15:54] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[20:15:54] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420 =======
[20:15:54] [PASSED] Automatic
[20:15:54] [PASSED] Full
[20:15:54] [PASSED] Limited 16:235
[20:15:54] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[20:15:54] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[20:15:54] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[20:15:54] [PASSED] drm_test_check_disable_connector
[20:15:54] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[20:15:54] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[20:15:54] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[20:15:54] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[20:15:54] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[20:15:54] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[20:15:54] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[20:15:54] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[20:15:54] [PASSED] drm_test_check_output_bpc_dvi
[20:15:54] [PASSED] drm_test_check_output_bpc_format_vic_1
[20:15:54] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[20:15:54] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[20:15:54] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[20:15:54] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[20:15:54] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[20:15:54] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[20:15:54] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[20:15:54] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[20:15:54] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[20:15:54] [PASSED] drm_test_check_broadcast_rgb_value
[20:15:54] [PASSED] drm_test_check_bpc_8_value
[20:15:54] [PASSED] drm_test_check_bpc_10_value
[20:15:54] [PASSED] drm_test_check_bpc_12_value
[20:15:54] [PASSED] drm_test_check_format_value
[20:15:54] [PASSED] drm_test_check_tmds_char_value
[20:15:54] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[20:15:54] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[20:15:54] [PASSED] drm_test_check_mode_valid
[20:15:54] [PASSED] drm_test_check_mode_valid_reject
[20:15:54] [PASSED] drm_test_check_mode_valid_reject_rate
[20:15:54] [PASSED] drm_test_check_mode_valid_reject_max_clock
[20:15:54] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[20:15:54] = drm_atomic_helper_connector_hdmi_infoframes (5 subtests) =
[20:15:54] [PASSED] drm_test_check_infoframes
[20:15:54] [PASSED] drm_test_check_reject_avi_infoframe
[20:15:54] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_8
[20:15:54] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_10
[20:15:54] [PASSED] drm_test_check_reject_audio_infoframe
[20:15:54] === [PASSED] drm_atomic_helper_connector_hdmi_infoframes ===
[20:15:54] ================= drm_managed (2 subtests) =================
[20:15:54] [PASSED] drm_test_managed_release_action
[20:15:54] [PASSED] drm_test_managed_run_action
[20:15:54] =================== [PASSED] drm_managed ===================
[20:15:54] =================== drm_mm (6 subtests) ====================
[20:15:54] [PASSED] drm_test_mm_init
[20:15:54] [PASSED] drm_test_mm_debug
[20:15:54] [PASSED] drm_test_mm_align32
[20:15:54] [PASSED] drm_test_mm_align64
[20:15:54] [PASSED] drm_test_mm_lowest
[20:15:54] [PASSED] drm_test_mm_highest
[20:15:54] ===================== [PASSED] drm_mm ======================
[20:15:54] ============= drm_modes_analog_tv (5 subtests) =============
[20:15:54] [PASSED] drm_test_modes_analog_tv_mono_576i
[20:15:54] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[20:15:54] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[20:15:54] [PASSED] drm_test_modes_analog_tv_pal_576i
[20:15:54] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[20:15:54] =============== [PASSED] drm_modes_analog_tv ===============
[20:15:54] ============== drm_plane_helper (2 subtests) ===============
[20:15:54] =============== drm_test_check_plane_state ================
[20:15:54] [PASSED] clipping_simple
[20:15:54] [PASSED] clipping_rotate_reflect
[20:15:54] [PASSED] positioning_simple
[20:15:54] [PASSED] upscaling
[20:15:54] [PASSED] downscaling
[20:15:54] [PASSED] rounding1
[20:15:54] [PASSED] rounding2
[20:15:54] [PASSED] rounding3
[20:15:54] [PASSED] rounding4
[20:15:54] =========== [PASSED] drm_test_check_plane_state ============
[20:15:54] =========== drm_test_check_invalid_plane_state ============
[20:15:54] [PASSED] positioning_invalid
[20:15:54] [PASSED] upscaling_invalid
[20:15:54] [PASSED] downscaling_invalid
[20:15:54] ======= [PASSED] drm_test_check_invalid_plane_state ========
[20:15:54] ================ [PASSED] drm_plane_helper =================
[20:15:54] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[20:15:54] ====== drm_test_connector_helper_tv_get_modes_check =======
[20:15:54] [PASSED] None
[20:15:54] [PASSED] PAL
[20:15:54] [PASSED] NTSC
[20:15:54] [PASSED] Both, NTSC Default
[20:15:54] [PASSED] Both, PAL Default
[20:15:54] [PASSED] Both, NTSC Default, with PAL on command-line
[20:15:54] [PASSED] Both, PAL Default, with NTSC on command-line
[20:15:54] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[20:15:54] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[20:15:54] ================== drm_rect (9 subtests) ===================
[20:15:54] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[20:15:54] [PASSED] drm_test_rect_clip_scaled_not_clipped
[20:15:54] [PASSED] drm_test_rect_clip_scaled_clipped
[20:15:54] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[20:15:54] ================= drm_test_rect_intersect =================
[20:15:54] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[20:15:54] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[20:15:54] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[20:15:54] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[20:15:54] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[20:15:54] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[20:15:54] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[20:15:54] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[20:15:54] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[20:15:54] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[20:15:54] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[20:15:54] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[20:15:54] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[20:15:54] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[20:15:54] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[20:15:54] ============= [PASSED] drm_test_rect_intersect =============
[20:15:54] ================ drm_test_rect_calc_hscale ================
[20:15:54] [PASSED] normal use
[20:15:54] [PASSED] out of max range
[20:15:54] [PASSED] out of min range
[20:15:54] [PASSED] zero dst
[20:15:54] [PASSED] negative src
[20:15:54] [PASSED] negative dst
[20:15:54] ============ [PASSED] drm_test_rect_calc_hscale ============
[20:15:54] ================ drm_test_rect_calc_vscale ================
[20:15:54] [PASSED] normal use
[20:15:54] [PASSED] out of max range
[20:15:54] [PASSED] out of min range
[20:15:54] [PASSED] zero dst
[20:15:54] [PASSED] negative src
[20:15:54] [PASSED] negative dst
[20:15:54] ============ [PASSED] drm_test_rect_calc_vscale ============
[20:15:54] ================== drm_test_rect_rotate ===================
[20:15:54] [PASSED] reflect-x
[20:15:54] [PASSED] reflect-y
[20:15:54] [PASSED] rotate-0
[20:15:54] [PASSED] rotate-90
[20:15:54] [PASSED] rotate-180
[20:15:54] [PASSED] rotate-270
[20:15:54] ============== [PASSED] drm_test_rect_rotate ===============
[20:15:54] ================ drm_test_rect_rotate_inv =================
[20:15:54] [PASSED] reflect-x
[20:15:54] [PASSED] reflect-y
[20:15:54] [PASSED] rotate-0
[20:15:54] [PASSED] rotate-90
[20:15:54] [PASSED] rotate-180
[20:15:54] [PASSED] rotate-270
[20:15:54] ============ [PASSED] drm_test_rect_rotate_inv =============
[20:15:54] ==================== [PASSED] drm_rect =====================
[20:15:54] ============ drm_sysfb_modeset_test (1 subtest) ============
[20:15:54] ============ drm_test_sysfb_build_fourcc_list =============
[20:15:54] [PASSED] no native formats
[20:15:54] [PASSED] XRGB8888 as native format
[20:15:54] [PASSED] remove duplicates
[20:15:54] [PASSED] convert alpha formats
[20:15:54] [PASSED] random formats
[20:15:54] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[20:15:54] ============= [PASSED] drm_sysfb_modeset_test ==============
[20:15:54] ================== drm_fixp (2 subtests) ===================
[20:15:54] [PASSED] drm_test_int2fixp
[20:15:54] [PASSED] drm_test_sm2fixp
[20:15:54] ==================== [PASSED] drm_fixp =====================
[20:15:54] ============================================================
[20:15:54] Testing complete. Ran 621 tests: passed: 621
[20:15:54] Elapsed time: 26.788s total, 1.915s configuring, 24.701s building, 0.141s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[20:15:54] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[20:15:56] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[20:16:05] Starting KUnit Kernel (1/1)...
[20:16:05] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[20:16:05] ================= ttm_device (5 subtests) ==================
[20:16:05] [PASSED] ttm_device_init_basic
[20:16:05] [PASSED] ttm_device_init_multiple
[20:16:05] [PASSED] ttm_device_fini_basic
[20:16:05] [PASSED] ttm_device_init_no_vma_man
[20:16:05] ================== ttm_device_init_pools ==================
[20:16:05] [PASSED] No DMA allocations, no DMA32 required
[20:16:05] [PASSED] DMA allocations, DMA32 required
[20:16:05] [PASSED] No DMA allocations, DMA32 required
[20:16:05] [PASSED] DMA allocations, no DMA32 required
[20:16:05] ============== [PASSED] ttm_device_init_pools ==============
[20:16:05] =================== [PASSED] ttm_device ====================
[20:16:05] ================== ttm_pool (8 subtests) ===================
[20:16:05] ================== ttm_pool_alloc_basic ===================
[20:16:05] [PASSED] One page
[20:16:05] [PASSED] More than one page
[20:16:05] [PASSED] Above the allocation limit
[20:16:05] [PASSED] One page, with coherent DMA mappings enabled
[20:16:05] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[20:16:05] ============== [PASSED] ttm_pool_alloc_basic ===============
[20:16:05] ============== ttm_pool_alloc_basic_dma_addr ==============
[20:16:05] [PASSED] One page
[20:16:05] [PASSED] More than one page
[20:16:05] [PASSED] Above the allocation limit
[20:16:05] [PASSED] One page, with coherent DMA mappings enabled
[20:16:05] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[20:16:05] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[20:16:05] [PASSED] ttm_pool_alloc_order_caching_match
[20:16:05] [PASSED] ttm_pool_alloc_caching_mismatch
[20:16:05] [PASSED] ttm_pool_alloc_order_mismatch
[20:16:05] [PASSED] ttm_pool_free_dma_alloc
[20:16:05] [PASSED] ttm_pool_free_no_dma_alloc
[20:16:05] [PASSED] ttm_pool_fini_basic
[20:16:05] ==================== [PASSED] ttm_pool =====================
[20:16:05] ================ ttm_resource (8 subtests) =================
[20:16:05] ================= ttm_resource_init_basic =================
[20:16:05] [PASSED] Init resource in TTM_PL_SYSTEM
[20:16:05] [PASSED] Init resource in TTM_PL_VRAM
[20:16:05] [PASSED] Init resource in a private placement
[20:16:05] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[20:16:05] ============= [PASSED] ttm_resource_init_basic =============
[20:16:05] [PASSED] ttm_resource_init_pinned
[20:16:05] [PASSED] ttm_resource_fini_basic
[20:16:05] [PASSED] ttm_resource_manager_init_basic
[20:16:05] [PASSED] ttm_resource_manager_usage_basic
[20:16:05] [PASSED] ttm_resource_manager_set_used_basic
[20:16:05] [PASSED] ttm_sys_man_alloc_basic
[20:16:05] [PASSED] ttm_sys_man_free_basic
[20:16:05] ================== [PASSED] ttm_resource ===================
[20:16:05] =================== ttm_tt (15 subtests) ===================
[20:16:05] ==================== ttm_tt_init_basic ====================
[20:16:05] [PASSED] Page-aligned size
[20:16:05] [PASSED] Extra pages requested
[20:16:05] ================ [PASSED] ttm_tt_init_basic ================
[20:16:05] [PASSED] ttm_tt_init_misaligned
[20:16:05] [PASSED] ttm_tt_fini_basic
[20:16:05] [PASSED] ttm_tt_fini_sg
[20:16:05] [PASSED] ttm_tt_fini_shmem
[20:16:05] [PASSED] ttm_tt_create_basic
[20:16:05] [PASSED] ttm_tt_create_invalid_bo_type
[20:16:05] [PASSED] ttm_tt_create_ttm_exists
[20:16:05] [PASSED] ttm_tt_create_failed
[20:16:05] [PASSED] ttm_tt_destroy_basic
[20:16:05] [PASSED] ttm_tt_populate_null_ttm
[20:16:05] [PASSED] ttm_tt_populate_populated_ttm
[20:16:05] [PASSED] ttm_tt_unpopulate_basic
[20:16:05] [PASSED] ttm_tt_unpopulate_empty_ttm
[20:16:05] [PASSED] ttm_tt_swapin_basic
[20:16:05] ===================== [PASSED] ttm_tt ======================
[20:16:05] =================== ttm_bo (14 subtests) ===================
[20:16:05] =========== ttm_bo_reserve_optimistic_no_ticket ===========
[20:16:05] [PASSED] Cannot be interrupted and sleeps
[20:16:05] [PASSED] Cannot be interrupted, locks straight away
[20:16:05] [PASSED] Can be interrupted, sleeps
[20:16:05] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[20:16:05] [PASSED] ttm_bo_reserve_locked_no_sleep
[20:16:05] [PASSED] ttm_bo_reserve_no_wait_ticket
[20:16:06] [PASSED] ttm_bo_reserve_double_resv
[20:16:06] [PASSED] ttm_bo_reserve_interrupted
[20:16:06] [PASSED] ttm_bo_reserve_deadlock
[20:16:06] [PASSED] ttm_bo_unreserve_basic
[20:16:06] [PASSED] ttm_bo_unreserve_pinned
[20:16:06] [PASSED] ttm_bo_unreserve_bulk
[20:16:06] [PASSED] ttm_bo_fini_basic
[20:16:06] [PASSED] ttm_bo_fini_shared_resv
[20:16:06] [PASSED] ttm_bo_pin_basic
[20:16:06] [PASSED] ttm_bo_pin_unpin_resource
[20:16:06] [PASSED] ttm_bo_multiple_pin_one_unpin
[20:16:06] ===================== [PASSED] ttm_bo ======================
[20:16:06] ============== ttm_bo_validate (22 subtests) ===============
[20:16:06] ============== ttm_bo_init_reserved_sys_man ===============
[20:16:06] [PASSED] Buffer object for userspace
[20:16:06] [PASSED] Kernel buffer object
[20:16:06] [PASSED] Shared buffer object
[20:16:06] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[20:16:06] ============== ttm_bo_init_reserved_mock_man ==============
[20:16:06] [PASSED] Buffer object for userspace
[20:16:06] [PASSED] Kernel buffer object
[20:16:06] [PASSED] Shared buffer object
[20:16:06] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[20:16:06] [PASSED] ttm_bo_init_reserved_resv
[20:16:06] ================== ttm_bo_validate_basic ==================
[20:16:06] [PASSED] Buffer object for userspace
[20:16:06] [PASSED] Kernel buffer object
[20:16:06] [PASSED] Shared buffer object
[20:16:06] ============== [PASSED] ttm_bo_validate_basic ==============
[20:16:06] [PASSED] ttm_bo_validate_invalid_placement
[20:16:06] ============= ttm_bo_validate_same_placement ==============
[20:16:06] [PASSED] System manager
[20:16:06] [PASSED] VRAM manager
[20:16:06] ========= [PASSED] ttm_bo_validate_same_placement ==========
[20:16:06] [PASSED] ttm_bo_validate_failed_alloc
[20:16:06] [PASSED] ttm_bo_validate_pinned
[20:16:06] [PASSED] ttm_bo_validate_busy_placement
[20:16:06] ================ ttm_bo_validate_multihop =================
[20:16:06] [PASSED] Buffer object for userspace
[20:16:06] [PASSED] Kernel buffer object
[20:16:06] [PASSED] Shared buffer object
[20:16:06] ============ [PASSED] ttm_bo_validate_multihop =============
[20:16:06] ========== ttm_bo_validate_no_placement_signaled ==========
[20:16:06] [PASSED] Buffer object in system domain, no page vector
[20:16:06] [PASSED] Buffer object in system domain with an existing page vector
[20:16:06] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[20:16:06] ======== ttm_bo_validate_no_placement_not_signaled ========
[20:16:06] [PASSED] Buffer object for userspace
[20:16:06] [PASSED] Kernel buffer object
[20:16:06] [PASSED] Shared buffer object
[20:16:06] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[20:16:06] [PASSED] ttm_bo_validate_move_fence_signaled
[20:16:06] ========= ttm_bo_validate_move_fence_not_signaled =========
[20:16:06] [PASSED] Waits for GPU
[20:16:06] [PASSED] Tries to lock straight away
[20:16:06] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[20:16:06] [PASSED] ttm_bo_validate_swapout
[20:16:06] [PASSED] ttm_bo_validate_happy_evict
[20:16:06] [PASSED] ttm_bo_validate_all_pinned_evict
[20:16:06] [PASSED] ttm_bo_validate_allowed_only_evict
[20:16:06] [PASSED] ttm_bo_validate_deleted_evict
[20:16:06] [PASSED] ttm_bo_validate_busy_domain_evict
[20:16:06] [PASSED] ttm_bo_validate_evict_gutting
[20:16:06] [PASSED] ttm_bo_validate_recrusive_evict
[20:16:06] ================= [PASSED] ttm_bo_validate =================
[20:16:06] ============================================================
[20:16:06] Testing complete. Ran 102 tests: passed: 102
[20:16:06] Elapsed time: 11.613s total, 1.757s configuring, 9.641s building, 0.181s running
+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel
^ permalink raw reply [flat|nested] 15+ messages in thread
* ✗ i915.CI.BAT: failure for drm/i915/bw: Split bandwidth params into platform- and display-IP-specific structs (rev3)
2026-05-14 19:19 [PATCH v3 0/5] drm/i915/bw: Split bandwidth params into platform- and display-IP-specific structs Gustavo Sousa
` (5 preceding siblings ...)
2026-05-14 20:16 ` ✓ CI.KUnit: success for drm/i915/bw: Split bandwidth params into platform- and display-IP-specific structs (rev2) Patchwork
@ 2026-05-14 20:36 ` Patchwork
2026-05-14 21:26 ` Gustavo Sousa
2026-05-14 21:11 ` ✓ Xe.CI.BAT: success for drm/i915/bw: Split bandwidth params into platform- and display-IP-specific structs (rev2) Patchwork
2026-05-15 14:02 ` ✓ Xe.CI.FULL: " Patchwork
8 siblings, 1 reply; 15+ messages in thread
From: Patchwork @ 2026-05-14 20:36 UTC (permalink / raw)
To: Gustavo Sousa; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 3773 bytes --]
== Series Details ==
Series: drm/i915/bw: Split bandwidth params into platform- and display-IP-specific structs (rev3)
URL : https://patchwork.freedesktop.org/series/164567/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_18491 -> Patchwork_164567v3
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_164567v3 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_164567v3, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v3/index.html
Participating hosts (42 -> 40)
------------------------------
Missing (2): bat-dg2-13 fi-snb-2520m
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_164567v3:
### IGT changes ###
#### Possible regressions ####
* igt@i915_module_load@load:
- bat-dg2-9: [PASS][1] -> [ABORT][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18491/bat-dg2-9/igt@i915_module_load@load.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v3/bat-dg2-9/igt@i915_module_load@load.html
- bat-dg2-14: [PASS][3] -> [ABORT][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18491/bat-dg2-14/igt@i915_module_load@load.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v3/bat-dg2-14/igt@i915_module_load@load.html
- bat-dg2-8: [PASS][5] -> [ABORT][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18491/bat-dg2-8/igt@i915_module_load@load.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v3/bat-dg2-8/igt@i915_module_load@load.html
Known issues
------------
Here are the changes found in Patchwork_164567v3 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_selftest@live@workarounds:
- bat-arls-5: [PASS][7] -> [DMESG-FAIL][8] ([i915#12061]) +1 other test dmesg-fail
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18491/bat-arls-5/igt@i915_selftest@live@workarounds.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v3/bat-arls-5/igt@i915_selftest@live@workarounds.html
- bat-mtlp-9: [PASS][9] -> [DMESG-FAIL][10] ([i915#12061]) +1 other test dmesg-fail
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18491/bat-mtlp-9/igt@i915_selftest@live@workarounds.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v3/bat-mtlp-9/igt@i915_selftest@live@workarounds.html
#### Possible fixes ####
* igt@i915_selftest@live@workarounds:
- bat-arls-6: [DMESG-FAIL][11] ([i915#12061]) -> [PASS][12] +1 other test pass
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18491/bat-arls-6/igt@i915_selftest@live@workarounds.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v3/bat-arls-6/igt@i915_selftest@live@workarounds.html
[i915#12061]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12061
Build changes
-------------
* Linux: CI_DRM_18491 -> Patchwork_164567v3
CI-20190529: 20190529
CI_DRM_18491: 66af2225d31aa8315b0b9f3c735dba4a53e8d3bf @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_8912: 22222b7d987067331459c2a866e6387a669b7f70 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_164567v3: 66af2225d31aa8315b0b9f3c735dba4a53e8d3bf @ git://anongit.freedesktop.org/gfx-ci/linux
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v3/index.html
[-- Attachment #2: Type: text/html, Size: 4594 bytes --]
^ permalink raw reply [flat|nested] 15+ messages in thread
* ✓ Xe.CI.BAT: success for drm/i915/bw: Split bandwidth params into platform- and display-IP-specific structs (rev2)
2026-05-14 19:19 [PATCH v3 0/5] drm/i915/bw: Split bandwidth params into platform- and display-IP-specific structs Gustavo Sousa
` (6 preceding siblings ...)
2026-05-14 20:36 ` ✗ i915.CI.BAT: failure for drm/i915/bw: Split bandwidth params into platform- and display-IP-specific structs (rev3) Patchwork
@ 2026-05-14 21:11 ` Patchwork
2026-05-15 14:02 ` ✓ Xe.CI.FULL: " Patchwork
8 siblings, 0 replies; 15+ messages in thread
From: Patchwork @ 2026-05-14 21:11 UTC (permalink / raw)
To: Gustavo Sousa; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 1003 bytes --]
== Series Details ==
Series: drm/i915/bw: Split bandwidth params into platform- and display-IP-specific structs (rev2)
URL : https://patchwork.freedesktop.org/series/166340/
State : success
== Summary ==
CI Bug Log - changes from xe-5065-66af2225d31aa8315b0b9f3c735dba4a53e8d3bf_BAT -> xe-pw-166340v2_BAT
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (13 -> 13)
------------------------------
No changes in participating hosts
Changes
-------
No changes found
Build changes
-------------
* Linux: xe-5065-66af2225d31aa8315b0b9f3c735dba4a53e8d3bf -> xe-pw-166340v2
IGT_8912: 22222b7d987067331459c2a866e6387a669b7f70 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
xe-5065-66af2225d31aa8315b0b9f3c735dba4a53e8d3bf: 66af2225d31aa8315b0b9f3c735dba4a53e8d3bf
xe-pw-166340v2: 166340v2
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v2/index.html
[-- Attachment #2: Type: text/html, Size: 1551 bytes --]
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: ✗ i915.CI.BAT: failure for drm/i915/bw: Split bandwidth params into platform- and display-IP-specific structs (rev3)
2026-05-14 20:36 ` ✗ i915.CI.BAT: failure for drm/i915/bw: Split bandwidth params into platform- and display-IP-specific structs (rev3) Patchwork
@ 2026-05-14 21:26 ` Gustavo Sousa
0 siblings, 0 replies; 15+ messages in thread
From: Gustavo Sousa @ 2026-05-14 21:26 UTC (permalink / raw)
To: Jani Nikula, Matt Roper; +Cc: intel-gfx
Patchwork <patchwork@emeril.freedesktop.org> writes:
> == Series Details ==
>
> Series: drm/i915/bw: Split bandwidth params into platform- and display-IP-specific structs (rev3)
> URL : https://patchwork.freedesktop.org/series/164567/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_18491 -> Patchwork_164567v3
> ====================================================
>
> Summary
> -------
>
> **FAILURE**
>
> Serious unknown changes coming with Patchwork_164567v3 absolutely need to be
> verified manually.
>
> If you think the reported changes have nothing to do with the changes
> introduced in Patchwork_164567v3, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
> to document this new failure mode, which will reduce false positives in CI.
>
> External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v3/index.html
>
> Participating hosts (42 -> 40)
> ------------------------------
>
> Missing (2): bat-dg2-13 fi-snb-2520m
>
> Possible new issues
> -------------------
>
> Here are the unknown changes that may have been introduced in Patchwork_164567v3:
>
> ### IGT changes ###
>
> #### Possible regressions ####
>
> * igt@i915_module_load@load:
> - bat-dg2-9: [PASS][1] -> [ABORT][2]
> [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18491/bat-dg2-9/igt@i915_module_load@load.html
> [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v3/bat-dg2-9/igt@i915_module_load@load.html
> - bat-dg2-14: [PASS][3] -> [ABORT][4]
> [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18491/bat-dg2-14/igt@i915_module_load@load.html
> [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v3/bat-dg2-14/igt@i915_module_load@load.html
> - bat-dg2-8: [PASS][5] -> [ABORT][6]
> [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18491/bat-dg2-8/igt@i915_module_load@load.html
> [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_164567v3/bat-dg2-8/igt@i915_module_load@load.html
Hm... This shows the warning because DG2 does not use bandwidth
parameters and get_soc_bw_params() rightfully does not cover DG2.
We could just get rid of the warnings in get_soc_bw_params() and
get_display_bw_params() all together. The idea of the warning was to
serve as an aid to the developer, but I guess tracing the null pointer
dereference back to those functions shouldn't be too hard?
Another idea is to make sure that only the functions that use those
parameters make the call to get_{soc,display}_bw_params(). Jani, I know
you preferred the other way around, but maybe this is a compelling
reason for moving the call to the direct users?
--
Gustavo Sousa
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v3 1/5] drm/i915/bw: Don't call intel_dram_info() too early
2026-05-14 19:19 ` [PATCH v3 1/5] drm/i915/bw: Don't call intel_dram_info() too early Gustavo Sousa
@ 2026-05-15 8:26 ` Jani Nikula
0 siblings, 0 replies; 15+ messages in thread
From: Jani Nikula @ 2026-05-15 8:26 UTC (permalink / raw)
To: Gustavo Sousa, intel-gfx, intel-xe; +Cc: Gustavo Sousa
On Thu, 14 May 2026, Gustavo Sousa <gustavo.sousa@intel.com> wrote:
> If we end-up bailing early from intel_bw_init_hw() due to
> !HAS_DISPLAY(display), the call to intel_dram_info() to initialize
> dram_info will be meaningless. Move the call to be done after that
> check.
>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_bw.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
> index 9c3a9bbb49f6..7eef693b51ad 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.c
> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> @@ -791,11 +791,13 @@ static unsigned int icl_qgv_bw(struct intel_display *display,
>
> void intel_bw_init_hw(struct intel_display *display)
> {
> - const struct dram_info *dram_info = intel_dram_info(display);
> + const struct dram_info *dram_info;
>
> if (!HAS_DISPLAY(display))
> return;
>
> + dram_info = intel_dram_info(display);
> +
> /*
> * Starting with Xe3p_LPD, the hardware tells us whether memory has ECC
> * enabled that would impact display bandwidth. However, so far there
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 15+ messages in thread
* ✓ Xe.CI.FULL: success for drm/i915/bw: Split bandwidth params into platform- and display-IP-specific structs (rev2)
2026-05-14 19:19 [PATCH v3 0/5] drm/i915/bw: Split bandwidth params into platform- and display-IP-specific structs Gustavo Sousa
` (7 preceding siblings ...)
2026-05-14 21:11 ` ✓ Xe.CI.BAT: success for drm/i915/bw: Split bandwidth params into platform- and display-IP-specific structs (rev2) Patchwork
@ 2026-05-15 14:02 ` Patchwork
8 siblings, 0 replies; 15+ messages in thread
From: Patchwork @ 2026-05-15 14:02 UTC (permalink / raw)
To: Gustavo Sousa; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 30374 bytes --]
== Series Details ==
Series: drm/i915/bw: Split bandwidth params into platform- and display-IP-specific structs (rev2)
URL : https://patchwork.freedesktop.org/series/166340/
State : success
== Summary ==
CI Bug Log - changes from xe-5065-66af2225d31aa8315b0b9f3c735dba4a53e8d3bf_FULL -> xe-pw-166340v2_FULL
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (2 -> 2)
------------------------------
No changes in participating hosts
Known issues
------------
Here are the changes found in xe-pw-166340v2_FULL that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@intel_hwmon@hwmon-read:
- shard-bmg: [PASS][1] -> [SKIP][2] ([Intel XE#5177] / [Intel XE#6703])
[1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5065-66af2225d31aa8315b0b9f3c735dba4a53e8d3bf/shard-bmg-5/igt@intel_hwmon@hwmon-read.html
[2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v2/shard-bmg-2/igt@intel_hwmon@hwmon-read.html
* igt@kms_async_flips@alternate-sync-async-flip:
- shard-bmg: [PASS][3] -> [FAIL][4] ([Intel XE#3718] / [Intel XE#6078])
[3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5065-66af2225d31aa8315b0b9f3c735dba4a53e8d3bf/shard-bmg-9/igt@kms_async_flips@alternate-sync-async-flip.html
[4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v2/shard-bmg-6/igt@kms_async_flips@alternate-sync-async-flip.html
* igt@kms_async_flips@alternate-sync-async-flip@pipe-b-dp-2:
- shard-bmg: [PASS][5] -> [FAIL][6] ([Intel XE#6078])
[5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5065-66af2225d31aa8315b0b9f3c735dba4a53e8d3bf/shard-bmg-9/igt@kms_async_flips@alternate-sync-async-flip@pipe-b-dp-2.html
[6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v2/shard-bmg-6/igt@kms_async_flips@alternate-sync-async-flip@pipe-b-dp-2.html
* igt@kms_big_fb@yf-tiled-64bpp-rotate-90:
- shard-bmg: NOTRUN -> [SKIP][7] ([Intel XE#1124])
[7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v2/shard-bmg-1/igt@kms_big_fb@yf-tiled-64bpp-rotate-90.html
* igt@kms_ccs@bad-rotation-90-y-tiled-ccs:
- shard-bmg: NOTRUN -> [SKIP][8] ([Intel XE#2887]) +2 other tests skip
[8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v2/shard-bmg-1/igt@kms_ccs@bad-rotation-90-y-tiled-ccs.html
* igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs:
- shard-bmg: [PASS][9] -> [INCOMPLETE][10] ([Intel XE#7084]) +1 other test incomplete
[9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5065-66af2225d31aa8315b0b9f3c735dba4a53e8d3bf/shard-bmg-9/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html
[10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v2/shard-bmg-6/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html
* igt@kms_cursor_legacy@cursor-vs-flip-toggle:
- shard-bmg: [PASS][11] -> [SKIP][12] ([Intel XE#6703] / [Intel XE#7935])
[11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5065-66af2225d31aa8315b0b9f3c735dba4a53e8d3bf/shard-bmg-5/igt@kms_cursor_legacy@cursor-vs-flip-toggle.html
[12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v2/shard-bmg-2/igt@kms_cursor_legacy@cursor-vs-flip-toggle.html
* igt@kms_dsc@dsc-with-bpc-formats:
- shard-bmg: NOTRUN -> [SKIP][13] ([Intel XE#2244])
[13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v2/shard-bmg-1/igt@kms_dsc@dsc-with-bpc-formats.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-lnl: [PASS][14] -> [FAIL][15] ([i915#4767])
[14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5065-66af2225d31aa8315b0b9f3c735dba4a53e8d3bf/shard-lnl-7/igt@kms_fbcon_fbt@fbc-suspend.html
[15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v2/shard-lnl-5/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_flip@2x-nonexisting-fb:
- shard-bmg: [PASS][16] -> [SKIP][17] ([Intel XE#6703]) +152 other tests skip
[16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5065-66af2225d31aa8315b0b9f3c735dba4a53e8d3bf/shard-bmg-5/igt@kms_flip@2x-nonexisting-fb.html
[17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v2/shard-bmg-2/igt@kms_flip@2x-nonexisting-fb.html
* igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-upscaling:
- shard-bmg: NOTRUN -> [SKIP][18] ([Intel XE#7178] / [Intel XE#7351])
[18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v2/shard-bmg-1/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-upscaling.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-pgflip-blt:
- shard-bmg: NOTRUN -> [SKIP][19] ([Intel XE#4141])
[19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v2/shard-bmg-1/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-pgflip-blt.html
* igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-indfb-pgflip-blt:
- shard-bmg: NOTRUN -> [SKIP][20] ([Intel XE#2311]) +3 other tests skip
[20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v2/shard-bmg-1/igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-indfb-pgflip-blt.html
* igt@kms_frontbuffer_tracking@fbcpsrhdr-2p-primscrn-spr-indfb-draw-render:
- shard-bmg: NOTRUN -> [SKIP][21] ([Intel XE#2313]) +4 other tests skip
[21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v2/shard-bmg-1/igt@kms_frontbuffer_tracking@fbcpsrhdr-2p-primscrn-spr-indfb-draw-render.html
* igt@kms_hdr@static-swap@pipe-a-hdmi-a-3-xrgb2101010:
- shard-bmg: [PASS][22] -> [SKIP][23] ([Intel XE#7915]) +1 other test skip
[22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5065-66af2225d31aa8315b0b9f3c735dba4a53e8d3bf/shard-bmg-9/igt@kms_hdr@static-swap@pipe-a-hdmi-a-3-xrgb2101010.html
[23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v2/shard-bmg-7/igt@kms_hdr@static-swap@pipe-a-hdmi-a-3-xrgb2101010.html
* igt@xe_eudebug@basic-vm-bind-ufence:
- shard-bmg: NOTRUN -> [SKIP][24] ([Intel XE#7636]) +2 other tests skip
[24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v2/shard-bmg-1/igt@xe_eudebug@basic-vm-bind-ufence.html
* igt@xe_exec_fault_mode@twice-multi-queue-userptr-rebind:
- shard-bmg: NOTRUN -> [SKIP][25] ([Intel XE#7136]) +1 other test skip
[25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v2/shard-bmg-1/igt@xe_exec_fault_mode@twice-multi-queue-userptr-rebind.html
* igt@xe_exec_multi_queue@many-queues-preempt-mode-fault-close-fd-smem:
- shard-bmg: NOTRUN -> [SKIP][26] ([Intel XE#6874]) +1 other test skip
[26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v2/shard-bmg-1/igt@xe_exec_multi_queue@many-queues-preempt-mode-fault-close-fd-smem.html
* igt@xe_exec_system_allocator@many-stride-mmap-prefetch:
- shard-bmg: [PASS][27] -> [SKIP][28] ([Intel XE#6557] / [Intel XE#6703])
[27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5065-66af2225d31aa8315b0b9f3c735dba4a53e8d3bf/shard-bmg-5/igt@xe_exec_system_allocator@many-stride-mmap-prefetch.html
[28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v2/shard-bmg-2/igt@xe_exec_system_allocator@many-stride-mmap-prefetch.html
* igt@xe_exec_threads@threads-multi-queue-cm-shared-vm-userptr:
- shard-bmg: NOTRUN -> [SKIP][29] ([Intel XE#7138])
[29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v2/shard-bmg-1/igt@xe_exec_threads@threads-multi-queue-cm-shared-vm-userptr.html
* igt@xe_pxp@pxp-termination-key-update-post-suspend:
- shard-bmg: NOTRUN -> [SKIP][30] ([Intel XE#4733] / [Intel XE#7417])
[30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v2/shard-bmg-1/igt@xe_pxp@pxp-termination-key-update-post-suspend.html
#### Possible fixes ####
* igt@kms_flip@flip-vs-expired-vblank@c-edp1:
- shard-lnl: [FAIL][31] ([Intel XE#301] / [Intel XE#3149]) -> [PASS][32]
[31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5065-66af2225d31aa8315b0b9f3c735dba4a53e8d3bf/shard-lnl-7/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html
[32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v2/shard-lnl-5/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html
* igt@kms_hdr@invalid-hdr:
- shard-bmg: [SKIP][33] ([Intel XE#1503]) -> [PASS][34]
[33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5065-66af2225d31aa8315b0b9f3c735dba4a53e8d3bf/shard-bmg-6/igt@kms_hdr@invalid-hdr.html
[34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v2/shard-bmg-8/igt@kms_hdr@invalid-hdr.html
* igt@kms_hdr@invalid-hdr@pipe-a-hdmi-a-3-xrgb2101010:
- shard-bmg: [SKIP][35] ([Intel XE#7922]) -> [PASS][36] +1 other test pass
[35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5065-66af2225d31aa8315b0b9f3c735dba4a53e8d3bf/shard-bmg-6/igt@kms_hdr@invalid-hdr@pipe-a-hdmi-a-3-xrgb2101010.html
[36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v2/shard-bmg-8/igt@kms_hdr@invalid-hdr@pipe-a-hdmi-a-3-xrgb2101010.html
* igt@kms_hdr@static-toggle-dpms@pipe-a-hdmi-a-3-xrgb2101010:
- shard-bmg: [SKIP][37] ([Intel XE#7915]) -> [PASS][38] +3 other tests pass
[37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5065-66af2225d31aa8315b0b9f3c735dba4a53e8d3bf/shard-bmg-7/igt@kms_hdr@static-toggle-dpms@pipe-a-hdmi-a-3-xrgb2101010.html
[38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v2/shard-bmg-9/igt@kms_hdr@static-toggle-dpms@pipe-a-hdmi-a-3-xrgb2101010.html
* igt@kms_vrr@seamless-rr-switch-virtual@pipe-a-edp-1:
- shard-lnl: [FAIL][39] ([Intel XE#2142]) -> [PASS][40] +1 other test pass
[39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5065-66af2225d31aa8315b0b9f3c735dba4a53e8d3bf/shard-lnl-3/igt@kms_vrr@seamless-rr-switch-virtual@pipe-a-edp-1.html
[40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v2/shard-lnl-3/igt@kms_vrr@seamless-rr-switch-virtual@pipe-a-edp-1.html
* igt@xe_survivability@runtime-survivability:
- shard-bmg: [DMESG-WARN][41] ([Intel XE#6627] / [Intel XE#7419]) -> [PASS][42]
[41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5065-66af2225d31aa8315b0b9f3c735dba4a53e8d3bf/shard-bmg-6/igt@xe_survivability@runtime-survivability.html
[42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v2/shard-bmg-9/igt@xe_survivability@runtime-survivability.html
#### Warnings ####
* igt@kms_big_fb@x-tiled-16bpp-rotate-270:
- shard-bmg: [SKIP][43] ([Intel XE#2327]) -> [SKIP][44] ([Intel XE#6703])
[43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5065-66af2225d31aa8315b0b9f3c735dba4a53e8d3bf/shard-bmg-5/igt@kms_big_fb@x-tiled-16bpp-rotate-270.html
[44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v2/shard-bmg-2/igt@kms_big_fb@x-tiled-16bpp-rotate-270.html
* igt@kms_big_fb@y-tiled-64bpp-rotate-90:
- shard-bmg: [SKIP][45] ([Intel XE#1124]) -> [SKIP][46] ([Intel XE#6703]) +2 other tests skip
[45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5065-66af2225d31aa8315b0b9f3c735dba4a53e8d3bf/shard-bmg-5/igt@kms_big_fb@y-tiled-64bpp-rotate-90.html
[46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v2/shard-bmg-2/igt@kms_big_fb@y-tiled-64bpp-rotate-90.html
* igt@kms_bw@linear-tiling-2-displays-target-1920x1080p:
- shard-bmg: [SKIP][47] ([Intel XE#367]) -> [SKIP][48] ([Intel XE#6703])
[47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5065-66af2225d31aa8315b0b9f3c735dba4a53e8d3bf/shard-bmg-5/igt@kms_bw@linear-tiling-2-displays-target-1920x1080p.html
[48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v2/shard-bmg-2/igt@kms_bw@linear-tiling-2-displays-target-1920x1080p.html
* igt@kms_ccs@crc-primary-basic-4-tiled-mtl-rc-ccs-cc:
- shard-bmg: [SKIP][49] ([Intel XE#2887]) -> [SKIP][50] ([Intel XE#6703]) +2 other tests skip
[49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5065-66af2225d31aa8315b0b9f3c735dba4a53e8d3bf/shard-bmg-5/igt@kms_ccs@crc-primary-basic-4-tiled-mtl-rc-ccs-cc.html
[50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v2/shard-bmg-2/igt@kms_ccs@crc-primary-basic-4-tiled-mtl-rc-ccs-cc.html
* igt@kms_ccs@crc-primary-suspend-yf-tiled-ccs:
- shard-bmg: [SKIP][51] ([Intel XE#3432]) -> [SKIP][52] ([Intel XE#6703])
[51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5065-66af2225d31aa8315b0b9f3c735dba4a53e8d3bf/shard-bmg-5/igt@kms_ccs@crc-primary-suspend-yf-tiled-ccs.html
[52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v2/shard-bmg-2/igt@kms_ccs@crc-primary-suspend-yf-tiled-ccs.html
* igt@kms_chamelium_color@degamma:
- shard-bmg: [SKIP][53] ([Intel XE#2325] / [Intel XE#7358]) -> [SKIP][54] ([Intel XE#6703])
[53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5065-66af2225d31aa8315b0b9f3c735dba4a53e8d3bf/shard-bmg-5/igt@kms_chamelium_color@degamma.html
[54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v2/shard-bmg-2/igt@kms_chamelium_color@degamma.html
* igt@kms_chamelium_hpd@hdmi-hpd-enable-disable-mode:
- shard-bmg: [SKIP][55] ([Intel XE#2252]) -> [SKIP][56] ([Intel XE#6703])
[55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5065-66af2225d31aa8315b0b9f3c735dba4a53e8d3bf/shard-bmg-5/igt@kms_chamelium_hpd@hdmi-hpd-enable-disable-mode.html
[56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v2/shard-bmg-2/igt@kms_chamelium_hpd@hdmi-hpd-enable-disable-mode.html
* igt@kms_content_protection@dp-mst-lic-type-0:
- shard-bmg: [SKIP][57] ([Intel XE#2390] / [Intel XE#6974]) -> [SKIP][58] ([Intel XE#6703])
[57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5065-66af2225d31aa8315b0b9f3c735dba4a53e8d3bf/shard-bmg-5/igt@kms_content_protection@dp-mst-lic-type-0.html
[58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v2/shard-bmg-2/igt@kms_content_protection@dp-mst-lic-type-0.html
* igt@kms_fbcon_fbt@psr:
- shard-bmg: [SKIP][59] ([Intel XE#6126] / [Intel XE#776]) -> [SKIP][60] ([Intel XE#6703])
[59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5065-66af2225d31aa8315b0b9f3c735dba4a53e8d3bf/shard-bmg-5/igt@kms_fbcon_fbt@psr.html
[60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v2/shard-bmg-2/igt@kms_fbcon_fbt@psr.html
* igt@kms_flip@flip-vs-expired-vblank:
- shard-lnl: [FAIL][61] ([Intel XE#301] / [Intel XE#3149]) -> [FAIL][62] ([Intel XE#301])
[61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5065-66af2225d31aa8315b0b9f3c735dba4a53e8d3bf/shard-lnl-7/igt@kms_flip@flip-vs-expired-vblank.html
[62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v2/shard-lnl-5/igt@kms_flip@flip-vs-expired-vblank.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-upscaling:
- shard-bmg: [SKIP][63] ([Intel XE#7178] / [Intel XE#7351]) -> [SKIP][64] ([Intel XE#6703])
[63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5065-66af2225d31aa8315b0b9f3c735dba4a53e8d3bf/shard-bmg-5/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-upscaling.html
[64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v2/shard-bmg-2/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-upscaling.html
* igt@kms_frontbuffer_tracking@drrs-2p-primscrn-shrfb-msflip-blt:
- shard-bmg: [SKIP][65] ([Intel XE#2311]) -> [SKIP][66] ([Intel XE#6703]) +12 other tests skip
[65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5065-66af2225d31aa8315b0b9f3c735dba4a53e8d3bf/shard-bmg-5/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-shrfb-msflip-blt.html
[66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v2/shard-bmg-2/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-shrfb-msflip-blt.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-render:
- shard-bmg: [SKIP][67] ([Intel XE#4141]) -> [SKIP][68] ([Intel XE#6703]) +1 other test skip
[67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5065-66af2225d31aa8315b0b9f3c735dba4a53e8d3bf/shard-bmg-5/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-render.html
[68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v2/shard-bmg-2/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbcpsr-argb161616f-draw-render:
- shard-bmg: [SKIP][69] ([Intel XE#7061] / [Intel XE#7356]) -> [SKIP][70] ([Intel XE#6703])
[69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5065-66af2225d31aa8315b0b9f3c735dba4a53e8d3bf/shard-bmg-5/igt@kms_frontbuffer_tracking@fbcpsr-argb161616f-draw-render.html
[70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v2/shard-bmg-2/igt@kms_frontbuffer_tracking@fbcpsr-argb161616f-draw-render.html
* igt@kms_frontbuffer_tracking@fbcpsrhdr-2p-primscrn-cur-indfb-draw-render:
- shard-bmg: [SKIP][71] ([Intel XE#2313]) -> [SKIP][72] ([Intel XE#6703]) +11 other tests skip
[71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5065-66af2225d31aa8315b0b9f3c735dba4a53e8d3bf/shard-bmg-5/igt@kms_frontbuffer_tracking@fbcpsrhdr-2p-primscrn-cur-indfb-draw-render.html
[72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v2/shard-bmg-2/igt@kms_frontbuffer_tracking@fbcpsrhdr-2p-primscrn-cur-indfb-draw-render.html
* igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
- shard-bmg: [SKIP][73] ([Intel XE#7591]) -> [SKIP][74] ([Intel XE#6703])
[73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5065-66af2225d31aa8315b0b9f3c735dba4a53e8d3bf/shard-bmg-5/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
[74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v2/shard-bmg-2/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
* igt@kms_plane@pixel-format-y-tiled-gen12-rc-ccs-cc-modifier-source-clamping:
- shard-bmg: [SKIP][75] ([Intel XE#7283]) -> [SKIP][76] ([Intel XE#6703])
[75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5065-66af2225d31aa8315b0b9f3c735dba4a53e8d3bf/shard-bmg-5/igt@kms_plane@pixel-format-y-tiled-gen12-rc-ccs-cc-modifier-source-clamping.html
[76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v2/shard-bmg-2/igt@kms_plane@pixel-format-y-tiled-gen12-rc-ccs-cc-modifier-source-clamping.html
* igt@kms_psr2_sf@psr2-plane-move-sf-dmg-area:
- shard-bmg: [SKIP][77] ([Intel XE#1489]) -> [SKIP][78] ([Intel XE#6703])
[77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5065-66af2225d31aa8315b0b9f3c735dba4a53e8d3bf/shard-bmg-5/igt@kms_psr2_sf@psr2-plane-move-sf-dmg-area.html
[78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v2/shard-bmg-2/igt@kms_psr2_sf@psr2-plane-move-sf-dmg-area.html
* igt@kms_psr@psr2-cursor-plane-move:
- shard-bmg: [SKIP][79] ([Intel XE#2234] / [Intel XE#2850]) -> [SKIP][80] ([Intel XE#6703]) +2 other tests skip
[79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5065-66af2225d31aa8315b0b9f3c735dba4a53e8d3bf/shard-bmg-5/igt@kms_psr@psr2-cursor-plane-move.html
[80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v2/shard-bmg-2/igt@kms_psr@psr2-cursor-plane-move.html
* igt@kms_tiled_display@basic-test-pattern:
- shard-bmg: [FAIL][81] ([Intel XE#1729] / [Intel XE#7424]) -> [SKIP][82] ([Intel XE#2426] / [Intel XE#5848])
[81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5065-66af2225d31aa8315b0b9f3c735dba4a53e8d3bf/shard-bmg-6/igt@kms_tiled_display@basic-test-pattern.html
[82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v2/shard-bmg-8/igt@kms_tiled_display@basic-test-pattern.html
* igt@kms_tiled_display@basic-test-pattern-with-chamelium:
- shard-bmg: [SKIP][83] ([Intel XE#2509] / [Intel XE#7437]) -> [SKIP][84] ([Intel XE#2426] / [Intel XE#5848])
[83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5065-66af2225d31aa8315b0b9f3c735dba4a53e8d3bf/shard-bmg-6/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
[84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v2/shard-bmg-9/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
* igt@kms_vrr@flip-dpms:
- shard-bmg: [SKIP][85] ([Intel XE#1499]) -> [SKIP][86] ([Intel XE#6703])
[85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5065-66af2225d31aa8315b0b9f3c735dba4a53e8d3bf/shard-bmg-5/igt@kms_vrr@flip-dpms.html
[86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v2/shard-bmg-2/igt@kms_vrr@flip-dpms.html
* igt@xe_eudebug@discovery-empty:
- shard-bmg: [SKIP][87] ([Intel XE#7636]) -> [SKIP][88] ([Intel XE#6703]) +2 other tests skip
[87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5065-66af2225d31aa8315b0b9f3c735dba4a53e8d3bf/shard-bmg-5/igt@xe_eudebug@discovery-empty.html
[88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v2/shard-bmg-2/igt@xe_eudebug@discovery-empty.html
* igt@xe_eudebug_sriov@deny-sriov:
- shard-bmg: [SKIP][89] ([Intel XE#5793] / [Intel XE#7320] / [Intel XE#7464]) -> [SKIP][90] ([Intel XE#6703])
[89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5065-66af2225d31aa8315b0b9f3c735dba4a53e8d3bf/shard-bmg-5/igt@xe_eudebug_sriov@deny-sriov.html
[90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v2/shard-bmg-2/igt@xe_eudebug_sriov@deny-sriov.html
* igt@xe_evict@evict-mixed-many-threads-small:
- shard-bmg: [INCOMPLETE][91] ([Intel XE#6321]) -> [SKIP][92] ([Intel XE#6703])
[91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5065-66af2225d31aa8315b0b9f3c735dba4a53e8d3bf/shard-bmg-5/igt@xe_evict@evict-mixed-many-threads-small.html
[92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v2/shard-bmg-2/igt@xe_evict@evict-mixed-many-threads-small.html
* igt@xe_exec_basic@multigpu-no-exec-bindexecqueue-rebind:
- shard-bmg: [SKIP][93] ([Intel XE#2322] / [Intel XE#7372]) -> [SKIP][94] ([Intel XE#6703])
[93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5065-66af2225d31aa8315b0b9f3c735dba4a53e8d3bf/shard-bmg-5/igt@xe_exec_basic@multigpu-no-exec-bindexecqueue-rebind.html
[94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v2/shard-bmg-2/igt@xe_exec_basic@multigpu-no-exec-bindexecqueue-rebind.html
* igt@xe_exec_fault_mode@many-execqueues-multi-queue-imm:
- shard-bmg: [SKIP][95] ([Intel XE#7136]) -> [SKIP][96] ([Intel XE#6703]) +2 other tests skip
[95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5065-66af2225d31aa8315b0b9f3c735dba4a53e8d3bf/shard-bmg-5/igt@xe_exec_fault_mode@many-execqueues-multi-queue-imm.html
[96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v2/shard-bmg-2/igt@xe_exec_fault_mode@many-execqueues-multi-queue-imm.html
* igt@xe_exec_multi_queue@one-queue-preempt-mode-fault-dyn-priority-smem:
- shard-bmg: [SKIP][97] ([Intel XE#6874]) -> [SKIP][98] ([Intel XE#6703]) +7 other tests skip
[97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5065-66af2225d31aa8315b0b9f3c735dba4a53e8d3bf/shard-bmg-5/igt@xe_exec_multi_queue@one-queue-preempt-mode-fault-dyn-priority-smem.html
[98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v2/shard-bmg-2/igt@xe_exec_multi_queue@one-queue-preempt-mode-fault-dyn-priority-smem.html
* igt@xe_exec_reset@long-spin-reuse-many-preempt-gt1-threads:
- shard-bmg: [FAIL][99] ([Intel XE#7850]) -> [SKIP][100] ([Intel XE#6703])
[99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5065-66af2225d31aa8315b0b9f3c735dba4a53e8d3bf/shard-bmg-5/igt@xe_exec_reset@long-spin-reuse-many-preempt-gt1-threads.html
[100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v2/shard-bmg-2/igt@xe_exec_reset@long-spin-reuse-many-preempt-gt1-threads.html
* igt@xe_exec_threads@threads-multi-queue-mixed-rebind:
- shard-bmg: [SKIP][101] ([Intel XE#7138]) -> [SKIP][102] ([Intel XE#6703]) +1 other test skip
[101]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5065-66af2225d31aa8315b0b9f3c735dba4a53e8d3bf/shard-bmg-5/igt@xe_exec_threads@threads-multi-queue-mixed-rebind.html
[102]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v2/shard-bmg-2/igt@xe_exec_threads@threads-multi-queue-mixed-rebind.html
* igt@xe_pm@d3hot-i2c:
- shard-bmg: [SKIP][103] ([Intel XE#5742] / [Intel XE#7328] / [Intel XE#7400]) -> [SKIP][104] ([Intel XE#6703])
[103]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5065-66af2225d31aa8315b0b9f3c735dba4a53e8d3bf/shard-bmg-5/igt@xe_pm@d3hot-i2c.html
[104]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v2/shard-bmg-2/igt@xe_pm@d3hot-i2c.html
* igt@xe_wedged@wedged-at-any-timeout:
- shard-bmg: [DMESG-WARN][105] ([Intel XE#5545]) -> [SKIP][106] ([Intel XE#6703])
[105]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5065-66af2225d31aa8315b0b9f3c735dba4a53e8d3bf/shard-bmg-5/igt@xe_wedged@wedged-at-any-timeout.html
[106]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v2/shard-bmg-2/igt@xe_wedged@wedged-at-any-timeout.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
[Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
[Intel XE#1499]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1499
[Intel XE#1503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1503
[Intel XE#1729]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1729
[Intel XE#2142]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2142
[Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
[Intel XE#2244]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2244
[Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
[Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
[Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
[Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
[Intel XE#2325]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2325
[Intel XE#2327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2327
[Intel XE#2390]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2390
[Intel XE#2426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2426
[Intel XE#2509]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2509
[Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
[Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
[Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
[Intel XE#3149]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3149
[Intel XE#3432]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3432
[Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
[Intel XE#3718]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3718
[Intel XE#4141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4141
[Intel XE#4733]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4733
[Intel XE#5177]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5177
[Intel XE#5545]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5545
[Intel XE#5742]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5742
[Intel XE#5793]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5793
[Intel XE#5848]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5848
[Intel XE#6078]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6078
[Intel XE#6126]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6126
[Intel XE#6321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6321
[Intel XE#6557]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6557
[Intel XE#6627]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6627
[Intel XE#6703]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6703
[Intel XE#6874]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6874
[Intel XE#6974]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6974
[Intel XE#7061]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7061
[Intel XE#7084]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7084
[Intel XE#7136]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7136
[Intel XE#7138]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7138
[Intel XE#7178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7178
[Intel XE#7283]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7283
[Intel XE#7320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7320
[Intel XE#7328]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7328
[Intel XE#7351]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7351
[Intel XE#7356]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7356
[Intel XE#7358]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7358
[Intel XE#7372]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7372
[Intel XE#7400]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7400
[Intel XE#7417]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7417
[Intel XE#7419]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7419
[Intel XE#7424]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7424
[Intel XE#7437]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7437
[Intel XE#7464]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7464
[Intel XE#7591]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7591
[Intel XE#7636]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7636
[Intel XE#776]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/776
[Intel XE#7850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7850
[Intel XE#7915]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7915
[Intel XE#7922]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7922
[Intel XE#7935]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7935
[i915#4767]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4767
Build changes
-------------
* Linux: xe-5065-66af2225d31aa8315b0b9f3c735dba4a53e8d3bf -> xe-pw-166340v2
IGT_8912: 22222b7d987067331459c2a866e6387a669b7f70 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
xe-5065-66af2225d31aa8315b0b9f3c735dba4a53e8d3bf: 66af2225d31aa8315b0b9f3c735dba4a53e8d3bf
xe-pw-166340v2: 166340v2
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166340v2/index.html
[-- Attachment #2: Type: text/html, Size: 35613 bytes --]
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v3 2/5] drm/i915/bw: Extract platform-specific parameters
2026-05-14 19:19 ` [PATCH v3 2/5] drm/i915/bw: Extract platform-specific parameters Gustavo Sousa
@ 2026-05-15 15:41 ` Gustavo Sousa
2026-05-15 16:49 ` Jani Nikula
0 siblings, 1 reply; 15+ messages in thread
From: Gustavo Sousa @ 2026-05-15 15:41 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: Jani Nikula, Matt Roper, Rodrigo Vivi
Gustavo Sousa <gustavo.sousa@intel.com> writes:
> We got confirmation from the hardware team that the bandwidth parameters
> deprogbwlimit and derating are platform-specific and not tied to the
> display IP. As such, let's make sure that we use platform checks for
> those.
>
> The rest of the members of struct intel_sa_info are tied to the display
> IP and we will deal with them as a follow-up.
>
> v2:
> - Use good old if-ladder instead of weird-looking pattern "assign ret,
> check platform, then return ret". (Jani, Matt)
> - Have a single call site for get_platform_bw_params() and pass the
> result as parameter to the *_get_bw_info() functions. (Jani)
> - Avoid using "plat" as abbreviation for "platform". (Jani)
> - s/_plat_bw_params/_bw_params/, since all of the instances are
> prefixed with platform names. (Jani)
> - s/struct intel_platform_bw_params/struct intel_soc_bw_params/.
> (Matt)
> - Do not return a default value; prefer to return NULL and
> intentionally cause a NULL pointer dereference if a platform is
> missing. (Gustavo)
>
> v3:
> - Call get_soc_bw_params() only after the check on
> HAS_DISPLAY(display). (Jani)
> - Combine if-ladder branches for adl_s_bw_params into a single one.
> (Matt)
> - Flatten if-ladder by checking for WCL before PTL (as opposed to
> checking for WCL inside the brace for PTL). (Matt)
> - Bail out of intel_bw_init_hw() if display version is below 11.
> (Gustavo)
>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_bw.c | 162 ++++++++++++++++++++++----------
> 1 file changed, 114 insertions(+), 48 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
> index 7eef693b51ad..351ecf741b54 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.c
> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> @@ -372,81 +372,144 @@ static int icl_sagv_max_dclk(const struct intel_qgv_info *qi)
> return dclk;
> }
>
> +struct intel_soc_bw_params {
> + u8 deprogbwlimit;
> + u8 derating;
> +};
> +
> +static const struct intel_soc_bw_params icl_bw_params = {
> + .deprogbwlimit = 25,
> + .derating = 10,
> +};
> +
> +static const struct intel_soc_bw_params tgl_bw_params = {
> + .deprogbwlimit = 34,
> + .derating = 10,
> +};
> +
> +static const struct intel_soc_bw_params rkl_bw_params = {
> + .deprogbwlimit = 20,
> + .derating = 10,
> +};
> +
> +static const struct intel_soc_bw_params adl_s_bw_params = {
> + .deprogbwlimit = 38,
> + .derating = 10,
> +};
> +
> +static const struct intel_soc_bw_params adl_p_bw_params = {
> + .deprogbwlimit = 38,
> + .derating = 20,
> +};
> +
> +static const struct intel_soc_bw_params bmg_bw_params = {
> + .deprogbwlimit = 53,
> + .derating = 30,
> +};
> +
> +static const struct intel_soc_bw_params bmg_ecc_bw_params = {
> + .deprogbwlimit = 53,
> + .derating = 45,
> +};
> +
> +static const struct intel_soc_bw_params ptl_bw_params = {
> + .deprogbwlimit = 65,
> + .derating = 10,
> +};
> +
> +static const struct intel_soc_bw_params wcl_bw_params = {
> + .deprogbwlimit = 22,
> + .derating = 10,
> +};
> +
> +static const struct intel_soc_bw_params *get_soc_bw_params(struct intel_display *display)
> +{
> + if (display->platform.dgfx) {
> + if (display->platform.dg1) {
> + return &tgl_bw_params;
> + } else if (display->platform.battlemage) {
> + const struct dram_info *dram_info = intel_dram_info(display);
> +
> + if (dram_info->type == INTEL_DRAM_GDDR_ECC)
> + return &bmg_ecc_bw_params;
> + else
> + return &bmg_bw_params;
> + }
> + } else {
> + if (display->platform.icelake ||
> + display->platform.jasperlake ||
> + display->platform.elkhartlake)
> + return &icl_bw_params;
> + else if (display->platform.tigerlake)
> + return &tgl_bw_params;
> + else if (display->platform.rocketlake)
> + return &rkl_bw_params;
> + else if (display->platform.alderlake_s ||
> + display->platform.meteorlake ||
> + display->platform.lunarlake)
> + return &adl_s_bw_params;
> + else if (display->platform.alderlake_p)
> + return &adl_p_bw_params;
> + else if (display->platform.pantherlake_wildcatlake)
> + return &wcl_bw_params;
> + else if (display->platform.pantherlake ||
> + display->platform.novalake)
> + return &ptl_bw_params;
> + }
> +
> + drm_WARN(display->drm, 1, "Platform-specific bandwidth parameters not found!\n");
CI shows the warning because DG2 does not use bandwidth
parameters and get_soc_bw_params() rightfully does not cover DG2.
We could just get rid of the warnings in get_soc_bw_params() and
get_display_bw_params() all together. The idea of the warning was to
serve as an aid to the developer, but I guess tracing the null pointer
dereference back to those functions shouldn't be too hard?
Another idea is to make sure that only the functions that use those
parameters make the call to get_{soc,display}_bw_params().
Jani, I know you preferred the other way around, but maybe this is a
compelling reason for moving the call to the direct users?
--
Gustavo Sousa
> +
> + return NULL;
> +}
> +
> struct intel_sa_info {
> u16 displayrtids;
> - u8 deburst, deprogbwlimit, derating;
> + u8 deburst;
> };
>
> static const struct intel_sa_info icl_sa_info = {
> .deburst = 8,
> - .deprogbwlimit = 25, /* GB/s */
> .displayrtids = 128,
> - .derating = 10,
> };
>
> static const struct intel_sa_info tgl_sa_info = {
> .deburst = 16,
> - .deprogbwlimit = 34, /* GB/s */
> .displayrtids = 256,
> - .derating = 10,
> };
>
> static const struct intel_sa_info rkl_sa_info = {
> .deburst = 8,
> - .deprogbwlimit = 20, /* GB/s */
> .displayrtids = 128,
> - .derating = 10,
> };
>
> static const struct intel_sa_info adls_sa_info = {
> .deburst = 16,
> - .deprogbwlimit = 38, /* GB/s */
> .displayrtids = 256,
> - .derating = 10,
> };
>
> static const struct intel_sa_info adlp_sa_info = {
> .deburst = 16,
> - .deprogbwlimit = 38, /* GB/s */
> .displayrtids = 256,
> - .derating = 20,
> };
>
> static const struct intel_sa_info mtl_sa_info = {
> .deburst = 32,
> - .deprogbwlimit = 38, /* GB/s */
> .displayrtids = 256,
> - .derating = 10,
> -};
> -
> -static const struct intel_sa_info xe2_hpd_sa_info = {
> - .derating = 30,
> - .deprogbwlimit = 53,
> - /* Other values not used by simplified algorithm */
> -};
> -
> -static const struct intel_sa_info xe2_hpd_ecc_sa_info = {
> - .derating = 45,
> - .deprogbwlimit = 53,
> - /* Other values not used by simplified algorithm */
> };
>
> static const struct intel_sa_info xe3lpd_sa_info = {
> .deburst = 32,
> - .deprogbwlimit = 65, /* GB/s */
> .displayrtids = 256,
> - .derating = 10,
> };
>
> static const struct intel_sa_info xe3lpd_3002_sa_info = {
> .deburst = 32,
> - .deprogbwlimit = 22, /* GB/s */
> .displayrtids = 256,
> - .derating = 10,
> };
>
> static int icl_get_bw_info(struct intel_display *display,
> const struct dram_info *dram_info,
> + const struct intel_soc_bw_params *soc_bw_params,
> const struct intel_sa_info *sa)
> {
> struct intel_qgv_info qi = {};
> @@ -466,7 +529,7 @@ static int icl_get_bw_info(struct intel_display *display,
> }
>
> dclk_max = icl_sagv_max_dclk(&qi);
> - maxdebw = min(sa->deprogbwlimit * 1000, dclk_max * 16 * 6 / 10);
> + maxdebw = min(soc_bw_params->deprogbwlimit * 1000, dclk_max * 16 * 6 / 10);
> ipqdepth = min(ipqdepthpch, sa->displayrtids / num_channels);
> qi.deinterleave = DIV_ROUND_UP(num_channels, is_y_tile ? 4 : 2);
>
> @@ -496,7 +559,7 @@ static int icl_get_bw_info(struct intel_display *display,
> bw = DIV_ROUND_UP(sp->dclk * clpchgroup * 32 * num_channels, ct);
>
> bi->deratedbw[j] = min(maxdebw,
> - bw * (100 - sa->derating) / 100);
> + bw * (100 - soc_bw_params->derating) / 100);
>
> drm_dbg_kms(display->drm,
> "BW%d / QGV %d: num_planes=%d deratedbw=%u\n",
> @@ -518,6 +581,7 @@ static int icl_get_bw_info(struct intel_display *display,
>
> static int tgl_get_bw_info(struct intel_display *display,
> const struct dram_info *dram_info,
> + const struct intel_soc_bw_params *soc_bw_params,
> const struct intel_sa_info *sa)
> {
> struct intel_qgv_info qi = {};
> @@ -554,7 +618,7 @@ static int tgl_get_bw_info(struct intel_display *display,
> dclk_max = icl_sagv_max_dclk(&qi);
>
> peakbw = num_channels * DIV_ROUND_UP(qi.channel_width, 8) * dclk_max;
> - maxdebw = min(sa->deprogbwlimit * 1000, peakbw * DEPROGBWPCLIMIT / 100);
> + maxdebw = min(soc_bw_params->deprogbwlimit * 1000, peakbw * DEPROGBWPCLIMIT / 100);
>
> ipqdepth = min(ipqdepthpch, sa->displayrtids / num_channels);
> /*
> @@ -599,7 +663,7 @@ static int tgl_get_bw_info(struct intel_display *display,
> bw = DIV_ROUND_UP(sp->dclk * clpchgroup * 32 * num_channels, ct);
>
> bi->deratedbw[j] = min(maxdebw,
> - bw * (100 - sa->derating) / 100);
> + bw * (100 - soc_bw_params->derating) / 100);
> bi->peakbw[j] = DIV_ROUND_CLOSEST(sp->dclk *
> num_channels *
> qi.channel_width, 8);
> @@ -661,7 +725,7 @@ static void dg2_get_bw_info(struct intel_display *display)
>
> static int xe2_hpd_get_bw_info(struct intel_display *display,
> const struct dram_info *dram_info,
> - const struct intel_sa_info *sa)
> + const struct intel_soc_bw_params *soc_bw_params)
> {
> struct intel_qgv_info qi = {};
> int num_channels = dram_info->num_channels;
> @@ -676,14 +740,14 @@ static int xe2_hpd_get_bw_info(struct intel_display *display,
> }
>
> peakbw = num_channels * qi.channel_width / 8 * icl_sagv_max_dclk(&qi);
> - maxdebw = min(sa->deprogbwlimit * 1000, peakbw * DEPROGBWPCLIMIT / 10);
> + maxdebw = min(soc_bw_params->deprogbwlimit * 1000, peakbw * DEPROGBWPCLIMIT / 10);
>
> for (i = 0; i < qi.num_points; i++) {
> const struct intel_qgv_point *point = &qi.points[i];
> int bw = num_channels * (qi.channel_width / 8) * point->dclk;
>
> display->bw.max[0].deratedbw[i] =
> - min(maxdebw, (100 - sa->derating) * bw / 100);
> + min(maxdebw, (100 - soc_bw_params->derating) * bw / 100);
> display->bw.max[0].peakbw[i] = bw;
>
> drm_dbg_kms(display->drm, "QGV %d: deratedbw=%u peakbw: %u\n",
> @@ -792,11 +856,16 @@ static unsigned int icl_qgv_bw(struct intel_display *display,
> void intel_bw_init_hw(struct intel_display *display)
> {
> const struct dram_info *dram_info;
> + const struct intel_soc_bw_params *soc_bw_params;
>
> if (!HAS_DISPLAY(display))
> return;
>
> + if (DISPLAY_VER(display) < 11)
> + return;
> +
> dram_info = intel_dram_info(display);
> + soc_bw_params = get_soc_bw_params(display);
>
> /*
> * Starting with Xe3p_LPD, the hardware tells us whether memory has ECC
> @@ -809,28 +878,25 @@ void intel_bw_init_hw(struct intel_display *display)
>
> if (DISPLAY_VER(display) >= 30) {
> if (DISPLAY_VERx100(display) == 3002)
> - tgl_get_bw_info(display, dram_info, &xe3lpd_3002_sa_info);
> + tgl_get_bw_info(display, dram_info, soc_bw_params, &xe3lpd_3002_sa_info);
> else
> - tgl_get_bw_info(display, dram_info, &xe3lpd_sa_info);
> + tgl_get_bw_info(display, dram_info, soc_bw_params, &xe3lpd_sa_info);
> } else if (DISPLAY_VERx100(display) >= 1401 && display->platform.dgfx) {
> - if (dram_info->type == INTEL_DRAM_GDDR_ECC)
> - xe2_hpd_get_bw_info(display, dram_info, &xe2_hpd_ecc_sa_info);
> - else
> - xe2_hpd_get_bw_info(display, dram_info, &xe2_hpd_sa_info);
> + xe2_hpd_get_bw_info(display, dram_info, soc_bw_params);
> } else if (DISPLAY_VER(display) >= 14) {
> - tgl_get_bw_info(display, dram_info, &mtl_sa_info);
> + tgl_get_bw_info(display, dram_info, soc_bw_params, &mtl_sa_info);
> } else if (display->platform.dg2) {
> dg2_get_bw_info(display);
> } else if (display->platform.alderlake_p) {
> - tgl_get_bw_info(display, dram_info, &adlp_sa_info);
> + tgl_get_bw_info(display, dram_info, soc_bw_params, &adlp_sa_info);
> } else if (display->platform.alderlake_s) {
> - tgl_get_bw_info(display, dram_info, &adls_sa_info);
> + tgl_get_bw_info(display, dram_info, soc_bw_params, &adls_sa_info);
> } else if (display->platform.rocketlake) {
> - tgl_get_bw_info(display, dram_info, &rkl_sa_info);
> + tgl_get_bw_info(display, dram_info, soc_bw_params, &rkl_sa_info);
> } else if (DISPLAY_VER(display) == 12) {
> - tgl_get_bw_info(display, dram_info, &tgl_sa_info);
> + tgl_get_bw_info(display, dram_info, soc_bw_params, &tgl_sa_info);
> } else if (DISPLAY_VER(display) == 11) {
> - icl_get_bw_info(display, dram_info, &icl_sa_info);
> + icl_get_bw_info(display, dram_info, soc_bw_params, &icl_sa_info);
> }
> }
>
>
> --
> 2.53.0
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v3 2/5] drm/i915/bw: Extract platform-specific parameters
2026-05-15 15:41 ` Gustavo Sousa
@ 2026-05-15 16:49 ` Jani Nikula
2026-05-15 17:54 ` Gustavo Sousa
0 siblings, 1 reply; 15+ messages in thread
From: Jani Nikula @ 2026-05-15 16:49 UTC (permalink / raw)
To: Gustavo Sousa, intel-gfx, intel-xe; +Cc: Matt Roper, Rodrigo Vivi
On Fri, 15 May 2026, Gustavo Sousa <gustavo.sousa@intel.com> wrote:
> Gustavo Sousa <gustavo.sousa@intel.com> writes:
>
>> We got confirmation from the hardware team that the bandwidth parameters
>> deprogbwlimit and derating are platform-specific and not tied to the
>> display IP. As such, let's make sure that we use platform checks for
>> those.
>>
>> The rest of the members of struct intel_sa_info are tied to the display
>> IP and we will deal with them as a follow-up.
>>
>> v2:
>> - Use good old if-ladder instead of weird-looking pattern "assign ret,
>> check platform, then return ret". (Jani, Matt)
>> - Have a single call site for get_platform_bw_params() and pass the
>> result as parameter to the *_get_bw_info() functions. (Jani)
>> - Avoid using "plat" as abbreviation for "platform". (Jani)
>> - s/_plat_bw_params/_bw_params/, since all of the instances are
>> prefixed with platform names. (Jani)
>> - s/struct intel_platform_bw_params/struct intel_soc_bw_params/.
>> (Matt)
>> - Do not return a default value; prefer to return NULL and
>> intentionally cause a NULL pointer dereference if a platform is
>> missing. (Gustavo)
>>
>> v3:
>> - Call get_soc_bw_params() only after the check on
>> HAS_DISPLAY(display). (Jani)
>> - Combine if-ladder branches for adl_s_bw_params into a single one.
>> (Matt)
>> - Flatten if-ladder by checking for WCL before PTL (as opposed to
>> checking for WCL inside the brace for PTL). (Matt)
>> - Bail out of intel_bw_init_hw() if display version is below 11.
>> (Gustavo)
>>
>> Cc: Jani Nikula <jani.nikula@intel.com>
>> Cc: Matt Roper <matthew.d.roper@intel.com>
>> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
>> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
>> ---
>> drivers/gpu/drm/i915/display/intel_bw.c | 162 ++++++++++++++++++++++----------
>> 1 file changed, 114 insertions(+), 48 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
>> index 7eef693b51ad..351ecf741b54 100644
>> --- a/drivers/gpu/drm/i915/display/intel_bw.c
>> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
>> @@ -372,81 +372,144 @@ static int icl_sagv_max_dclk(const struct intel_qgv_info *qi)
>> return dclk;
>> }
>>
>> +struct intel_soc_bw_params {
>> + u8 deprogbwlimit;
>> + u8 derating;
>> +};
>> +
>> +static const struct intel_soc_bw_params icl_bw_params = {
>> + .deprogbwlimit = 25,
>> + .derating = 10,
>> +};
>> +
>> +static const struct intel_soc_bw_params tgl_bw_params = {
>> + .deprogbwlimit = 34,
>> + .derating = 10,
>> +};
>> +
>> +static const struct intel_soc_bw_params rkl_bw_params = {
>> + .deprogbwlimit = 20,
>> + .derating = 10,
>> +};
>> +
>> +static const struct intel_soc_bw_params adl_s_bw_params = {
>> + .deprogbwlimit = 38,
>> + .derating = 10,
>> +};
>> +
>> +static const struct intel_soc_bw_params adl_p_bw_params = {
>> + .deprogbwlimit = 38,
>> + .derating = 20,
>> +};
>> +
>> +static const struct intel_soc_bw_params bmg_bw_params = {
>> + .deprogbwlimit = 53,
>> + .derating = 30,
>> +};
>> +
>> +static const struct intel_soc_bw_params bmg_ecc_bw_params = {
>> + .deprogbwlimit = 53,
>> + .derating = 45,
>> +};
>> +
>> +static const struct intel_soc_bw_params ptl_bw_params = {
>> + .deprogbwlimit = 65,
>> + .derating = 10,
>> +};
>> +
>> +static const struct intel_soc_bw_params wcl_bw_params = {
>> + .deprogbwlimit = 22,
>> + .derating = 10,
>> +};
>> +
>> +static const struct intel_soc_bw_params *get_soc_bw_params(struct intel_display *display)
>> +{
>> + if (display->platform.dgfx) {
>> + if (display->platform.dg1) {
>> + return &tgl_bw_params;
>> + } else if (display->platform.battlemage) {
>> + const struct dram_info *dram_info = intel_dram_info(display);
>> +
>> + if (dram_info->type == INTEL_DRAM_GDDR_ECC)
>> + return &bmg_ecc_bw_params;
>> + else
>> + return &bmg_bw_params;
>> + }
>> + } else {
>> + if (display->platform.icelake ||
>> + display->platform.jasperlake ||
>> + display->platform.elkhartlake)
>> + return &icl_bw_params;
>> + else if (display->platform.tigerlake)
>> + return &tgl_bw_params;
>> + else if (display->platform.rocketlake)
>> + return &rkl_bw_params;
>> + else if (display->platform.alderlake_s ||
>> + display->platform.meteorlake ||
>> + display->platform.lunarlake)
>> + return &adl_s_bw_params;
>> + else if (display->platform.alderlake_p)
>> + return &adl_p_bw_params;
>> + else if (display->platform.pantherlake_wildcatlake)
>> + return &wcl_bw_params;
>> + else if (display->platform.pantherlake ||
>> + display->platform.novalake)
>> + return &ptl_bw_params;
>> + }
>> +
>> + drm_WARN(display->drm, 1, "Platform-specific bandwidth parameters not found!\n");
>
> CI shows the warning because DG2 does not use bandwidth
> parameters and get_soc_bw_params() rightfully does not cover DG2.
>
> We could just get rid of the warnings in get_soc_bw_params() and
> get_display_bw_params() all together. The idea of the warning was to
> serve as an aid to the developer, but I guess tracing the null pointer
> dereference back to those functions shouldn't be too hard?
>
> Another idea is to make sure that only the functions that use those
> parameters make the call to get_{soc,display}_bw_params().
>
> Jani, I know you preferred the other way around, but maybe this is a
> compelling reason for moving the call to the direct users?
I still prefer figuring the pointer out early, and passing it around to
the places that need it. Actually, ditto for dram_info above. I
refactored this stuff once to call intel_dram_info() once, and pass the
pointer around.
I think the alternatives are:
- Remove the drm_WARN() altogether.
- Return NULL directly for platforms where the parameters don't make
sense, e.g. DG2.
BR,
Jani.
>
> --
> Gustavo Sousa
>
>> +
>> + return NULL;
>> +}
>> +
>> struct intel_sa_info {
>> u16 displayrtids;
>> - u8 deburst, deprogbwlimit, derating;
>> + u8 deburst;
>> };
>>
>> static const struct intel_sa_info icl_sa_info = {
>> .deburst = 8,
>> - .deprogbwlimit = 25, /* GB/s */
>> .displayrtids = 128,
>> - .derating = 10,
>> };
>>
>> static const struct intel_sa_info tgl_sa_info = {
>> .deburst = 16,
>> - .deprogbwlimit = 34, /* GB/s */
>> .displayrtids = 256,
>> - .derating = 10,
>> };
>>
>> static const struct intel_sa_info rkl_sa_info = {
>> .deburst = 8,
>> - .deprogbwlimit = 20, /* GB/s */
>> .displayrtids = 128,
>> - .derating = 10,
>> };
>>
>> static const struct intel_sa_info adls_sa_info = {
>> .deburst = 16,
>> - .deprogbwlimit = 38, /* GB/s */
>> .displayrtids = 256,
>> - .derating = 10,
>> };
>>
>> static const struct intel_sa_info adlp_sa_info = {
>> .deburst = 16,
>> - .deprogbwlimit = 38, /* GB/s */
>> .displayrtids = 256,
>> - .derating = 20,
>> };
>>
>> static const struct intel_sa_info mtl_sa_info = {
>> .deburst = 32,
>> - .deprogbwlimit = 38, /* GB/s */
>> .displayrtids = 256,
>> - .derating = 10,
>> -};
>> -
>> -static const struct intel_sa_info xe2_hpd_sa_info = {
>> - .derating = 30,
>> - .deprogbwlimit = 53,
>> - /* Other values not used by simplified algorithm */
>> -};
>> -
>> -static const struct intel_sa_info xe2_hpd_ecc_sa_info = {
>> - .derating = 45,
>> - .deprogbwlimit = 53,
>> - /* Other values not used by simplified algorithm */
>> };
>>
>> static const struct intel_sa_info xe3lpd_sa_info = {
>> .deburst = 32,
>> - .deprogbwlimit = 65, /* GB/s */
>> .displayrtids = 256,
>> - .derating = 10,
>> };
>>
>> static const struct intel_sa_info xe3lpd_3002_sa_info = {
>> .deburst = 32,
>> - .deprogbwlimit = 22, /* GB/s */
>> .displayrtids = 256,
>> - .derating = 10,
>> };
>>
>> static int icl_get_bw_info(struct intel_display *display,
>> const struct dram_info *dram_info,
>> + const struct intel_soc_bw_params *soc_bw_params,
>> const struct intel_sa_info *sa)
>> {
>> struct intel_qgv_info qi = {};
>> @@ -466,7 +529,7 @@ static int icl_get_bw_info(struct intel_display *display,
>> }
>>
>> dclk_max = icl_sagv_max_dclk(&qi);
>> - maxdebw = min(sa->deprogbwlimit * 1000, dclk_max * 16 * 6 / 10);
>> + maxdebw = min(soc_bw_params->deprogbwlimit * 1000, dclk_max * 16 * 6 / 10);
>> ipqdepth = min(ipqdepthpch, sa->displayrtids / num_channels);
>> qi.deinterleave = DIV_ROUND_UP(num_channels, is_y_tile ? 4 : 2);
>>
>> @@ -496,7 +559,7 @@ static int icl_get_bw_info(struct intel_display *display,
>> bw = DIV_ROUND_UP(sp->dclk * clpchgroup * 32 * num_channels, ct);
>>
>> bi->deratedbw[j] = min(maxdebw,
>> - bw * (100 - sa->derating) / 100);
>> + bw * (100 - soc_bw_params->derating) / 100);
>>
>> drm_dbg_kms(display->drm,
>> "BW%d / QGV %d: num_planes=%d deratedbw=%u\n",
>> @@ -518,6 +581,7 @@ static int icl_get_bw_info(struct intel_display *display,
>>
>> static int tgl_get_bw_info(struct intel_display *display,
>> const struct dram_info *dram_info,
>> + const struct intel_soc_bw_params *soc_bw_params,
>> const struct intel_sa_info *sa)
>> {
>> struct intel_qgv_info qi = {};
>> @@ -554,7 +618,7 @@ static int tgl_get_bw_info(struct intel_display *display,
>> dclk_max = icl_sagv_max_dclk(&qi);
>>
>> peakbw = num_channels * DIV_ROUND_UP(qi.channel_width, 8) * dclk_max;
>> - maxdebw = min(sa->deprogbwlimit * 1000, peakbw * DEPROGBWPCLIMIT / 100);
>> + maxdebw = min(soc_bw_params->deprogbwlimit * 1000, peakbw * DEPROGBWPCLIMIT / 100);
>>
>> ipqdepth = min(ipqdepthpch, sa->displayrtids / num_channels);
>> /*
>> @@ -599,7 +663,7 @@ static int tgl_get_bw_info(struct intel_display *display,
>> bw = DIV_ROUND_UP(sp->dclk * clpchgroup * 32 * num_channels, ct);
>>
>> bi->deratedbw[j] = min(maxdebw,
>> - bw * (100 - sa->derating) / 100);
>> + bw * (100 - soc_bw_params->derating) / 100);
>> bi->peakbw[j] = DIV_ROUND_CLOSEST(sp->dclk *
>> num_channels *
>> qi.channel_width, 8);
>> @@ -661,7 +725,7 @@ static void dg2_get_bw_info(struct intel_display *display)
>>
>> static int xe2_hpd_get_bw_info(struct intel_display *display,
>> const struct dram_info *dram_info,
>> - const struct intel_sa_info *sa)
>> + const struct intel_soc_bw_params *soc_bw_params)
>> {
>> struct intel_qgv_info qi = {};
>> int num_channels = dram_info->num_channels;
>> @@ -676,14 +740,14 @@ static int xe2_hpd_get_bw_info(struct intel_display *display,
>> }
>>
>> peakbw = num_channels * qi.channel_width / 8 * icl_sagv_max_dclk(&qi);
>> - maxdebw = min(sa->deprogbwlimit * 1000, peakbw * DEPROGBWPCLIMIT / 10);
>> + maxdebw = min(soc_bw_params->deprogbwlimit * 1000, peakbw * DEPROGBWPCLIMIT / 10);
>>
>> for (i = 0; i < qi.num_points; i++) {
>> const struct intel_qgv_point *point = &qi.points[i];
>> int bw = num_channels * (qi.channel_width / 8) * point->dclk;
>>
>> display->bw.max[0].deratedbw[i] =
>> - min(maxdebw, (100 - sa->derating) * bw / 100);
>> + min(maxdebw, (100 - soc_bw_params->derating) * bw / 100);
>> display->bw.max[0].peakbw[i] = bw;
>>
>> drm_dbg_kms(display->drm, "QGV %d: deratedbw=%u peakbw: %u\n",
>> @@ -792,11 +856,16 @@ static unsigned int icl_qgv_bw(struct intel_display *display,
>> void intel_bw_init_hw(struct intel_display *display)
>> {
>> const struct dram_info *dram_info;
>> + const struct intel_soc_bw_params *soc_bw_params;
>>
>> if (!HAS_DISPLAY(display))
>> return;
>>
>> + if (DISPLAY_VER(display) < 11)
>> + return;
>> +
>> dram_info = intel_dram_info(display);
>> + soc_bw_params = get_soc_bw_params(display);
>>
>> /*
>> * Starting with Xe3p_LPD, the hardware tells us whether memory has ECC
>> @@ -809,28 +878,25 @@ void intel_bw_init_hw(struct intel_display *display)
>>
>> if (DISPLAY_VER(display) >= 30) {
>> if (DISPLAY_VERx100(display) == 3002)
>> - tgl_get_bw_info(display, dram_info, &xe3lpd_3002_sa_info);
>> + tgl_get_bw_info(display, dram_info, soc_bw_params, &xe3lpd_3002_sa_info);
>> else
>> - tgl_get_bw_info(display, dram_info, &xe3lpd_sa_info);
>> + tgl_get_bw_info(display, dram_info, soc_bw_params, &xe3lpd_sa_info);
>> } else if (DISPLAY_VERx100(display) >= 1401 && display->platform.dgfx) {
>> - if (dram_info->type == INTEL_DRAM_GDDR_ECC)
>> - xe2_hpd_get_bw_info(display, dram_info, &xe2_hpd_ecc_sa_info);
>> - else
>> - xe2_hpd_get_bw_info(display, dram_info, &xe2_hpd_sa_info);
>> + xe2_hpd_get_bw_info(display, dram_info, soc_bw_params);
>> } else if (DISPLAY_VER(display) >= 14) {
>> - tgl_get_bw_info(display, dram_info, &mtl_sa_info);
>> + tgl_get_bw_info(display, dram_info, soc_bw_params, &mtl_sa_info);
>> } else if (display->platform.dg2) {
>> dg2_get_bw_info(display);
>> } else if (display->platform.alderlake_p) {
>> - tgl_get_bw_info(display, dram_info, &adlp_sa_info);
>> + tgl_get_bw_info(display, dram_info, soc_bw_params, &adlp_sa_info);
>> } else if (display->platform.alderlake_s) {
>> - tgl_get_bw_info(display, dram_info, &adls_sa_info);
>> + tgl_get_bw_info(display, dram_info, soc_bw_params, &adls_sa_info);
>> } else if (display->platform.rocketlake) {
>> - tgl_get_bw_info(display, dram_info, &rkl_sa_info);
>> + tgl_get_bw_info(display, dram_info, soc_bw_params, &rkl_sa_info);
>> } else if (DISPLAY_VER(display) == 12) {
>> - tgl_get_bw_info(display, dram_info, &tgl_sa_info);
>> + tgl_get_bw_info(display, dram_info, soc_bw_params, &tgl_sa_info);
>> } else if (DISPLAY_VER(display) == 11) {
>> - icl_get_bw_info(display, dram_info, &icl_sa_info);
>> + icl_get_bw_info(display, dram_info, soc_bw_params, &icl_sa_info);
>> }
>> }
>>
>>
>> --
>> 2.53.0
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v3 2/5] drm/i915/bw: Extract platform-specific parameters
2026-05-15 16:49 ` Jani Nikula
@ 2026-05-15 17:54 ` Gustavo Sousa
0 siblings, 0 replies; 15+ messages in thread
From: Gustavo Sousa @ 2026-05-15 17:54 UTC (permalink / raw)
To: Jani Nikula, intel-gfx, intel-xe; +Cc: Matt Roper, Rodrigo Vivi
Jani Nikula <jani.nikula@intel.com> writes:
> On Fri, 15 May 2026, Gustavo Sousa <gustavo.sousa@intel.com> wrote:
>> Gustavo Sousa <gustavo.sousa@intel.com> writes:
>>
>>> We got confirmation from the hardware team that the bandwidth parameters
>>> deprogbwlimit and derating are platform-specific and not tied to the
>>> display IP. As such, let's make sure that we use platform checks for
>>> those.
>>>
>>> The rest of the members of struct intel_sa_info are tied to the display
>>> IP and we will deal with them as a follow-up.
>>>
>>> v2:
>>> - Use good old if-ladder instead of weird-looking pattern "assign ret,
>>> check platform, then return ret". (Jani, Matt)
>>> - Have a single call site for get_platform_bw_params() and pass the
>>> result as parameter to the *_get_bw_info() functions. (Jani)
>>> - Avoid using "plat" as abbreviation for "platform". (Jani)
>>> - s/_plat_bw_params/_bw_params/, since all of the instances are
>>> prefixed with platform names. (Jani)
>>> - s/struct intel_platform_bw_params/struct intel_soc_bw_params/.
>>> (Matt)
>>> - Do not return a default value; prefer to return NULL and
>>> intentionally cause a NULL pointer dereference if a platform is
>>> missing. (Gustavo)
>>>
>>> v3:
>>> - Call get_soc_bw_params() only after the check on
>>> HAS_DISPLAY(display). (Jani)
>>> - Combine if-ladder branches for adl_s_bw_params into a single one.
>>> (Matt)
>>> - Flatten if-ladder by checking for WCL before PTL (as opposed to
>>> checking for WCL inside the brace for PTL). (Matt)
>>> - Bail out of intel_bw_init_hw() if display version is below 11.
>>> (Gustavo)
>>>
>>> Cc: Jani Nikula <jani.nikula@intel.com>
>>> Cc: Matt Roper <matthew.d.roper@intel.com>
>>> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
>>> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
>>> ---
>>> drivers/gpu/drm/i915/display/intel_bw.c | 162 ++++++++++++++++++++++----------
>>> 1 file changed, 114 insertions(+), 48 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
>>> index 7eef693b51ad..351ecf741b54 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_bw.c
>>> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
>>> @@ -372,81 +372,144 @@ static int icl_sagv_max_dclk(const struct intel_qgv_info *qi)
>>> return dclk;
>>> }
>>>
>>> +struct intel_soc_bw_params {
>>> + u8 deprogbwlimit;
>>> + u8 derating;
>>> +};
>>> +
>>> +static const struct intel_soc_bw_params icl_bw_params = {
>>> + .deprogbwlimit = 25,
>>> + .derating = 10,
>>> +};
>>> +
>>> +static const struct intel_soc_bw_params tgl_bw_params = {
>>> + .deprogbwlimit = 34,
>>> + .derating = 10,
>>> +};
>>> +
>>> +static const struct intel_soc_bw_params rkl_bw_params = {
>>> + .deprogbwlimit = 20,
>>> + .derating = 10,
>>> +};
>>> +
>>> +static const struct intel_soc_bw_params adl_s_bw_params = {
>>> + .deprogbwlimit = 38,
>>> + .derating = 10,
>>> +};
>>> +
>>> +static const struct intel_soc_bw_params adl_p_bw_params = {
>>> + .deprogbwlimit = 38,
>>> + .derating = 20,
>>> +};
>>> +
>>> +static const struct intel_soc_bw_params bmg_bw_params = {
>>> + .deprogbwlimit = 53,
>>> + .derating = 30,
>>> +};
>>> +
>>> +static const struct intel_soc_bw_params bmg_ecc_bw_params = {
>>> + .deprogbwlimit = 53,
>>> + .derating = 45,
>>> +};
>>> +
>>> +static const struct intel_soc_bw_params ptl_bw_params = {
>>> + .deprogbwlimit = 65,
>>> + .derating = 10,
>>> +};
>>> +
>>> +static const struct intel_soc_bw_params wcl_bw_params = {
>>> + .deprogbwlimit = 22,
>>> + .derating = 10,
>>> +};
>>> +
>>> +static const struct intel_soc_bw_params *get_soc_bw_params(struct intel_display *display)
>>> +{
>>> + if (display->platform.dgfx) {
>>> + if (display->platform.dg1) {
>>> + return &tgl_bw_params;
>>> + } else if (display->platform.battlemage) {
>>> + const struct dram_info *dram_info = intel_dram_info(display);
>>> +
>>> + if (dram_info->type == INTEL_DRAM_GDDR_ECC)
>>> + return &bmg_ecc_bw_params;
>>> + else
>>> + return &bmg_bw_params;
>>> + }
>>> + } else {
>>> + if (display->platform.icelake ||
>>> + display->platform.jasperlake ||
>>> + display->platform.elkhartlake)
>>> + return &icl_bw_params;
>>> + else if (display->platform.tigerlake)
>>> + return &tgl_bw_params;
>>> + else if (display->platform.rocketlake)
>>> + return &rkl_bw_params;
>>> + else if (display->platform.alderlake_s ||
>>> + display->platform.meteorlake ||
>>> + display->platform.lunarlake)
>>> + return &adl_s_bw_params;
>>> + else if (display->platform.alderlake_p)
>>> + return &adl_p_bw_params;
>>> + else if (display->platform.pantherlake_wildcatlake)
>>> + return &wcl_bw_params;
>>> + else if (display->platform.pantherlake ||
>>> + display->platform.novalake)
>>> + return &ptl_bw_params;
>>> + }
>>> +
>>> + drm_WARN(display->drm, 1, "Platform-specific bandwidth parameters not found!\n");
>>
>> CI shows the warning because DG2 does not use bandwidth
>> parameters and get_soc_bw_params() rightfully does not cover DG2.
>>
>> We could just get rid of the warnings in get_soc_bw_params() and
>> get_display_bw_params() all together. The idea of the warning was to
>> serve as an aid to the developer, but I guess tracing the null pointer
>> dereference back to those functions shouldn't be too hard?
>>
>> Another idea is to make sure that only the functions that use those
>> parameters make the call to get_{soc,display}_bw_params().
>>
>> Jani, I know you preferred the other way around, but maybe this is a
>> compelling reason for moving the call to the direct users?
>
> I still prefer figuring the pointer out early, and passing it around to
> the places that need it. Actually, ditto for dram_info above. I
Ack.
> refactored this stuff once to call intel_dram_info() once, and pass the
> pointer around.
>
> I think the alternatives are:
>
> - Remove the drm_WARN() altogether.
Okay. I think I'll just take the easy way out by dropping them in the
next iteration.
--
Gustavo Sousa
>
> - Return NULL directly for platforms where the parameters don't make
> sense, e.g. DG2.
>
> BR,
> Jani.
>
>>
>> --
>> Gustavo Sousa
>>
>>> +
>>> + return NULL;
>>> +}
>>> +
>>> struct intel_sa_info {
>>> u16 displayrtids;
>>> - u8 deburst, deprogbwlimit, derating;
>>> + u8 deburst;
>>> };
>>>
>>> static const struct intel_sa_info icl_sa_info = {
>>> .deburst = 8,
>>> - .deprogbwlimit = 25, /* GB/s */
>>> .displayrtids = 128,
>>> - .derating = 10,
>>> };
>>>
>>> static const struct intel_sa_info tgl_sa_info = {
>>> .deburst = 16,
>>> - .deprogbwlimit = 34, /* GB/s */
>>> .displayrtids = 256,
>>> - .derating = 10,
>>> };
>>>
>>> static const struct intel_sa_info rkl_sa_info = {
>>> .deburst = 8,
>>> - .deprogbwlimit = 20, /* GB/s */
>>> .displayrtids = 128,
>>> - .derating = 10,
>>> };
>>>
>>> static const struct intel_sa_info adls_sa_info = {
>>> .deburst = 16,
>>> - .deprogbwlimit = 38, /* GB/s */
>>> .displayrtids = 256,
>>> - .derating = 10,
>>> };
>>>
>>> static const struct intel_sa_info adlp_sa_info = {
>>> .deburst = 16,
>>> - .deprogbwlimit = 38, /* GB/s */
>>> .displayrtids = 256,
>>> - .derating = 20,
>>> };
>>>
>>> static const struct intel_sa_info mtl_sa_info = {
>>> .deburst = 32,
>>> - .deprogbwlimit = 38, /* GB/s */
>>> .displayrtids = 256,
>>> - .derating = 10,
>>> -};
>>> -
>>> -static const struct intel_sa_info xe2_hpd_sa_info = {
>>> - .derating = 30,
>>> - .deprogbwlimit = 53,
>>> - /* Other values not used by simplified algorithm */
>>> -};
>>> -
>>> -static const struct intel_sa_info xe2_hpd_ecc_sa_info = {
>>> - .derating = 45,
>>> - .deprogbwlimit = 53,
>>> - /* Other values not used by simplified algorithm */
>>> };
>>>
>>> static const struct intel_sa_info xe3lpd_sa_info = {
>>> .deburst = 32,
>>> - .deprogbwlimit = 65, /* GB/s */
>>> .displayrtids = 256,
>>> - .derating = 10,
>>> };
>>>
>>> static const struct intel_sa_info xe3lpd_3002_sa_info = {
>>> .deburst = 32,
>>> - .deprogbwlimit = 22, /* GB/s */
>>> .displayrtids = 256,
>>> - .derating = 10,
>>> };
>>>
>>> static int icl_get_bw_info(struct intel_display *display,
>>> const struct dram_info *dram_info,
>>> + const struct intel_soc_bw_params *soc_bw_params,
>>> const struct intel_sa_info *sa)
>>> {
>>> struct intel_qgv_info qi = {};
>>> @@ -466,7 +529,7 @@ static int icl_get_bw_info(struct intel_display *display,
>>> }
>>>
>>> dclk_max = icl_sagv_max_dclk(&qi);
>>> - maxdebw = min(sa->deprogbwlimit * 1000, dclk_max * 16 * 6 / 10);
>>> + maxdebw = min(soc_bw_params->deprogbwlimit * 1000, dclk_max * 16 * 6 / 10);
>>> ipqdepth = min(ipqdepthpch, sa->displayrtids / num_channels);
>>> qi.deinterleave = DIV_ROUND_UP(num_channels, is_y_tile ? 4 : 2);
>>>
>>> @@ -496,7 +559,7 @@ static int icl_get_bw_info(struct intel_display *display,
>>> bw = DIV_ROUND_UP(sp->dclk * clpchgroup * 32 * num_channels, ct);
>>>
>>> bi->deratedbw[j] = min(maxdebw,
>>> - bw * (100 - sa->derating) / 100);
>>> + bw * (100 - soc_bw_params->derating) / 100);
>>>
>>> drm_dbg_kms(display->drm,
>>> "BW%d / QGV %d: num_planes=%d deratedbw=%u\n",
>>> @@ -518,6 +581,7 @@ static int icl_get_bw_info(struct intel_display *display,
>>>
>>> static int tgl_get_bw_info(struct intel_display *display,
>>> const struct dram_info *dram_info,
>>> + const struct intel_soc_bw_params *soc_bw_params,
>>> const struct intel_sa_info *sa)
>>> {
>>> struct intel_qgv_info qi = {};
>>> @@ -554,7 +618,7 @@ static int tgl_get_bw_info(struct intel_display *display,
>>> dclk_max = icl_sagv_max_dclk(&qi);
>>>
>>> peakbw = num_channels * DIV_ROUND_UP(qi.channel_width, 8) * dclk_max;
>>> - maxdebw = min(sa->deprogbwlimit * 1000, peakbw * DEPROGBWPCLIMIT / 100);
>>> + maxdebw = min(soc_bw_params->deprogbwlimit * 1000, peakbw * DEPROGBWPCLIMIT / 100);
>>>
>>> ipqdepth = min(ipqdepthpch, sa->displayrtids / num_channels);
>>> /*
>>> @@ -599,7 +663,7 @@ static int tgl_get_bw_info(struct intel_display *display,
>>> bw = DIV_ROUND_UP(sp->dclk * clpchgroup * 32 * num_channels, ct);
>>>
>>> bi->deratedbw[j] = min(maxdebw,
>>> - bw * (100 - sa->derating) / 100);
>>> + bw * (100 - soc_bw_params->derating) / 100);
>>> bi->peakbw[j] = DIV_ROUND_CLOSEST(sp->dclk *
>>> num_channels *
>>> qi.channel_width, 8);
>>> @@ -661,7 +725,7 @@ static void dg2_get_bw_info(struct intel_display *display)
>>>
>>> static int xe2_hpd_get_bw_info(struct intel_display *display,
>>> const struct dram_info *dram_info,
>>> - const struct intel_sa_info *sa)
>>> + const struct intel_soc_bw_params *soc_bw_params)
>>> {
>>> struct intel_qgv_info qi = {};
>>> int num_channels = dram_info->num_channels;
>>> @@ -676,14 +740,14 @@ static int xe2_hpd_get_bw_info(struct intel_display *display,
>>> }
>>>
>>> peakbw = num_channels * qi.channel_width / 8 * icl_sagv_max_dclk(&qi);
>>> - maxdebw = min(sa->deprogbwlimit * 1000, peakbw * DEPROGBWPCLIMIT / 10);
>>> + maxdebw = min(soc_bw_params->deprogbwlimit * 1000, peakbw * DEPROGBWPCLIMIT / 10);
>>>
>>> for (i = 0; i < qi.num_points; i++) {
>>> const struct intel_qgv_point *point = &qi.points[i];
>>> int bw = num_channels * (qi.channel_width / 8) * point->dclk;
>>>
>>> display->bw.max[0].deratedbw[i] =
>>> - min(maxdebw, (100 - sa->derating) * bw / 100);
>>> + min(maxdebw, (100 - soc_bw_params->derating) * bw / 100);
>>> display->bw.max[0].peakbw[i] = bw;
>>>
>>> drm_dbg_kms(display->drm, "QGV %d: deratedbw=%u peakbw: %u\n",
>>> @@ -792,11 +856,16 @@ static unsigned int icl_qgv_bw(struct intel_display *display,
>>> void intel_bw_init_hw(struct intel_display *display)
>>> {
>>> const struct dram_info *dram_info;
>>> + const struct intel_soc_bw_params *soc_bw_params;
>>>
>>> if (!HAS_DISPLAY(display))
>>> return;
>>>
>>> + if (DISPLAY_VER(display) < 11)
>>> + return;
>>> +
>>> dram_info = intel_dram_info(display);
>>> + soc_bw_params = get_soc_bw_params(display);
>>>
>>> /*
>>> * Starting with Xe3p_LPD, the hardware tells us whether memory has ECC
>>> @@ -809,28 +878,25 @@ void intel_bw_init_hw(struct intel_display *display)
>>>
>>> if (DISPLAY_VER(display) >= 30) {
>>> if (DISPLAY_VERx100(display) == 3002)
>>> - tgl_get_bw_info(display, dram_info, &xe3lpd_3002_sa_info);
>>> + tgl_get_bw_info(display, dram_info, soc_bw_params, &xe3lpd_3002_sa_info);
>>> else
>>> - tgl_get_bw_info(display, dram_info, &xe3lpd_sa_info);
>>> + tgl_get_bw_info(display, dram_info, soc_bw_params, &xe3lpd_sa_info);
>>> } else if (DISPLAY_VERx100(display) >= 1401 && display->platform.dgfx) {
>>> - if (dram_info->type == INTEL_DRAM_GDDR_ECC)
>>> - xe2_hpd_get_bw_info(display, dram_info, &xe2_hpd_ecc_sa_info);
>>> - else
>>> - xe2_hpd_get_bw_info(display, dram_info, &xe2_hpd_sa_info);
>>> + xe2_hpd_get_bw_info(display, dram_info, soc_bw_params);
>>> } else if (DISPLAY_VER(display) >= 14) {
>>> - tgl_get_bw_info(display, dram_info, &mtl_sa_info);
>>> + tgl_get_bw_info(display, dram_info, soc_bw_params, &mtl_sa_info);
>>> } else if (display->platform.dg2) {
>>> dg2_get_bw_info(display);
>>> } else if (display->platform.alderlake_p) {
>>> - tgl_get_bw_info(display, dram_info, &adlp_sa_info);
>>> + tgl_get_bw_info(display, dram_info, soc_bw_params, &adlp_sa_info);
>>> } else if (display->platform.alderlake_s) {
>>> - tgl_get_bw_info(display, dram_info, &adls_sa_info);
>>> + tgl_get_bw_info(display, dram_info, soc_bw_params, &adls_sa_info);
>>> } else if (display->platform.rocketlake) {
>>> - tgl_get_bw_info(display, dram_info, &rkl_sa_info);
>>> + tgl_get_bw_info(display, dram_info, soc_bw_params, &rkl_sa_info);
>>> } else if (DISPLAY_VER(display) == 12) {
>>> - tgl_get_bw_info(display, dram_info, &tgl_sa_info);
>>> + tgl_get_bw_info(display, dram_info, soc_bw_params, &tgl_sa_info);
>>> } else if (DISPLAY_VER(display) == 11) {
>>> - icl_get_bw_info(display, dram_info, &icl_sa_info);
>>> + icl_get_bw_info(display, dram_info, soc_bw_params, &icl_sa_info);
>>> }
>>> }
>>>
>>>
>>> --
>>> 2.53.0
>
> --
> Jani Nikula, Intel
^ permalink raw reply [flat|nested] 15+ messages in thread
end of thread, other threads:[~2026-05-15 17:54 UTC | newest]
Thread overview: 15+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2026-05-14 19:19 [PATCH v3 0/5] drm/i915/bw: Split bandwidth params into platform- and display-IP-specific structs Gustavo Sousa
2026-05-14 19:19 ` [PATCH v3 1/5] drm/i915/bw: Don't call intel_dram_info() too early Gustavo Sousa
2026-05-15 8:26 ` Jani Nikula
2026-05-14 19:19 ` [PATCH v3 2/5] drm/i915/bw: Extract platform-specific parameters Gustavo Sousa
2026-05-15 15:41 ` Gustavo Sousa
2026-05-15 16:49 ` Jani Nikula
2026-05-15 17:54 ` Gustavo Sousa
2026-05-14 19:19 ` [PATCH v3 3/5] drm/i915/bw: Deduplicate intel_sa_info instances Gustavo Sousa
2026-05-14 19:19 ` [PATCH v3 4/5] drm/i915/bw: Rename struct intel_sa_info to intel_display_bw_params Gustavo Sousa
2026-05-14 19:19 ` [PATCH v3 5/5] drm/i915/bw: Extract get_display_bw_params() Gustavo Sousa
2026-05-14 20:16 ` ✓ CI.KUnit: success for drm/i915/bw: Split bandwidth params into platform- and display-IP-specific structs (rev2) Patchwork
2026-05-14 20:36 ` ✗ i915.CI.BAT: failure for drm/i915/bw: Split bandwidth params into platform- and display-IP-specific structs (rev3) Patchwork
2026-05-14 21:26 ` Gustavo Sousa
2026-05-14 21:11 ` ✓ Xe.CI.BAT: success for drm/i915/bw: Split bandwidth params into platform- and display-IP-specific structs (rev2) Patchwork
2026-05-15 14:02 ` ✓ Xe.CI.FULL: " Patchwork
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