Re: [PATCH v4 0/9] Support Zve32[xf] and Zve64[xfd] Vector subextensions - patchwork-bot+linux-riscv

From: patchwork-bot+linux-riscv@kernel.org
To: Andy Chiu <andy.chiu@sifive.com>
Cc: linux-riscv@lists.infradead.org, paul.walmsley@sifive.com,
	palmer@dabbelt.com, aou@eecs.berkeley.edu,
	conor.dooley@microchip.com, heiko@sntech.de, guoren@kernel.org,
	conor@kernel.org, robh@kernel.org,
	krzysztof.kozlowski+dt@linaro.org, corbet@lwn.net,
	evan@rivosinc.com, cleger@rivosinc.com, shuah@kernel.org,
	linux-kernel@vger.kernel.org, palmer@rivosinc.com,
	vincent.chen@sifive.com, greentime.hu@sifive.com,
	devicetree@vger.kernel.org, linux-doc@vger.kernel.org,
	linux-kselftest@vger.kernel.org, j.granados@samsung.com
Subject: Re: [PATCH v4 0/9] Support Zve32[xf] and Zve64[xfd] Vector subextensions
Date: Thu, 25 Apr 2024 23:00:30 +0000	[thread overview]
Message-ID: <171408603081.8761.8620733679475942661.git-patchwork-notify@kernel.org> (raw)
In-Reply-To: <20240412-zve-detection-v4-0-e0c45bb6b253@sifive.com>

Hello:

This series was applied to riscv/linux.git (fixes)
by Palmer Dabbelt <palmer@rivosinc.com>:

On Fri, 12 Apr 2024 14:48:56 +0800 you wrote:
> The series composes of two parts. The first part provides a quick fix for
> the issue on a recent thread[1]. The issue happens when a platform has
> ununified vector register length across multiple cores. Specifically,
> patch 1 adds a comment at a callsite of riscv_setup_vsize to clarify how
> vlenb is observed by the system. Patch 2 fixes the issue by failing the
> boot process of a secondary core if vlenb mismatches.
> 
> [...]

Here is the summary with links:
  - [v4,1/9] riscv: vector: add a comment when calling riscv_setup_vsize()
    (no matching commit)
  - [v4,2/9] riscv: smp: fail booting up smp if inconsistent vlen is detected
    (no matching commit)
  - [v4,3/9] riscv: cpufeature: call match_isa_ext() for single-letter extensions
    (no matching commit)
  - [v4,4/9] riscv: cpufeature: add zve32[xf] and zve64[xfd] isa detection
    (no matching commit)
  - [v4,5/9] dt-bindings: riscv: add Zve32[xf] Zve64[xfd] ISA extension description
    (no matching commit)
  - [v4,6/9] riscv: hwprobe: add zve Vector subextensions into hwprobe interface
    (no matching commit)
  - [v4,7/9] riscv: vector: adjust minimum Vector requirement to ZVE32X
    (no matching commit)
  - [v4,8/9] hwprobe: fix integer promotion in RISCV_HWPROBE_EXT macro
    https://git.kernel.org/riscv/c/5ea6764d9095
  - [v4,9/9] selftest: run vector prctl test for ZVE32X
    (no matching commit)

You are awesome, thank you!
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