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From: patchwork-bot+linux-riscv@kernel.org
To: yu fangyu <fangyu.yu@linux.alibaba.com>
Cc: linux-riscv@lists.infradead.org, joro@8bytes.org,
	will@kernel.org, robin.murphy@arm.com, pjw@kernel.org,
	palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr,
	tjeznach@rivosinc.com, jgg@ziepe.ca, kevin.tian@intel.com,
	baolu.lu@linux.intel.com, vasant.hegde@amd.com,
	anup@brainfault.org, atish.patra@linux.dev, skhawaja@google.com,
	jgg@nvidia.com, nutty.liu@hotmail.com, guoren@kernel.org,
	andrew.jones@oss.qualcomm.com, kvm@vger.kernel.org,
	iommu@lists.linux.dev, kvm-riscv@lists.infradead.org,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH v4 0/2] iommu/riscv: Support Svpbmt memory types in generic_pt
Date: Fri, 26 Jun 2026 08:21:00 +0000	[thread overview]
Message-ID: <178246206005.3816447.8810357368655365502.git-patchwork-notify@kernel.org> (raw)
In-Reply-To: <20260512074142.16356-1-fangyu.yu@linux.alibaba.com>

Hello:

This series was applied to riscv/linux.git (fixes)
by Joerg Roedel <joerg.roedel@amd.com>:

On Tue, 12 May 2026 15:41:40 +0800 you wrote:
> From: Fangyu Yu <fangyu.yu@linux.alibaba.com>
> 
> RISC-V Svpbmt adds page-based memory types (PBMT) to PTEs, allowing
> mappings to be tagged as e.g. normal memory, non-cacheable memory, or
> I/O.
> 
> This series wires the RISC-V IOMMU Svpbmt capability into generic_pt
> and uses PBMT to encode device memory attributes for IOMMU mappings.
> 
> [...]

Here is the summary with links:
  - [v4,1/2] iommu/riscv: Advertise Svpbmt support to generic page table
    https://git.kernel.org/riscv/c/f196a8668797
  - [v4,2/2] iommupt: Encode IOMMU_MMIO/IOMMU_CACHE via RISC-V Svpbmt bits
    (no matching commit)

You are awesome, thank you!
-- 
Deet-doot-dot, I am a bot.
https://korg.docs.kernel.org/patchwork/pwbot.html



WARNING: multiple messages have this Message-ID (diff)
From: patchwork-bot+linux-riscv@kernel.org
To: yu fangyu <fangyu.yu@linux.alibaba.com>
Cc: linux-riscv@lists.infradead.org, joro@8bytes.org,
	will@kernel.org, robin.murphy@arm.com, pjw@kernel.org,
	palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr,
	tjeznach@rivosinc.com, jgg@ziepe.ca, kevin.tian@intel.com,
	baolu.lu@linux.intel.com, vasant.hegde@amd.com,
	anup@brainfault.org, atish.patra@linux.dev, skhawaja@google.com,
	jgg@nvidia.com, nutty.liu@hotmail.com, guoren@kernel.org,
	andrew.jones@oss.qualcomm.com, kvm@vger.kernel.org,
	iommu@lists.linux.dev, kvm-riscv@lists.infradead.org,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH v4 0/2] iommu/riscv: Support Svpbmt memory types in generic_pt
Date: Fri, 26 Jun 2026 08:21:00 +0000	[thread overview]
Message-ID: <178246206005.3816447.8810357368655365502.git-patchwork-notify@kernel.org> (raw)
In-Reply-To: <20260512074142.16356-1-fangyu.yu@linux.alibaba.com>

Hello:

This series was applied to riscv/linux.git (fixes)
by Joerg Roedel <joerg.roedel@amd.com>:

On Tue, 12 May 2026 15:41:40 +0800 you wrote:
> From: Fangyu Yu <fangyu.yu@linux.alibaba.com>
> 
> RISC-V Svpbmt adds page-based memory types (PBMT) to PTEs, allowing
> mappings to be tagged as e.g. normal memory, non-cacheable memory, or
> I/O.
> 
> This series wires the RISC-V IOMMU Svpbmt capability into generic_pt
> and uses PBMT to encode device memory attributes for IOMMU mappings.
> 
> [...]

Here is the summary with links:
  - [v4,1/2] iommu/riscv: Advertise Svpbmt support to generic page table
    https://git.kernel.org/riscv/c/f196a8668797
  - [v4,2/2] iommupt: Encode IOMMU_MMIO/IOMMU_CACHE via RISC-V Svpbmt bits
    (no matching commit)

You are awesome, thank you!
-- 
Deet-doot-dot, I am a bot.
https://korg.docs.kernel.org/patchwork/pwbot.html



-- 
kvm-riscv mailing list
kvm-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/kvm-riscv

WARNING: multiple messages have this Message-ID (diff)
From: patchwork-bot+linux-riscv@kernel.org
To: yu fangyu <fangyu.yu@linux.alibaba.com>
Cc: linux-riscv@lists.infradead.org, joro@8bytes.org,
	will@kernel.org, robin.murphy@arm.com, pjw@kernel.org,
	palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr,
	tjeznach@rivosinc.com, jgg@ziepe.ca, kevin.tian@intel.com,
	baolu.lu@linux.intel.com, vasant.hegde@amd.com,
	anup@brainfault.org, atish.patra@linux.dev, skhawaja@google.com,
	jgg@nvidia.com, nutty.liu@hotmail.com, guoren@kernel.org,
	andrew.jones@oss.qualcomm.com, kvm@vger.kernel.org,
	iommu@lists.linux.dev, kvm-riscv@lists.infradead.org,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH v4 0/2] iommu/riscv: Support Svpbmt memory types in generic_pt
Date: Fri, 26 Jun 2026 08:21:00 +0000	[thread overview]
Message-ID: <178246206005.3816447.8810357368655365502.git-patchwork-notify@kernel.org> (raw)
In-Reply-To: <20260512074142.16356-1-fangyu.yu@linux.alibaba.com>

Hello:

This series was applied to riscv/linux.git (fixes)
by Joerg Roedel <joerg.roedel@amd.com>:

On Tue, 12 May 2026 15:41:40 +0800 you wrote:
> From: Fangyu Yu <fangyu.yu@linux.alibaba.com>
> 
> RISC-V Svpbmt adds page-based memory types (PBMT) to PTEs, allowing
> mappings to be tagged as e.g. normal memory, non-cacheable memory, or
> I/O.
> 
> This series wires the RISC-V IOMMU Svpbmt capability into generic_pt
> and uses PBMT to encode device memory attributes for IOMMU mappings.
> 
> [...]

Here is the summary with links:
  - [v4,1/2] iommu/riscv: Advertise Svpbmt support to generic page table
    https://git.kernel.org/riscv/c/f196a8668797
  - [v4,2/2] iommupt: Encode IOMMU_MMIO/IOMMU_CACHE via RISC-V Svpbmt bits
    (no matching commit)

You are awesome, thank you!
-- 
Deet-doot-dot, I am a bot.
https://korg.docs.kernel.org/patchwork/pwbot.html



_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

  parent reply	other threads:[~2026-06-26  8:21 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-05-12  7:41 [PATCH v4 0/2] iommu/riscv: Support Svpbmt memory types in generic_pt fangyu.yu
2026-05-12  7:41 ` fangyu.yu
2026-05-12  7:41 ` fangyu.yu
2026-05-12  7:41 ` [PATCH v4 1/2] iommu/riscv: Advertise Svpbmt support to generic page table fangyu.yu
2026-05-12  7:41   ` fangyu.yu
2026-05-12  7:41   ` fangyu.yu
2026-05-12  7:41 ` [PATCH v4 2/2] iommupt: Encode IOMMU_MMIO/IOMMU_CACHE via RISC-V Svpbmt bits fangyu.yu
2026-05-12  7:41   ` fangyu.yu
2026-05-12  7:41   ` fangyu.yu
2026-05-12 13:34 ` [PATCH v4 0/2] iommu/riscv: Support Svpbmt memory types in generic_pt Jörg Rödel
2026-05-12 13:34   ` Jörg Rödel
2026-05-12 13:34   ` Jörg Rödel
2026-05-12 14:50   ` fangyu.yu
2026-05-12 14:50     ` fangyu.yu
2026-05-12 14:50     ` fangyu.yu
2026-06-26  8:21 ` patchwork-bot+linux-riscv [this message]
2026-06-26  8:21   ` patchwork-bot+linux-riscv
2026-06-26  8:21   ` patchwork-bot+linux-riscv

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